Class / Patent application number | Description | Number of patent applications / Date published |
327258000 | Multiple outputs | 11 |
20080265965 | Electronic Module - The invention relates to an electronic module ( | 10-30-2008 |
20100052757 | COOPERATION CIRCUIT - The present invention discloses a cooperation circuit, comprising: a first control module, capable of generating a first control signal and a second control signal, the pulse width of the first control signal being determined by the pulse width of the second control signal; and a second control module, coupled to the first control module to receive the first control signal and the second control signal and generate a third control signal according to the first control signal and the second control signal; wherein, according to the first control signal and the second control signal, the second control module enables the third control signal and the second control signal to exhibit the same frequency and the same duty cycle with a phase delay. | 03-04-2010 |
20100315145 | APPARATUS FOR GENERATING A PLURALITY OF SIGNALS - An apparatus for generating a plurality of signals is provided. The apparatus provided includes a first signal generation unit, including an input receiving a reference signal, and a plurality of outputs providing a first plurality of output signals being generated based on the reference signal, wherein any two of the output signals have a different phase. The apparatus provided further includes a second signal generation unit, including at least two inputs receiving at least two signals selected from the first plurality of output signals generated by the first signal generation unit, and a plurality of outputs providing a second plurality of output signals generated by interpolating the respective phases of the received at least two signals selected from the first plurality of output signals. The apparatus provided further includes a selection unit, including a first plurality of inputs receiving the first plurality of output signals generated by the first signal generation unit, a second plurality of inputs receiving the second plurality of output signals generated by the second signal generation unit, and a plurality of outputs providing the plurality of signals wherein each of the signals is selected from the first plurality of output signals generated by the first signal generation unit and the second plurality of output signals generated by the second signal generation unit, wherein any two signals of the plurality of signals have a different phase. | 12-16-2010 |
20110298518 | PHASE INTERPOLATION CIRCUIT SUITABLE FOR WIDE RANGE FREQUENCY INPUT AND OUTPUT CHARACTERISTICS STABILIZING METHOD THEREOF - A phase interpolation circuit includes a waveform shaping unit and a phase interpolator. The waveform shaping unit adaptively waveform-shapes first or second phase offset input clock signal pair that is applied, to output first and second buffered clock signals having a rising time and falling time each of more than about a quarter of a period of the first and second offset input clock signals. The phase interpolator is applied to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal. | 12-08-2011 |
20130307603 | CIRCUT AND METHOD FOR GENERATING PERIODIC CONTROL SIGNALS, AND MICROSCOPE AND METHOD FOR CONTROLLING A MICROSCOPE - A circuit is configured to generate periodic control signals including at least two mutually phase-shifted control signals. The circuit includes a plurality of generator circuits, where a separate generator circuit is provided for each control signal output by the circuit. Each generator circuit includes a phase value memory configured to store a phase value, where the phase value defines a phase shift. Each generator circuit includes an activation input and, in response to application of an activation level to the activation input, is configured to initiate a generation of a control signal which is phase-shifted by an amount defined by the phase value. The activation inputs of the generator circuits are connected together to an activation circuit for outputting an activation level to the generator circuits simultaneously. | 11-21-2013 |
20140176214 | PHASE SPLITTER - A phase splitter includes: a first signal path; and a second signal path, wherein the phase splitter outputs an internal signal of the first signal path as a first phase signal, and mixes an output signal of the first signal path with an output signal of the second signal path, thereby outputting a second phase signal having a predetermined phase difference from the first phase signal. | 06-26-2014 |
20140266370 | Multi-Stage Delay-Locked Loop Phase Detector - A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another. | 09-18-2014 |
20140266371 | MULTI-PHASE GENERATOR - A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units. | 09-18-2014 |
327259000 | Non-overlapping | 3 |
20090066389 | Power Controlling Apparatus Applied to Biochip and Operating Method Thereof - The invention discloses a power controlling apparatus for a biochip including M regions. Each region includes a plurality of cells respectively. The power controlling apparatus includes a pulse generating module, a combinational circuit, and M controlling modules. The pulse generating module generates a pulse. The combinational circuit receives the pulse and generates M controlling signals. Each controlling signal has a predetermined phase which is different from the phase of the other controlling signal. The M controlling modules are electrically connected to the combinational circuit. Each of the M controlling signals corresponds to and activates one of the M controlling modules to selectively power on one corresponding region of the M regions. The cells in the corresponding region which is powered have an action potential refractory time that is longer than the power-on interval of the corresponding region. | 03-12-2009 |
20090315604 | CLOCK SIGNAL GENERATION APPARATUS AND DISCRETE-TIME CIRCUIT - In a clock signal generation apparatus, a clock signal delay calculation section has a delay detection circuit for monitoring the delay characteristics of the variable delay circuits of a clock signal generation circuit due to external variation factors and calculates the delay amounts of N-phase clock signals, and a clock signal delay control section varies the delay amounts of the variable delay circuits on the basis of delay variation data, external variation factors being used as parameters thereof, stored in a delay variation data section and the calculated delay amounts of the N-phase clock signals. In the case that, for example, clock signals required for a discrete-time circuit have changed due to external variation factors, such as power supply voltage and environmental temperature, the non-overlap times and the duty ratios of the clock signals required for the discrete-time circuit can be set to optimal values. | 12-24-2009 |
20130187696 | CIRCUIT FOR GENERATING MULTI-PHASE NON-OVERLAPPING CLOCK SIGNALS - A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals. | 07-25-2013 |