| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327170000 | Slope control of leading or trailing edge of rectangular (e.g., clock, etc.) or pulse waveform | 87 |
| 20080252348 | Apparatus and method for high speed signals on a printed circuit board - In some embodiments, an apparatus includes a printed circuit board substrate, a copper signal line disposed on the printed circuit board substrate, and a nonlinear transmission structure coupled to the copper signal line, wherein the nonlinear transmission structure is configured to sharpen a wavefront of a high speed signal pulse on the copper signal line. In some embodiments, the nonlinear transmission structure may include a voltage dependent dielectric layer on the printed circuit board substrate. In some embodiments, the voltage dependent dielectric layer may include a plurality of varactors positioned at a receiving end of the signal line. | 10-16-2008 |
| 20080278207 | FALL TIME ACCELERATOR CIRCUIT - Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus. | 11-13-2008 |
| 20080278208 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit includes a data output clock signal generating unit that generates a rising data output clock signal and a rising latch signal from a rising clock signal in response to a falling latch signal, and generates a falling data output clock signal and the falling latch signal from a falling clock signal in response to the rising latch signal; and a data output pre-driver that drives a rising data in response to the rising data output clock signal, and drives a falling data in response to the falling data output clock signal. | 11-13-2008 |
| 20080309390 | Multi-Mode Digital-to-Analog Converter - Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus for supplying a reference signal, including a digital-to-analog converter, a counter and a clock. The digital-to-analog converter has a digital input and an analog output that supplies a reference signal based on the digital input. The counter has a digital control word input, a clock input, a clock enable output and a count output connected to the digital input of the digital-to-analog converter. The counter is adapted to assert the clock enable output when the digital control word input requests an output count that is different from an actual count at the count output of the counter. The clock has an enable input connected to the clock enable output of the counter and a clock output connected to the clock input of the counter. The clock is adapted to produce clock pulses on the clock output while the enable input is asserted. | 12-18-2008 |
| 20090027096 | DC BRUSHED MOTOR DRIVE WITH CIRCUIT TO REDUCE DI/DT AND EMI, FOR MOSFET VTH DETECTION, VOLTAGE SOURCE DETECTION, AND OVERPOWER PROTECTION - A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals Vth. | 01-29-2009 |
| 20090045860 | Apparatus and method for two tier output stage for switching devices - A circuit for reducing EMI is provided. The circuit includes driver circuitry that drives a power switch, such as a power MOSFET. The power switch provides an output voltage. The circuit decreases the drive strength by which the power switch is driven during each output edge (i.e. when the output goes from low to high (rising edge) or high to low (falling edge)), and returns the drive strength to its normal level when the output edge is complete or approximately complete. Reducing the drive strength of the driver circuitry causes the output edge to occur over a longer period of time. This results in reduction of the EMI of the device. | 02-19-2009 |
| 20090058480 | SCHEME FOR CONTROLLING RISE-FALL TIMES IN SIGNAL TRANSITIONS - A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry. | 03-05-2009 |
| 20090066381 | EDGE RATE CONTROL FOR I2C BUS APPLICATIONS | 03-12-2009 |
| 20090096500 | SKEW COMPENSATION CIRCUIT - The present invention describes a skew compensation circuit that can compensate for changes in signal skew in response to changes in external environments and processes. The skew compensation circuit includes a controller for outputting a control signal according to whether an external power supply is supplied and its operation mode. The skew compensation circuit also includes a signal output unit which selects either a normal path or a skew reduction path according to the control signal and outputs an input signal through the selected path. | 04-16-2009 |
| 20090146714 | DRIVER CIRCUIT - A driver circuit facilitates reducing noises and losses and improving the driving performances thereof without connecting a series circuit of capacitor and a resistor to the gate of IGBT. The driver circuit includes a slope setting circuit that sets the gate voltage waveform of IGBT; and an operational amplifier that includes a non-inverting input terminal, to which an output voltage V* from slope setting circuit is inputted, and an inverting input terminal, to which a divided voltage Vgsf divided by resistors is inputted; and the operational amplifier outputs an output voltage Vout, proportional to the difference between the output voltage V* and the divided voltage Vgsf, to the gate of IGBT. | 06-11-2009 |
| 20090160514 | Chip structure capable of smoothing slope of signal during conversation - The present invention discloses a chip structure capable of smoothing slope of signal during conversion. And the chip structure is suitable for a DC motor which is embedded in a portable electronic device. The DC motor is for adjusting the focal distance of a digital camera which is installed within the portable electronic device. The chip structure comprises an input terminal, a first converter, a control unit, a second converter, an amplifier circuit and an output terminal. The input terminal is for receiving a first digital signal. The first converter is for converting the first digital signal into an analog signal. The control unit is for elongating the transform time of the analog signal. The amplifier circuit is for amplifying the elongated analog signal. The second converter is for converting the elongated analog signal into a second digital signal. And the output terminal outputs the second digital signal. | 06-25-2009 |
| 20090167391 | QUARTER CYCLE DELAY CLOCK GENERATOR - Embodiments relate to a quarter cycle delay clock generator. According to embodiments, a quarter cycle delay clock generator may include a reference clock generator to generate a reference clock signal, a first logic circuit to catch a first input signal input thereto at a rising edge of the reference clock signal and outputting a first input signal as a first output signal until a next rising edge of the reference clock signal, and a second logic circuit to catch a second input signal input thereto and outputting the second input signal as a second output signal. The first output signal may be inverted and input to the first logic circuit as the first input signal, and the second logic circuit may receive the first output signal from the first logic circuit as the second input signal. | 07-02-2009 |
| 20090174449 | DRIVING CIRCUIT SLEW RATE COMPENSATION METHOD - An apparatus for compensating slew rate of a driving circuit includes: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ideal edge transition of the driving circuit and generating a second pulse proportional to an ideal slope of the ideal edge transition; a comparison circuit, coupled to the first circuit and the second circuit, for comparing an extreme value of amplitude of the first pulse with an extreme value of amplitude of the second pulse to produce a comparison signal; and a control circuit, coupled to the comparison circuit, for increasing or decreasing the slew rate of the driving circuit according to the comparison signal. | 07-09-2009 |
| 20090179679 | SLEW-RATE CONTROL CIRCUITRY WITH OUTPUT BUFFER AND FEEDBACK - The present invention proposed a slew-rate control circuitry without the use of external components such as amplifiers. Therefore slew-rate control circuitry of the present invention not only provides an IC with build-in slew-rate control, but also reduces number of transistors used externally which will increase gate-oxide reliability of the IC. The slew-rate control circuitry of the present invention is primarily comprised by an output buffer and feedback circuitry, the output buffer mainly consisted four transistors and depends on output of the IC, these four transistors will interact with each other to control the slew-rate of IC output. Additional feedback circuitry and gate-tracking circuitry are also disclosed to enhance the performance of the slew-rate control circuitry. | 07-16-2009 |
| 20090206899 | SYSTEM FOR CONTROLLING A SIGNAL SLEW RATE IN A DIGITAL DEVICE - A system for controlling a slew rate of a signal, such as used in an imaging device, comprises a counter for measuring a duration that the signal drops from a maximum voltage to a predetermined reference voltage; a register for retaining a desired duration that the signal drops from the maximum voltage to the predetermined reference voltage; and a comparator for comparing the measured duration to the desired duration, the comparator being operative of a current source for the signal. An anti-oscillation circuit prevents the system from oscillating between two discrete durations. | 08-20-2009 |
| 20090243682 | METHOD, SYSTEM AND DEVICE FOR ELIMINATING INTRA-PAIR SKEW - A method, system and device for eliminating intra-pair skew are disclosed. The method includes: measuring a phase difference between the received differential signals as a transmission delay difference; and compensating delays of the differential signals using the transmission delay difference, to eliminate intra-pair skew of the differential signals. A phase difference measuring apparatus is used to measure a phase difference between the differential signals as the transmission delay difference, so that the transmission delay difference may be adjusted according to the phase difference. Therefore, the procedure for eliminating intra-pair skew is effectively simplified, and the effect of adjusting the transmission delay difference is improved. | 10-01-2009 |
| 20090284292 | SIGNAL ADJUSTMENT RECEIVER CIRCUITRY - Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block. | 11-19-2009 |
| 20090289678 | METHOD OF CONTROL SLOPE REGULATION AND CONTROL SLOPE REGULATION APPARATUS - A control loop has a control slope associated therewith. The control loop is provided to control a unit under control. A method of regulating the control slope comprises the step of measuring the control slope of the control loop and modifying a parameter associated with the unit under control in order to maintain the control slope within a desired range. Lock of the control loop is therefore maintained. | 11-26-2009 |
| 20090295443 | System and Method For Modifying Signal Characteristics - The present invention embodiments provide a system to modify signal characteristics to produce a desired signal. The system comprises a signal module to modify signal characteristics. The signal module includes at least one input to receive an input signal including a substantially rectangular signal and one or more control signals and an output to provide a substantially trapezoidal signal. A signal unit of the signal module adjusts characteristics of the substantially rectangular signal including leading and/or trailing edges of that signal in accordance with the one or more control signals to produce the substantially trapezoidal signal. The present invention embodiments further include a probe card and method to adjust signal characteristics as described above. | 12-03-2009 |
| 20090322393 | EDGE-TIMING ADJUSTMENT CIRCUIT - According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner. | 12-31-2009 |
| 20090322394 | RING OSCILLATOR AND MULTI-PHASE CLOCK CORRECTION CIRCUIT USING THE SAME - A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage. | 12-31-2009 |
| 20100052755 | SLEW RATE CONTROL FOR A LOAD SWITCH - An apparatus for slew rate control using a plurality of discrete slew rate levels. The apparatus includes a load switch and a switch controller. The load switch outputs a load voltage to a load. The switch controller generates a switch control signal in response to an enable signal. The switch control signal controls operation of the load switch. The switch controller controls a slew rate of the load switch according to a plurality of discrete slew rate levels. | 03-04-2010 |
| 20100073055 | INVERTING ZIPPER REPEATER CIRCUIT - Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described. | 03-25-2010 |
| 20100090738 | Circuit and Method for Clock Skew Compensation in Voltage Scaling - Circuit and methods for automatic clock skew compensation in circuits having two power domains. When one of the power domains is operated with a lowered supply voltage, lowering the supply voltage tends to slow the clock pulse and produces clock skew. Circuitry is provided for selectively delaying the clock pulse in one of the power domains to reduce the clock skew by comparing the clock pulses, and then automatically delaying the clock pulse in one of the domains by a delay determined to minimize the skew. A method is provided where the clock skew between two clock pulses is determined and the delay needed in one of the clock pulses to reduce the skew is determined by sampling the clock skew using a plurality of delays at multiples of a minimum delay, and then automatically delaying the one clock pulse by selecting an appropriate delay. The method may be iterated. | 04-15-2010 |
| 20100102864 | TRANSMISSION CIRCUIT - A transmission circuit including a first circuit outputting a first signal based on an input data, a second circuit outputting a second signal based on the input data, where each of the first signal and the second signal functions as a differential signal, a correction circuit generating a correction signal for correcting variation in current drive capabilities of two transistors of a first buffer included in at least one of the first circuit and the second circuit, and a second buffer coupled in parallel with the first buffer and reducing, based on the correction signal, the variation in the current drive capabilities of the two transistors. | 04-29-2010 |
| 20100123500 | INTEGRATED CIRCUIT - An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured to route the input signal to one of the pull-up compensation unit and the pull-down compensation unit in response to a conditional signal. | 05-20-2010 |
| 20100141319 | CLOCK SIGNAL OUTPUT CIRCUIT - A clock signal output circuit includes a clock signal source which produces a clock signal, a buffer circuit which drives the clock signal while adjusting rise and fall times of the clock signal according to control signals, a rise-time frequency generator, responsive to the control signals, which produces a rise-time signal having a frequency corresponding to the rise time given by the buffer circuit, a fall-time frequency generator, responsive to the control signals, which produces a fall-time signal having a frequency corresponding to the fall time given by the buffer circuit, and a control signal generator which produces the control signals, based on the frequencies of the rise-time signal and fall-time signal. | 06-10-2010 |
| 20100148834 | ENHANCED PREDISTORTION FOR SLEWING CORRECTION - The present invention relates to a circuit arrangement and method of applying predistortion to a baseband signal used for modulating a pulse-shaped signal, wherein an envelope information of the baseband signal is detected and slewing distortions of the pulse-shaped signal are reduced by applying at least one of a phase modulation and a duty cycle | 06-17-2010 |
| 20100171538 | BUFFER FOR DRIVING CIRCUIT AND METHOD THEREOF - A buffer for a driving circuit includes a first transistor, a second transistor and a slew rate controlling circuit. The first transistor serves to provide a current to an output terminal. The second transistor serves to sink a current from the output terminal. The slew rate controlling circuit serves to control slew rate of at least one of the first transistor and the second transistor according to the input signal. The managing circuit serves to prevent the first transistor and the second transistor from turning on simultaneously. | 07-08-2010 |
| 20100171539 | SLEW RATE CONTROL CIRCUIT - A slew rate control circuit is disclosed. An output impedance buffer and a slew rate buffer are coupled in parallel. An edge detector detects an input signal to accordingly control the output impedance buffer and the slew rate buffer, such that the input signal passes through the slew rate buffer during a rising or falling time period, and the input signal only passes through the output impedance buffer during a stable time period, thereby conforming to specification requirements for the slew rate and the output impedance at the same time. | 07-08-2010 |
| 20100176856 | METHOD AND APPARATUS FOR DETECTING AND ADJUSTING CHARACTERISTICS OF A SIGNAL - Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range. | 07-15-2010 |
| 20100237919 | METHOD AND SYSTEM FOR A SIGNAL DRIVER USING CAPACITIVE FEEDBACK - Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor ( | 09-23-2010 |
| 20100264970 | EDGE RATE CONTROL FOR I2C BUS APPLICATIONS - Consistent with an example embodiment, an edge-rate control circuit arrangement ( | 10-21-2010 |
| 20100271096 | WAVEFORM PROCESSING CIRCUIT - A rising edge or a falling edge is finely adjusted, or a dead time and a period are adjusted with high accuracy. A waveform processing circuit includes: an integration circuit | 10-28-2010 |
| 20100327928 | METHOD AND APPARATUS TO IMPROVE AND CONTROL THE PROPAGATION DELAY IN A CURRENT SLEWING CIRCUIT - A circuit for independently controlling slew and propagation delay of a current DAC is provided. The circuit applies dual slope technique with feed-back control the gate (or control electrode) of a switching transistor to make propagation delay independent control from rise/fall slew rate. This allows one to adjust propagation delay and current slew rate separately to achieve better performance. | 12-30-2010 |
| 20110025391 | Methods and Systems for Measuring and Reducing Clock Skew - A technique for a delay measurement system to measure the skews in a clock distribution network is presented. It uses the principle of sub-sampling to measure and amplify small clock skews and determine an estimate of clock skew by further manipulation if these sampled measurements. The technique can be applied to measure clock skew on a computer chip, between bit-line of a communication bus, or between elements connected by an electronic or optical interconnect. | 02-03-2011 |
| 20110084745 | OUTPUT BUFFER WITH SLEW-RATE ENHANCEMENT OUTPUT STAGE - An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage. | 04-14-2011 |
| 20110084746 | EDGE RATE CONTROL - This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal. | 04-14-2011 |
| 20110109361 | Semiconductor device and information processing system - The semiconductor device includes an output driver and a characteristic switching circuit that switches characteristics of the output driver. The characteristic switching circuit mutually matches a rising time and a falling time of an output signal output from the output driver, when a power voltage supplied to a power line is a first voltage, with a rising time and a falling time of the output signal output from the output driver, when the power voltage supplied to the power line is a second voltage. As a result, an increase in an influence of a harmonic component or a crosstalk when the power voltage is reduced does not occur. Moreover, because a receiving condition on a receiver side does not change even when the power voltage is reduced, signal transmission and reception can be performed correctly irrespective of the power voltage. | 05-12-2011 |
| 20110115537 | CIRCUIT DEVICES AND METHODS FOR RE-CLOCKING AN INPUT SIGNAL - Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate. | 05-19-2011 |
| 20110148493 | OUTPUT SLEW RATE CONTROL - This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry. | 06-23-2011 |
| 20110279158 | SLEW RATE CONTROL CIRCUIT AND METHOD THEREOF AND SLEW RATE CONTROL DEVICE - A slew rate control circuit is provided. The slew rate control circuit includes at least one switch and an inverter. A first end of the switch is coupled to a power terminal. A toggle end of the switch is coupled to a first control terminal. A second end of the switch is coupled to an output terminal. An output end of the inverter is coupled to the output terminal. An input end of the inverter is coupled to an input terminal. A voltage at the first control terminal conducts the switch to reduce the slew rate when a large voltage variation occurs at the output terminal. A method of controlling a slew rate and a slew rate control device are provided. | 11-17-2011 |
| 20120013378 | SLEW RATE BOOST CIRCUIT, OUTPUT BUFFER HAVING THE SAME, AND METHOD THEREOF - A slew rate boost circuit for an output buffer and an output buffer circuit for a source driver having the same are provided. In an output buffer including a pull-up unit providing a buffer output signal in a first level by receiving a buffer input signal and performing pull-up operation and a pull-down unit providing a buffer output signal in a second level having opposite phase from the first level by receiving the buffer input signal and performing pull-down operation, the slew rate boost circuit includes a first comparator generating a first boost signal to boost pull-up operation of the pull-up unit of the output buffer by inputting a first input signal and a second input signal and a second comparator generating a second boost signal to boost pull-down operation of the pull-down unit of the output buffer by inputting the first input signal and the second input signal. | 01-19-2012 |
| 20120056655 | Method and system for controlling HS-NMOS power switches with slew-rate limitation - A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal. | 03-08-2012 |
| 20120161839 | INVERTING ZIPPER REPEATER CIRCUIT - Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described. | 06-28-2012 |
| 20120169390 | DRIVE STRENGTH ADJUSTMENT THROUGH VOLTAGE AUTO-SENSE - An integrated circuit supports auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power supply voltage of the peripheral device received during power-up of the MMP chip, power-up of the peripheral circuitry, and/or dynamically while the MMP is powered-up. The auto-sense pad may adjust drive strength of at least one other pad, which may be an output pad or a bidirectional pad, integrated on the MMP chip may be configured to operate using the determined output voltage. A rise time and/or fall time of signals output by the MMP chip may be varied by the adjustment of the drive strength. | 07-05-2012 |
| 20120206179 | OUTPUT CIRCUIT, SYSTEM INCLUDING OUTPUT CIRCUIT, AND METHOD OF CONTROLLING OUTPUT CIRCUIT - An output circuit includes a first transistor coupled to an external terminal and having a gate terminal that receives a first drive signal. The first transistor drives a potential at the external terminal in accordance with the first drive signal. The output circuit also includes a capacitor. The capacitor includes a first end coupled to the gate terminal of the first transistor. A clamp circuit clamps a second end of the capacitor to a potential corresponding to the operation of the first transistor. | 08-16-2012 |
| 20130147532 | SLEW RATE MODULATION - Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described. | 06-13-2013 |
| 20130154704 | Method and System for Compensating Mode Conversion Over a Communications Channel - A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power. | 06-20-2013 |
| 20130176064 | ELECTRONIC CHIPS WITH SLEW-RATE CONTROL AT OUTPUT SIGNALS - Electronic chips with slew-rate control at output signals are disclosed. A disclosed electronic chip includes a slew-rate control circuit and slew-rate control charging and discharging transistors wherein the transistors are coupled at an output pin of the electronic chip. According to an input signal for an output stage of the electronic chip and a signal at the output pin, the slew-rate control circuit generates the slew-rate control charging and discharging signals to separately control the slew-rate control charging and discharging transistors to charge/discharge a load capacitance at the output pin. | 07-11-2013 |
| 20130187695 | CIRCUIT CONFIGURATION AND METHOD FOR LIMITING CURRENT INTENSITY AND/OR EDGE SLOPE OF ELECTRICAL SIGNALS - A circuit configuration for the limiting of current intensity and/or the edge slope of electrical signals includes: a voltage source; a switching element connected to the voltage source and equipped for switching the voltage source; and a limiting unit functionally positioned between the switching element and the voltage source, the limiting unit being equipped to limit a current intensity and/or an edge slope of an electrical signal in response to a switching process of the voltage source while using the switching element. | 07-25-2013 |
| 20130194014 | RECEIVER CIRCUIT - A receiver circuit includes a buffering unit configured to buffer an input signal and generate a buffering signal; a variation detection unit configured to generate a control signal according to a level of a reference voltage; a driving unit configured to drive the buffering signal and generate an output signal; and a compensation unit configured to control a slew rate of the output signal in response to the control signal. | 08-01-2013 |
| 20130222028 | METHOD AND APPARATUS FOR LOAD SWITCH CONTROLLER - A power control device can generate control signals to control operation of power sources. Additional control signals control operation of load switches that can be connected to the power sources to provide secondary sources of power. The load switches can be turned in a gradual manner at rates that depend on the power sources to which they are connected. The outputs of the load switches can be monitored for overvoltage and undervoltage conditions relative to the power sources to which they are connected. | 08-29-2013 |
| 20130234768 | BOOSTING CIRCUIT - A boosting circuit is provided which performs an appropriate boosting operation in accordance with load capacitance. In the boosting circuit, a slope control circuit is provided between a limiter circuit, which limits a high voltage obtained by a charge pump circuit to a desired boosted voltage VPP, and a discharge circuit, which makes the boosted voltage VPP drop quickly to a power supply voltage VCC after the completion of writing, to enable a boosting operation in an appropriate boosted-voltage reach time, by increasing the time taken to reach the boosted voltage VPP in the case where the load capacitance is low, while keeping the time taken to reach the boosted voltage VPP unchanged, irrespective of the presence/absence of the slope control circuit, in the case where the load capacitance is high as in the case of selecting the memory cells collectively. | 09-12-2013 |
| 20130249613 | SEMICONDUCTOR DEVICE AND INPUT SIGNAL RECEPTION CIRCUIT - A semiconductor device according to the present invention includes an input circuit that is connected between an input node and an output node and that changes a level of the output node corresponding to a signal supplied to the input node, wherein when a control signal represents a first mode, a speed at which input circuit changes the level of the output node from a first level to a second level is greater than the speed at which input circuit changes the level of the output node from the second level to the first level and when the control signal represents a second mode, the speed at which input circuit changes the level of the output node from the second level to the first level is greater than the speed at which the input circuit changes the level of the output node from the first level to the second level. | 09-26-2013 |
| 20130257498 | Pulse Clock Generation Logic with Built-in Level Shifter and Programmable Rising Edge and Pulse Width - Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation. | 10-03-2013 |
| 20140015580 | SEMICONDUCTOR DEVICE AND A POWER MANAGEMENT DEVICE USING THE SAME - A semiconductor device including, a slope signal generator configured to generate a slope signal, an error signal generator configured to generate an error signal in response to an output voltage, a pulse width modulation (PWM) signal generator configured to generate a PWM signal using a difference between the slope signal and the error signal, and a slope signal controller configured to adjust the slope signal according to a difference between the output voltage and a reference voltage. | 01-16-2014 |
| 20140021994 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V | 01-23-2014 |
| 20140035643 | EQUALIZED RISE AND FALL SLEW RATES FOR A BUFFER - Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer. | 02-06-2014 |
| 20140043076 | Pulsed Gate Driver - A gate driver includes a control input receiving a control signal, an output to provide an amplified output signal to the gate, and controller. The controller produces an adaptive pulse train varying with the control signal. An adaptive incrementer produces a sequence of numbers that set a slew rate of the switch, and a look-up table is fed with the sequence of numbers, and associates the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal to control the slew rate of the switch. The switch can be driven at various intermediate levels, and allows gate drive conditions to adapted to abnormal system states by varying the control input signal. The adaptive response allows the slew rate to vary without replacing any gate driver circuit components. Because the gate current is provided adaptively, the delivery of gate current results in low power dissipation. | 02-13-2014 |
| 20140043077 | Method and System for Controlling HS-NMOS Power Switches with Slew-Rate Limitation - A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal. | 02-13-2014 |
| 20140062557 | METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME - Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result. | 03-06-2014 |
| 20140062558 | CURRENT MODE CONTROLLED POWER CONVERTER - A current mode controlled power converter controllable in a digitally processing current mode even during an on time. In the power converter, each control period based on a reference signal includes a slope calculation period in which a slope compensation signal for the control period is calculated by a slope compensation unit. During each slope calculation period, the slope compensation unit negates the slope compensation signal calculated previous to the control period including the slope calculation period, and a reset signal generation unit compares a current detection signal detected by a current detection unit with a current instruction set to an error signal generated by an error signal generation unit to generate a reset signal. | 03-06-2014 |
| 20140070860 | APPARATUSES INCLUDING SCALABLE DRIVERS AND METHODS - Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described. | 03-13-2014 |
| 20140103979 | METHOD AND SYSTEM FOR COMPENSATING MODE CONVERSION OVER A COMMUNICATIONS CHANNEL - A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power. | 04-17-2014 |
| 20140103980 | Method and Apparatus for Reducing the Contribution of Noise to Digitally Sampled Signals - The contribution of noise to digitally sampled signals is reduced using a statistical processor and a slope limiter. The statistical processor determines an average value (mean and/or standard deviation) of the filtered signal which is used to determine a slope limit corresponding to an expected maximum first derivative value of a target signal frequency. This slope limit is applied to constrain the output of an analog to digital converter, to prevent the output of the analog to digital converter from exceeding this maximum rate of rise or fall. By constraining the output of the analog to digital converter, it is possible to digitally sample analog signals without first utilizing an anti-aliasing filter, since the post processing of the digitally sampled signals limits the contribution of the higher frequency components of the signal to thereby enable a fully digital sampling and filtering circuit to be provided for receiving signals. | 04-17-2014 |
| 20140125388 | OPTIMIZING PRE-DRIVER CONTROL FOR DIGITAL INTEGRATED CIRCUITS - Disclosed is a wave shaping apparatus and a method for shaping an input pulse train signal alternating between a low level and a high level to provide a signal delaying a turn on of one output transistor with respect to a turn off of the other output transistor thus decreasing time, when both the transistors would be simultaneously conducting current. | 05-08-2014 |
| 20140125389 | EDGE RATE CONTROL GATE DRIVE CIRCUIT AND SYSTEM FOR LOW SIDE DEVICES WITH CAPACITOR - An apparatus, comprising: a PMOS current mirror have a first PFET and a second PFET coupled at their respective gates; a first current source coupled to drain of the first PFET; a second current source configured to have a current that is greater than the first current source, coupled to the drain of the second PFET; a capacitor coupled to the gates of the PFET current mirror; a third PFET gate-coupled to the current mirror; a driver NFET having a gate coupled to the drain of the third PFET, wherein a drain of the driver NFET is coupled to the capacitor. | 05-08-2014 |
| 20140167827 | Apparatus and Method For Slew Rate Control - The slew rate of a transistor is controlled. Upon a transition of a MOSFET control signal, an operating voltage of the MOSFET is measured and a determination of whether the voltage is between a predetermined set of values is made. Based upon the determination, a counter is incremented, and the count of the counter corresponding slew rate. The turn-on current of the MOSFET is controlled based upon the count. | 06-19-2014 |
| 20140176210 | OUTPUT DRIVER HAVING IMPROVED SWITCHING DELAY AND ASSOCIATED METHODS - A switching device for driving a load is provided. The switching device comprises a control terminal and has a conduction threshold which, when crossed by a control signal coupled to the control terminal, causes the switching device to conduct. A control circuit for generating the control signal is also provided. The control circuit is configured to generate a control signal having a first slew rate prior to the control signal crossing the conduction threshold and a second slew rate after the control signal has crossed the conduction threshold. The first slew rate may be faster than the second slew rate. | 06-26-2014 |
| 20140203855 | GATE LINE DRIVER CAPABLE OF CONTROLLING SLEW RATE THEREOF - A gate line driver including an output buffer configured to receive a driving signal and output a driving voltage, and a slew rate controller including at least one capacitor and a switch connected in series to the at least one capacitor, the switch configured to selectively, electrically connect the at least one capacitor between an input terminal and an output terminal of the output buffer according to a slew rate control signal to control a slew rate of the output buffer. | 07-24-2014 |
| 20140210533 | EDGE RATE CONTROL GATE DRIVE CIRCUIT AND SYSTEM FOR HIGH AND LOW SIDE DEVICES WITH LARGE DRIVER FET - An apparatus, comprising: a NFET current mirror having a first NFET and a second NFET; a PFET gate-coupled to the drain of the second NFET, wherein the PFET has a larger gain than the second NFET; a driver NFET having a gate that is coupled to the drain the PFET; wherein the second NFET is coupled through its source to the drain of the driver NFET. | 07-31-2014 |
| 20140218087 | Wide Bandwidth Resonant Global Clock Distribution - A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal. | 08-07-2014 |
| 20140253194 | LOAD SWITCH - An IC generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between input pin and output pin and receives a negative voltage through the input pin. The control circuitry is coupled to the enable pin, the ground pin, and the load switch and controls the load switch and uses ground pin as positive supply rail and input pin as an internal ground. Voltage applied to the input terminal is negative, enabling pulling of the gate of a transistor of a level shifter to ground turns transistor as “on,” enabling a negative output signal to be provided through output pin VOUT. Therefore, the output signal (at output pin VOUT) can be ground (applied to the ground pin GND) when the transistor is “off” and can be the negative voltage (applied to the input pin VIN) when transistor is “on.” | 09-11-2014 |
| 20140312949 | APPARATUS FOR OUTPUT BUFFERING HAVING HALF-SWING RAIL-TO-RAIL STRUCTURE - There is provided an apparatus for output buffering having a half-swing rail-to-rail structure. The apparatus provides output buffering by using a switch structure in order to attain a high slew rate and low power characteristics, thereby reducing current consumption. The provided apparatus for output buffering having a half-swing rail-to-rail structure includes a first output buffer, driven between a first voltage rail and a second voltage rail and outputting a first output signal in response to a first input signal and a second input signal, and a second output buffer, driven between the first and the second voltage rails and a third voltage rail and outputting a second output signal in response to a third input signal and a fourth input signal. | 10-23-2014 |
| 20140347111 | SLEW RATE CONTROL FOR MULTIPLE VOLTAGE DOMAINS - A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate. | 11-27-2014 |
| 20140368244 | APPARATUSES AND METHODS FOR DUTY CYCLE ADJUSTMENT - Apparatuses and methods for duty cycle adjustment are disclosed herein. An example apparatus may include a node, a phase mixer, and a duty cycle adjuster circuit. The phase mixer may have a first step duty cycle response and may be configured to provide a first output signal to the node in accordance with the first step duty cycle response. The duty cycle adjuster circuit may have a second step duty cycle response complementary to the first step duty cycle response and may be configured to provide a second signal to the node in accordance with the second step duty cycle response. | 12-18-2014 |
| 20150035574 | SLEW RATE CONTROL DEVICE USING SWITCHING CAPACITOR - Disclosed is a slew rate control device using a switching capacitor which includes a first capacitor that is connected to a target circuit operated in response to a clock signal, and controls a rising slope of a signal output from the target circuit when the clock signal is in a high state; a switch that is connected to the first capacitor in parallel, receives a reverse signal of the clock signal, as a control signal, and is turned on when the clock signal is in a low state; and a second capacitor that is connected to the switch in series, and controls a falling slope of the signal output from the target circuit when the clock signal is in the low state. | 02-05-2015 |
| 20150109041 | METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME - Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise. | 04-23-2015 |
| 20150137866 | APPARATUSES INCLUDING SCALABLE DRIVERS AND METHODS - Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described. | 05-21-2015 |
| 20150311893 | METHOD, APPARATUS AND SYSTEM FOR AN EDGE RATE CONTROLLED OUTPUT BUFFER - A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers. | 10-29-2015 |
| 20160072488 | VOLTAGE-DRIVER CIRCUIT WITH DYNAMIC SLEW RATE CONTROL - A system for circuit for generating an output signal with a dynamically adjustable slew rate includes a sampler, an envelope detector, an envelope comparison and control circuit, and a voltage-driver circuit that includes output buffers for generating the output signal. The sampler generates a sampled signal indicative of the slew rate of the output signal. The envelope detector generates an envelope detection signal indicative of a peak value of the sampled signal. The envelope comparison and control circuit compares a voltage level of the envelope detection signal with various threshold voltage levels, and generates control signals. The voltage-driver circuit controls the operation states of the output buffers based on the control signals to dynamically adjust the slew rate of the output signal. | 03-10-2016 |
| 20160161979 | Process Skew Resilient Digital CMOS Circuit - A digital CMOS circuit comprising at least one pull-up circuit arranged, when in an on-state, to switch an output node of the digital CMOS circuit from a first voltage level to a second voltage level within a rising transition delay. The digital CMOS circuit further comprises at least one pull-down circuit arranged, when in an on-state, to switch the voltage level of the output node of the digital CMOS circuit from the second voltage level to the first voltage level within a falling transition delay. The digital CMOS circuit further comprises at least one performance matching transistor serially connected to the first and second type transistors, the gate terminal of which is connected to biasing means arranged for biasing the at least one performance matching transistor in such a way so as to compensate for the performance mismatch between the at least one first and second type transistors. | 06-09-2016 |
| 20160164508 | APPARATUSES AND METHODS FOR ADJUSTING TIMING OF SIGNALS - Apparatuses and methods for adjusting timing of signals are described herein. An example method may include providing an output clock signal responsive to an input clock signal, and adjusting a slew rate of the output clock signal by a delayed output clock signal. | 06-09-2016 |
| 20160164509 | APPARATUSES AND METHODS FOR ADJUSTING TIMING OF SIGNALS - Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary. | 06-09-2016 |
| 20160182046 | CROSSTALK COMPENSATION CIRCUIT | 06-23-2016 |
| 20170237416 | SEMICONDUCTOR DEVICE AND COMMUNICATION MODULE | 08-17-2017 |
