| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327119000 | Frequency multiplication (e.g., harmonic generation, etc.) | 51 |
| 20080211549 | Fast Pulse Generator - A pulse generator including a pulsed switch ( | 09-04-2008 |
| 20080224742 | SMALL SCALE CLOCK MULTIPLIER CIRCUIT FOR FIXED SPEED TESTING - An on-chip clock multiplier for outputting a fast clock that is approximately a predetermined multiple n of a slow clock. The multiplier utilizing a high-speed oscillator to generate a high-frequency base signal. A lower frequency signal is generated using the high-frequency base signal as a function of the output of a rollover counter that counts from a seed value to a terminal value. A saturation counter is used to determine whether no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. If not, the lower frequency signal is iteratively slowed by changing the seed value until no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. When this iteration is done, the fast clock having a frequency that is approximately n times the frequency of the slow clock is output. | 09-18-2008 |
| 20080258783 | BROADBAND LOW NOISE COMPLEX FREQUENCY MULTIPLIERS - A frequency multiplier device including a plurality of multipliers, each of which has a first input port, a second input port and an output port; a first combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of the plurality of multipliers, the first combiner outputting a first output signal; and a second combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of the plurality of multipliers, the second combiner outputting a second output signal. The plurality of multipliers includes a first multiplier, a second multiplier, a third multiplier and a fourth multiplier, where the first multiplier has a first input port and a second input port and receives a first input signal at the first input port and the second input port; the second multiplier has a first input port and a second input port and receives a second input signal at the first input port and the second input port; the third multiplier has a first input port and a second input port and receives the second input signal at the first input port and the first input signal at the second input port; and the fourth multiplier has a first input port and a second input port and receives the first input signal at the first input port and the second input signal at the second input port. | 10-23-2008 |
| 20090015300 | Method and apparatus for producing a signal - Apparatus for producing a signal, comprising a capacitor; a first current source for one of charging and discharging the capacitor over a first time period; a second current source for one of discharging and charging the capacitor over a first portion of a second time period; a detector for detecting when the voltage across the capacitor is substantially a first voltage and controlling the second current source for a second portion of the second time period to substantially maintain the voltage across the capacitor; and an apparatus output for indicating when the voltage across the capacitor is one of above and below the first voltage. | 01-15-2009 |
| 20090051394 | Frequency Multipliers Using Multi-Phase Oscillation - A method of generating an output signal from an input signal includes a step of generating a set of n signals, n being an integer greater than or equal to 3, by generating a signal for each integer i such that 0≦i≦(n−1), each signal within the set having the same frequency and approximately equal amplitude and a phase equal to (360/n)i degrees. The method also includes a step of inputting each of the set of n signals to a gate terminal of a corresponding one of a set of n transistors. Each of the transistors has a source terminal electrically connected to a common voltage drain and each of the transistors has a drain terminal electrically connected to a coupling. The coupling is electrically connected to a common voltage source. The output signal at the coupling has a frequency equal to the frequency of the input signal multiplied by n. | 02-26-2009 |
| 20090072870 | DIGITAL SIGNAL PROCESSING CIRCUIT - A digital signal processing circuit performs a predetermined computation processing on input data sequentially input at a first frequency, and generates output data of a second frequency oversampled to n times (n is an integer greater than or equal to 2). A computation processing unit collectively computes m (m is 2≦m≦n) successive output data in output data at n sampling timings after oversampling. A data holding unit holds data at a predetermined sampling timing in the data generated in the computation processing unit. An output data holding unit holds data at m sampling timings to be output. An output data generating unit sequentially outputs m output data obtained by the computation processing unit according to a second frequency. | 03-19-2009 |
| 20090160502 | FREQUENCY MULTIPLIER - A frequency multiplier is provided that includes a switching component having a plurality of differential pairs of transistors. The frequency multiplier further includes a gain stage. A common mode feedback generated by the switching component is also provided to the gain stage. | 06-25-2009 |
| 20090315596 | MATCHING CIRCUIT FOR A COMPLEX RADIO FREQUENCY (RF) WAVEFORM - A complex waveform frequency matching device is disclosed. In various embodiments, the matching device comprises a plurality of radio frequency generators coupled in parallel with one another. Each subsequent one of the plurality of radio frequency generators is configured to produce a harmonic frequency related by an integral multiple to a frequency produced by any lower-frequency producing radio frequency generator, thereby generating a complex waveform. A plurality of frequency splitter circuits is coupled to an output of the plurality of radio frequency generators, and each of a plurality of matching networks has an input coupled to an output of one of the plurality of frequency splitter circuits and an output configured to be coupled to a plasma chamber. | 12-24-2009 |
| 20100141307 | Frequency multiplier and method for frequency multiplying - A frequency multiplier according to the present invention comprises a period-to-voltage converter that generates a control signal in response to the period of an input signal. An oscillator generates an output signal in accordance with the control signal. The level of the control signal is corrected to the frequency of the input signal. The control signal is coupled to determine the frequency of the output signal. | 06-10-2010 |
| 20100156476 | SYSTEMS AND METHODS FOR PROVIDING A CLOCK SIGNAL - Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled. | 06-24-2010 |
| 20110095792 | FREQUENCY MULTIPLIER - A frequency multiplier including some embodiments, the frequency multiplier includes: a first transistor and a second transistor, wherein a first terminal of the first transistor is connected to a third terminal of the second transistor through a first capacitor, and a first terminal of the second transistor is connected to a third terminal of the first transistor through a second capacitor. The frequency multiplier also includes a balun, wherein the third terminal of the first transistor is connected to a terminal of the balun, and the third terminal of the second transistor is connected to a different terminal of the balun. | 04-28-2011 |
| 20110187420 | FREQUENCY MULTIPLIER DEVICE AND METHOD THEREOF - The present invention provides a method for identifying a specific number of communicating points having relatively smallest accumulated path values from a plurality of transmitting points for a receiving point in a communication system. The method includes steps of: (a) defining a first coordination of each of the plurality of transmitting points and the receiving point on a complex plane; (b) transferring the first coordination of the receiving point to a second coordination thereof, in which the second coordination of the receiving point is near an origin of the complex plane; and (c) identifying the specific number of transmitting points having relatively smallest accumulated path values based on the second coordination of the receiving point. | 08-04-2011 |
| 20110227612 | Frequency multiplier - A frequency multiplier for generating an output signal having a frequency N times the input signal, with N equal to or greater than 3, the frequency multiplier including a phase splitter circuit responsive to the input signal for generating N signals with phase differences, and a mixer circuit responsive to the N signals of the phasor circuit for providing an output signal having a frequency N times the input signal. | 09-22-2011 |
| 20120001667 | FREQUENCY CONVERTING CIRCUIT, SIGNAL PROCESSING CIRCUIT AND RECEIVER - A frequency converting apparatus according to one embodiment is a frequency converting circuit which generates a multiplied signal obtained by multiplying a local signal by an amplified signal generated by an amplifying portion comprising a first transistor having a drain terminal connected to a first power source potential, the frequency converting circuit comprising: a converter which comprises a second transistor of which gate terminal is connected to the amplifying portion and which converts the amplified signal inputted to the gate terminal into a current signal; a switching circuit which comprises two third-transistors of which a source terminal is connected each other and which multiplies the current signal by the local signal and generates the multiplied signal; and an impedance element which comprises a first terminal connected to a source terminal of the first transistor, a second terminal connected to a drain terminal of the second transistor and a third terminal connected to the source terminal of the third transistor, which inputs a first direct current inputted from the source terminal of the first transistor and a second direct current inputted from the source terminal of the third transistor into the drain terminal of the second transistor, of which impedance is an ACwise high impedance between the first terminal and the second terminal. | 01-05-2012 |
| 20120133400 | FREQUENCY MULTIPLIER - A frequency multiplier includes an input circuit, an output circuit, and a resonance circuit. The input circuit is coupled to an input node and a middle node. The middle node provides a middle signal that has a signal component having the same frequency as an input signal that is provided to the input node. The middle signal further has an even number “n” multiple of the input signal frequency. The output circuit has a predetermined input impedance for the middle node. The resonance circuit includes an inductor that is coupled in series with a capacitor, where the capacitor is in a parallel connection to the middle node. The resonance circuit has a resonance frequency that is equal to a frequency of the input signal, and such resonance circuit also has an output impedance that matches with the predetermined input impedance of the output circuit. | 05-31-2012 |
| 20120182053 | HALF CYCLE DELAY LOCKED LOOP - An integrated circuit for a half cycle delay locked loop is disclosed. The integrated circuit includes an input node coupled to an oscillator having a clock cycle of M. The integrated circuit also includes N delay elements outputting N different phase-shifted signals, where a total delay introduced by the N delay elements is M/2. The integrated circuit also includes a plurality of inverters, each coupled to an output of one of the N delay elements, where the plurality is less than N. The integrated circuit also includes a phase detector coupled to the input node and an inverted Nth phase-shifted signal. The integrated circuit also includes a charge pump coupled to the phase detector and the delay elements. | 07-19-2012 |
| 20120274368 | METHOD AND CIRCUIT FOR WAVEFORM GENERATION - A programmable waveform generator, comprising: a controllable waveform generator configured to generate an initial bandwidth signal having an initial frequency bandwidth; a tone generator configured to generate a plurality of tone signals, each tone signal having a different frequency; a first bandwidth-multiplying circuit, including a first mixer having a first input port configured to receive the low-bandwidth signal; a first switch configured to choose one of the plurality of tone signals or a phase shifted version of one of the plurality of tone signals and output the chosen signal as a first chosen tone; a controller configured to control the operation of the bandwidth multiplying block, wherein the first mixer is further configured to receive the first chosen tone at a second input port, wherein the first mixer is further configured to mix the initial bandwidth signal and the first chosen tone to generate a first bandwidth signal at an output port, the first bandwidth signal having a first frequency bandwidth, wherein the first frequency bandwidth is greater than the initial frequency bandwidth, and wherein the first frequency bandwidth is an integer multiple of the initial frequency bandwidth. | 11-01-2012 |
| 20120306547 | METHOD AND APPARATUS FOR LOCAL OSCILLATION DISTRIBUTION - A circuit includes an oscillation generation circuit, a distribution circuit, and a transceiver circuit. The oscillation generation circuit is configured to generate a first oscillation signal having a first frequency. The distribution circuit includes a voltage to current stage, a transmission portion and a current to voltage stage. The voltage to current stage is configured to receive the first oscillation signal, and convert the first oscillation signal into a current form. The transmission portion is configured to transmit the first oscillation signal in the current form. The current to voltage stage is configured to receive the first oscillation signal in the current form and generate a second oscillation signal having a sub-harmonic frequency of the first frequency, such as half of the first frequency. The transceiver circuit is configured to operate in a frequency band responsive to the second oscillation signal. | 12-06-2012 |
| 20120319745 | FREQUENCY MULTIPLIER OSCILLATION CIRCUIT AND METHOD OF MULTIPLYING FUNDAMENTAL WAVE - A frequency multiplier oscillation circuit (and a method of multiplying a fundamental wave) includes an oscillation unit, a multiplication unit, and a fundamental wave component removal unit. The oscillation unit outputs a fundamental wave. The multiplication unit multiplies the fundamental wave to output the multiplied wave. The fundamental wave component removal unit cancels a fundamental wave component included in the multiplied wave based on the fundamental wave that is output from the oscillation unit to output the multiplied wave to an output terminal. | 12-20-2012 |
| 20130120031 | FREQUENCY MULTIPLIER AND METHOD OF MULTIPLYING FREQUENCY - A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals. | 05-16-2013 |
| 20130229210 | ON-CHIP POWER-COMBINING FOR HIGH-POWER SCHOTTKY DIODE BASED FREQUENCY MULTIPLIERS - A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line. | 09-05-2013 |
| 20130265087 | Frequency multiplier circuit with function of automatically adjusting duty cycle of output signal and system thereof - A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%. | 10-10-2013 |
| 20130300464 | METHOD OF CONTROLLING A SWITCHED MODE POWER SUPPLY AND CONTROLLER THEREFOR - A controller for an SMPS is disclosed. The controller applies a frequency jitter to the SMPS to reduce Electromagnetic Interference (EMI) and/or audible noise. A second input variable is multiplied by a correlated jitter signal, in order to compensate the output power for the frequency jitter. A corresponding method is also disclosed. Since the jitter compensation occurs within the controller, the method is particularly suitable for controllers operating under different control modes for different output powers (or other output criteria). The multiplicative compensation is applicable across a wide range of converter types. | 11-14-2013 |
| 20140028359 | Frequency multiplier circuit and system - A frequency multiplier circuit includes a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to the first signal input terminal, the second signal input terminal, the power source terminal and the ground terminal, a reference circuit which is connected to the power source terminal and the ground terminal, and a frequency synthesis circuit which is connected to the main control circuit, the reference circuit, the output terminal, the power source terminal and the ground terminal. | 01-30-2014 |
| 20140070854 | INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY - Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples. | 03-13-2014 |
| 20140084971 | FREQUENCY MULTIPLIER APPARATUS AND OPERATING METHOD THEREOF - The present invention provides a frequency multiplier apparatus. The frequency multiplier apparatus includes an injection-locked frequency multiplier and a frequency-to-control signal converter. The injection-locked frequency multiplier outputs an output signal having a first frequency in response to an input signal having a first basic frequency. The frequency-to-control signal converter provides a first control signal to the injection-locked frequency multiplier in response to the input signal. The injection-locked frequency multiplier adjusts the first frequency to a second frequency in response to a change of the first control signal when the first basic frequency is changed to a second basic frequency. | 03-27-2014 |
| 20140132313 | FREQUENCY MULTIPLIER AND ASSOCIATED METHOD - A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal. | 05-15-2014 |
| 20140266329 | FREQUENCY QUADRUPLERS AT MILLIMETER-WAVE FREQUENCIES - A symmetric frequency multiplier includes four non-linear devices configured to receive an input signal having a fundamental mode and to provide an output having one or more harmonics; and three collinear transmission lines, each having a length of about one quarter of an input wavelength, configured to receive the outputs of the non-linear devices and configured to combine bifurcated components of the signals from the non-linear devices into two frequency-multiplied output signals. Two of the signals from the non-linear devices are provided at respective ends of the collinear transmission lines and two of the signals from the non-linear devices are provided between transmission lines, such that each of the bifurcated components of a given signal passes through a different subset of the transmission lines. | 09-18-2014 |
| 20140266330 | FREQUENCY QUADRUPLERS AT MILLIMETER-WAVE FREQUENCIES - Methods for increasing a signal frequency include generating two or more signals having a fundamental mode and one or more harmonics; phase shifting bifurcated components of the two or more signals in transmission lines; and combining the bifurcated components to create an output signal that cancels a fundamental mode, a second harmonic, and a third harmonic in the signals to produce a frequency-multiplied output signal. | 09-18-2014 |
| 20140266331 | METHOD AND APPARATUS FOR LOCAL OSCILLATION DISTRIBUTION - A circuit includes an oscillation generation circuit, a distribution circuit, and a transceiver circuit. The oscillation generation circuit is configured to generate a first oscillation signal having a first frequency. The distribution circuit includes a voltage to current stage, a transmission portion and a current to voltage stage. The voltage to current stage is configured to receive the first oscillation signal, and convert the first oscillation signal into a current form. The transmission portion is configured to transmit the first oscillation signal in the current form. The current to voltage stage is configured to receive the first oscillation signal in the current form and generate a second oscillation signal having a sub-harmonic frequency of the first frequency, such as half of the first frequency. The transceiver circuit is configured to operate in a frequency band responsive to the second oscillation signal. | 09-18-2014 |
| 20140292381 | GRAPHENE-BASED FREQUENCY TRIPLER - A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency. | 10-02-2014 |
| 20140312937 | Multi-Band Frequency Multiplier - A multi-band frequency multiplier configured to generate frequencies and multiplied frequencies in an integrated system. The multi-band frequency multiplier includes a multi-band multiplier core with a multiplier core differential amplifier configured to receive a multiplier input signal. A switchable load impedance connects to the multiplier core differential amplifier, and includes n multiplier sections. Each multiplier section includes a section impedance and a section switch. The multiplier core differential amplifier generates an output signal having a frequency substantially equal to k times the input frequency in a range of a selected one of n critical frequencies when a selected one of the section switches corresponding to the selected one of the n critical frequencies is triggered. | 10-23-2014 |
| 20140312938 | FREQUENCY MULTIPLIER - A frequency multiplier includes: a multiphase signal generator configured to generate multiphase signals in response to a source signal; a pulse generator configured to generate a plurality of pulse signals in response to the multiphase signals; and a synthesizer configured to generate a frequency multiplication signal in response to edges of the pulse signals. Each of the plurality of pulse signals is generated in response to a corresponding multiphase signal, and the frequency multiplication signal is obtained by multiplying a frequency of the source signal. | 10-23-2014 |
| 20150070055 | RECEIVER - A received is disclosed that is capable of improving reception sensitivity while avoiding an increase in circuit scale. The receiver includes: a multi-phase local oscillation signal generating section that generates a plurality of local oscillation signals of different phases; a phase selection signal generating section that generates a phase selection signal used to select a baseband signal of a predetermined phase based on a detection result of a reception level of a high-frequency signal; and a frequency converter that frequency-converts the high-frequency signal based on the plurality of local oscillation signals, that generates a plurality of baseband signals of different phases, and that selects a baseband signal from among the plurality of baseband signals based on the phase selection signal. | 03-12-2015 |
| 20160149562 | HIGH POWER W-BAND/F-BAND SCHOTTKY DIODE BASED FREQUENCY MULTIPLIERS - A solid state device chip including diodes (generating a higher frequency output through frequency multiplication of the input frequency) and a novel on-chip power combining design. Together with the on-chip power combining, the chip has increased efficiency because the diodes' anodes, being micro-fabricated simultaneously on the same patch of a GaAs wafer under identical conditions, are very well balanced. The diodes' GaAs heterostructure and the overall chip geometry are designed to be optimized for high power operation. As a result of all these features, the device can generate record-setting power having a signal frequency in the F-band and W-band (30% conversion efficiency). | 05-26-2016 |
| 327120000 | With plural outputs | 2 |
| 20140184282 | FREQUENCY MULTIPLIER AND SIGNAL FREQUENCY-MULTIPLYING METHOD - A frequency multiplier includes a first impedance module, a second impedance module, a first path and a second path. When the first path is conducted, the first impedance module generates a first output signal and the second impedance module generates a second output signal. When the second path is conducted, the first impedance module generates a third output signal and the second impedance module generates a fourth output signal. The first and second paths are not conducted simultaneously. A frequency of a first combination signal generated from the first and third output signals and a frequency of a second combination signal generated from the second and fourth output signals are N times of a frequency of the input signal, where N is a positive rational number. | 07-03-2014 |
| 327121000 | Selective | 1 |
| 20090033378 | PROGRAMMABLE FREQUENCY MULTIPLIER - A programmable frequency multiplier device which includes a frequency doubler section configured to receive an input signal having a frequency f, and to output doubled signals, each of the doubled signals having a frequency 2 | 02-05-2009 |
| 327122000 | Doubling | 14 |
| 20090079474 | METHOD AND SYSTEM FOR GENERATION OF SIGNALS UP TO EXTREMELY HIGH FREQUENCIES USING A DELAY BLOCK - Aspects of a method and system for generation of signals up to extremely high frequency using a delay block are provided. In this regard, a first signal may be delayed, via at least a portion of a plurality of delay elements and via a variable capacitance, to generate a second signal that is 90° out of phase relative to the first signal. Additionally, the first signal and second signal may be mixed to generate a third signal, wherein a frequency of the third signal is twice a frequency of said first signal. The portion of the delay elements utilized for delaying the signal may be controlled via one or more switching elements. In this regard, one of the plurality of delay elements may be selected to output the second signal. Moreover, the portion of the delay elements utilized for delaying the signal may be programmably controlled. | 03-26-2009 |
| 20090079475 | METHOD AND SYSTEM FOR TRANSMISSION AND/OR RECEPTION OF SIGNALS UP TO EXTREMELY HIGH FREQUENCIES UTILIZING A DELAY CIRCUIT - Aspects of a method and system for transmission and/or reception of signals up to EHF utilizing a delay circuit are provided. In this regard, a transceiver may comprise at least one delay circuit which may, in turn, comprise a plurality of delay elements and a variable capacitance. The delay circuit may be enabled to delay a first signal, via at least a portion of the delay elements and via the variable capacitance, to generate a second signal that is 90° phase shifted relative to said first signal. Additionally, the delay circuit may be enabled to mix the first signal with the second signal to generate a third signal that is twice a frequency of the first signal. The third signal may be utilized for up-conversion and/or down-conversion of signals to and/or from baseband, intermediate frequencies, and/or RF frequencies of up to EHF. | 03-26-2009 |
| 20100127737 | Variable PFC and grid-tied bus voltage control - An apparatus for generating a compensation signal for a power converter where the second harmonic ripple on the voltage bus is substantially removed from the compensation signal. The apparatus comprises a frequency-locked clock generator, a bus voltage data generator, a stack, and a compensation signal generator. The frequency-locked clock is coupled to the power converter voltage bus that contains harmonics of the AC line frequency. The clock generator frequency locks to the second harmonic of the AC line frequency and creates a system clock which is used for the synchronous operations throughout the apparatus. The bus-voltage data generator inputs a power converter scaled-bus voltage, generates bus-voltage data at a sampling rate which is determined by the coupled system clock. The output of the bus-voltage generator is input into a stack. The output of the stack is coupled to a summer to remove the second harmonic ripple, and is used by a modified PID′ filter to generate a compensation signal for a power converter controller. | 05-27-2010 |
| 20110215844 | FREQUENCY MULTIPLIER CIRCUIT - A frequency multiplier circuit, comprising a first stage including a first differential pair of amplifier elements having respective current conduction paths connected in parallel between first and second nodes and respective control terminals connected to receive input signals of opposite polarity at an input frequency in the radio frequency range, the first and second nodes being connected to respective bias voltage supply terminals through first and second impedances respectively so that current flowing differentially in the current conduction paths of the first differential pair of amplifier elements produces a voltage difference across the first and second nodes at a frequency which contains a harmonic of the input frequency, and a second stage including a second differential pair of amplifier elements coupled at the harmonic of the input frequency with the first and second nodes to amplify differentially the voltage difference and produce an output signal at the harmonic of the input frequency. Radio frequency connections apply the voltage difference across the first and second nodes at the frequency of the harmonic to the second differential pair of amplifier elements and block direct current, and separate direct current connections connect respectively the first differential pair of amplifier elements and the second differential pair of amplifier elements across the bias voltage supply terminals. | 09-08-2011 |
| 20110267113 | FREQUENCY MULTIPLIER - A multiplier circuit, including: a transistor with gate, source and drain connections adapted to accept an input signal by the transistor gate; a reference voltage source providing a DC reference voltage to the transistor drain; an inductor connected between the drain and the reference voltage source; a resistor connected in parallel to the inductor between the transistor drain and the reference voltage source; a current source providing a DC current to the transistor source; two capacitors forming a voltage divider, with the first capacitor connecting between the gate and the source and the second capacitor connecting between the source and the ground in parallel to the current source; and wherein the multiplier circuit is adapted to accept an input signal and provide as output an amplified current signal with a frequency that is double that of the input signal. | 11-03-2011 |
| 20120161824 | FREQUENCY DOUBLER, A DEVICE INCLUDING THE SAME AND A METHOD FOR FREQUENCY DOUBLING - A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal. | 06-28-2012 |
| 20130113529 | Signal Generator - A signal generator for coupling to a concealed conductor including a first oscillator configured to generate a first waveform having a first frequency, a first terminal coupled to the first oscillator through a first band pass filter configured to pass signals of the first frequency, a second oscillator configured to generate a second waveform having a second frequency, and a second terminal coupled to the second oscillator through a second band pass filter configured to pass signals of the second frequency. | 05-09-2013 |
| 20140139274 | BIPOLAR TRANSISTOR FREQUENCY DOUBLERS AT MILLIMETER-WAVE FREQUENCIES - Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency. | 05-22-2014 |
| 20140361815 | FREQUENCY DOUBLER AND RELATED METHOD OF GENERATING AN OSCILLATING VOLTAGE - A frequency doubling device suitable to generate an output terminal voltage oscillating at a differential frequency double the frequency of the input differential voltage, includes a first differential pair of P-type transistors and a second differential pair of N-type transistors controlled by the differential input voltage, as well as an LC oscillator including a LC resonant dipole through which the absorbed current is forced by two differential pairs of transistors. | 12-11-2014 |
| 20150035570 | CLOCK DOUBLER INCLUDING DUTY CYCLE CORRECTION - Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock. | 02-05-2015 |
| 20150130517 | BIPOLAR TRANSISTOR FREQUENCY DOUBLERS AT MILLIMETER-WAVE FREQUENCIES - Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency. The output frequency between the collector impedances and the common impedance is an even integer multiple of the input frequency. | 05-14-2015 |
| 20160049927 | FREQUENCY DOUBLER - A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node. | 02-18-2016 |
| 20160118964 | FREQUENCY TRIPLER AND LOCAL OSCILLATOR GENERATOR - A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal. | 04-28-2016 |
| 20160204773 | SYSTEM AND METHOD FOR ANTI-AMBIPOLAR HETEROJUNCTIONS FROM SOLUTION-PROCESSED SEMICONDUCTORS | 07-14-2016 |
