| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327058000 | Maximum or minimum amplitude | 37 |
| 20090015295 | Envelope detector having reduced harmonic interference - A system for detecting the envelope of a signal is provided. The system includes a first envelope detector generating a first envelope signal of an input RF signal, such as an envelope signal representing the positive peak envelope of the input RF signal. A second envelope detector generates a second envelope signal of the input RF signal, such as an envelope signal representing the negative peak envelope of the input RF signal. A signal combiner receives the first envelope signal and the second envelope signal and generates an even-order harmonic compensated envelope signal, such as by compensating for the difference between the positive peak envelope and the negative peak envelope. | 01-15-2009 |
| 20090058470 | SELF-STOP CIRCUIT USING NONVOLATILE STORAGE ELEMENT CHARGE AMOUNT AS TIMER - A self-stop circuit has a nonvolatile storage element ( | 03-05-2009 |
| 20090072865 | Peak Detector with Active Ripple Suppression - A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwith (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals. | 03-19-2009 |
| 20090134913 | SIGNAL COMPARISON CIRCUIT - A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison. | 05-28-2009 |
| 20090167361 | HIGH-SPEED AMPLITUDE DETECTOR WITH A DIGITAL OUTPUT - An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described. | 07-02-2009 |
| 20090289664 | Signal detecting apparatus, signal receiving apparatus, and signal detecting method - A signal detecting apparatus detects a signal received based on a current received and includes a detecting unit that detects, in the current received, a peak equal to or higher than a threshold and a time counting unit that counts a given period of time from a point in time of detection of the peak by the detecting unit. The signal detecting apparatus further includes a determining unit that determines whether the detecting unit has detected the peak again within the given period of time counted by the time counting unit. An output unit of the signal detecting apparatus outputs information indicating detection of the signal received when the determining unit determines that the peak has been detected again. | 11-26-2009 |
| 20090322379 | PEAK HOLD CIRCUIT - A peak hold circuit includes an input transistor, which is provided with an input signal, and a first hold capacitor, which holds a maximum or minimum value of the input signal. A correction circuit, which corrects the hold voltage held by the first hold capacitor, includes an operational amplifier, which is supplied with the hold voltage, and a correction transistor, which is provided with an output signal of the operational amplifier. A source/emitter of the correction transistor is coupled to the operational amplifier. The peak hold circuit also includes a current detection circuit, which detects current flowing to the input transistor, and a peak current hold circuit, which holds the peak value of the current detected by the current detection circuit as a peak current and supplies the peak current to the correction transistor. | 12-31-2009 |
| 20100007384 | COMBINATION AC/DC PEAK DETECTOR AND SIGNAL TYPE DISCRIMINATOR - A device and method for current detecting and discriminating is disclosed. The device includes a differential receiver configured to receive a current input, a positive-side Schmitt trigger in communication with the input stage, wherein the positive-side Schmitt trigger is configured to receive an output provided by the input stage, and wherein the positive-side Schmitt trigger is configured to create a positive-side Schmitt trigger output representative of the current input, and a negative-side Schmitt trigger in communication with the input stage, wherein the negative-side Schmitt trigger is configured to receive the output provided by the input stage, and wherein the negative-side Schmitt trigger is configured to create a negative-side Schmitt trigger output representative of the current input. | 01-14-2010 |
| 20100052734 | SYSTEM FOR PROVIDING LARGE RC TIME CONSTANTS IN INTEGRATED CIRCUITS - A peak detector for implementation in a monolithic integrated circuit includes one or more Miller capacitors and one or more transistors for selectively setting large RC time constant values only with components included in the integrated circuit's die. Neither resistors nor capacitors located outside the integrated circuit are used for setting a selected value of a time constant. Some embodiments of the invention include diodes for compensation of amplifier leakage current in the peak detector, thereby increasing a maximum value of a time constant that can be implemented in an integrated circuit. A peak detector in accord with an embodiment of the invention may optionally be configured for either single-ended or differential operation. | 03-04-2010 |
| 20100073033 | PEAK DETECTOR - A peak detector capable of rapidly detecting a peak value of a signal is provided. The peak detector includes first and second operational amplifiers and an auxiliary current source to detect two rail to rail signals. The first operational amplifier outputs a detection signal by buffering a first rail to rail input signal. The second operational amplifier outputs a control signal in response to a second rail to rail input signal and the detection signal. The auxiliary current source includes a terminal connected to an output terminal of the first operational amplifier and the other terminal connected to the first or second source voltage. The auxiliary current source operates in response to the control signal. The auxiliary current source supplies a current from the first source voltage to the output terminal in response to the control signal or supplies a path for discharging a current from the output terminal to the second source voltage. | 03-25-2010 |
| 20100271073 | QUARTER CYCLE WAVEFORM DETECTOR - A method for extracting peak information from an amplitude varying sinusoidal waveform output from a sensor is provided. The method includes gating a counter with a keying signal having a keying-signal period generated by a sinusoidal waveform associated with the amplitude varying sinusoidal waveform, receiving high frequency clock signals at the gated counter during keying-signal periods, wherein a clock-signal period is much less than the keying-signal periods, disabling the counter at the end of each keying-signal period, generating a quarter-count value based on the disabling, and outputting a sample pulse associated with each keying-signal period. If a current-keying-signal period is the same as a last-keying-signal period, the sample pulse is generated at a quarter-wave of the sinusoidal waveform. If the current-keying-signal period differs from the last-keying-signal period, the associated output sample pulses are adjusted to the quarter-wave of the sinusoidal waveform in the next-keying-signal period. | 10-28-2010 |
| 20110050285 | HIGH LINEAR FAST PEAK DETECTOR - A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor. | 03-03-2011 |
| 20110062995 | Low Power, Accurate Reference-Free Threshold Detector - Embodiments of the present invention relate generally to detector circuits. Embodiments provide a low-power, accurate reference-free threshold detector. In particular, embodiments reduce leakage current at low input levels and prevent shoot through current for higher than nominal low input levels. Further, embodiments require no bandgap or accurate reference, and as a result eliminate the need for a constantly ON bandgap or accurate reference circuit. As such, embodiments have significantly reduced power consumption compared to conventional circuits. In addition, embodiments detect correctly low and high input levels that are separated narrowly and that may have wide ranges. Embodiments can be extended to any particular design choice of low and high input levels and corresponding output levels. | 03-17-2011 |
| 20110115525 | DEVICE FOR DETECTING THE PEAK VALUE OF A SIGNAL - A device for detecting the peak value of a signal with crest factor not known a priori includes a pair of peak detectors, each of which includes a rectifier element and a discharge-current generator and generates a respective output signal that is a function of the ratio between a physical dimension of the rectifier element and the intensity of discharge current produced by the generator. The ratio is different for the two detectors, and a combination network combines the output signals of the two peak detectors with one another and produces a combined signal indicating the peak value sought with high accuracy. | 05-19-2011 |
| 20110241732 | LOW VOLTAGE SELF CALIBRATED CMOS PEAK DETECTOR - The present invention relates to a low-voltage self-calibrated peak detector ( | 10-06-2011 |
| 20110260755 | Methods and Systems for Detecting Battery Presence - A device has a battery presence detection system. A line charging pulse signal is applied to a terminal battery detection line, which is connected when the battery is present to a ground line via a resistor and a capacitance. A detector determines whether the battery is connected to the mobile terminal based on detecting whether a line voltage edge or a line voltage level on the terminal battery detection line is present. | 10-27-2011 |
| 20110267110 | Symmetrical Electrical Physical Layer Activity Detector - A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be fully rectified through the output devices of the two buffers, and may be filtered to provide the detected output. The two buffers may be configured in a symmetrical structure that allows for the rejection of common-mode signals when the outputs of the buffers are coupled to a common node. | 11-03-2011 |
| 20120119789 | Peak Detector Extension System - The different illustrative embodiments provide a method and apparatus for managing peak detector circuits. A first number of voltages for a first number of signals detected by a peak detector circuit connected to a wire in a bus system is identified. The first number of signals is used to send data over the wire. The first number of voltages is for a first number of transmission speeds for the first number of signals. A second number of voltages for a second number of signals detected by the peak detector circuit is identified. The second number of signals is present in the wire in an absence of the data being sent over the wire. The second number of voltages is for a second number of transmission speeds for the second number of signals. A number of settings are selected for the peak detector circuit based on the first number of voltages and the second number of voltages. | 05-17-2012 |
| 20130162296 | PEAK VOLTAGE DETECTOR AND RELATED METHOD OF GENERATING AN ENVELOPE VOLTAGE - A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor. | 06-27-2013 |
| 20130162297 | PEAK VOLTAGE DETECTOR AND RELATED METHOD OF GENERATING AN ENVELOPE VOLTAGE - A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor. | 06-27-2013 |
| 20130181744 | ANALOG PEAK HOLD CIRCUITS - A peak hold circuit includes an input node configured to receive an input waveform, a peak hold component coupled to the input node and configured to sample and hold a peak value of the input waveform at a peak value node, a reset node configured to receive a reset signal, a reset circuit coupled to the peak hold component and the reset node, the reset circuit configured to reset the peak hold value, and a voltage clamp coupled to the input node, the reset circuit, and the reset node, the voltage clamp configured to clamp the input node in response to the reset signal. | 07-18-2013 |
| 20140002139 | MAXIMUM VOLTAGE SELECTION CIRCUIT AND METHOD AND SUB-SELECTION CIRCUIT | 01-02-2014 |
| 20140232435 | ANALOG MINIMUM OR MAXIMUM VOLTAGE SELECTOR CIRCUIT - A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell. | 08-21-2014 |
| 20150123711 | OPTIMIZED PEAK DETECTOR for the AGC LOOP IN A DIGITAL RADIO RECEIVER - A method of peak detection applicable to complex in-phase and quadrature phase signals in a digital radio receiver where the incoming signal is divided into a plurality of frames. Each frame is then further divided into a plurality of smaller blocks, and the signal peak is determined in each block individually followed by selecting the peak signal value from the said blocks. | 05-07-2015 |
| 20160169943 | SIGNAL ANALYSIS CIRCUIT AND SIGNAL ANALYSIS METHOD THEREOF | 06-16-2016 |
| 327059000 | Employing input compared to output | 3 |
| 20080211544 | Peak voltage detector circuit and binarizing circuit including the same circuit - A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal. | 09-04-2008 |
| 20150008962 | SIGNAL ENVELOPE PROCESSING - Methods and apparatus for detection and tracking of a signal envelope. The circuit comprises absolute value circuitry configured to receive data samples and output a first value corresponding to the magnitude of said data samples. An envelope tracker maintains an envelope output value and compares the first value to the current envelope output value and modifies the envelope output value based on said comparison to provide the envelope output value with predetermined attack and decay characteristics. The absolute value circuitry has a first input for receiving a first digital signal at a first sample rate and a second input for receiving an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate and outputs the first value based on the magnitudes of the samples received at the first input and the samples received at the second input. Using the first digital signal provides an early indication of any increases in signal envelope whereas the second digital signal can allow a more accurate estimation. | 01-08-2015 |
| 20160169947 | Measurement Circuit | 06-16-2016 |
| 327060000 | Employing input compared to reference derived therefrom | 3 |
| 20080252337 | Receiver signal strength indicator - A system and method are provided for measuring the amplitude of a received signal. The method receives an analog input signal, and compares a peak value of the analog input signal to a threshold level. Threshold transition data is generated, and the threshold level is adjusted in response to the transition data. The above-mentioned processes of comparing, generating, and adjusting are reiterated until the threshold level is about equal to the analog input signal peak value. As a result, a measurement of the analog input signal peak value is supplied. In one aspect, threshold transition data is converted into a digital value. Then, the measurement of the analog input signal peak value uses the digital value to represent the analog input signal peak value. Further, the digital value is converted into an analog voltage as feedback, and the analog voltage is used as the threshold level. | 10-16-2008 |
| 20100271074 | COMPARISON CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - A comparison circuit includes a comparator into a first input terminal of which an input signal is input, and into a second input terminal of which a reference voltage for comparison is input, a controller which monitors an output signal of the comparator, and a voltage generation circuit into which a threshold voltage control signal from the controller is input, wherein the voltage generation circuit, when the voltage level of the output signal of the comparator is a first level, outputs as the reference voltage a first threshold voltage which is one of a high potential side threshold voltage and a low potential side threshold voltage which define a hysteresis width, and when the voltage level of the output signal of the comparator is a second level, outputs as the reference voltage a second threshold voltage which is the other one of the high potential side threshold voltage and low potential side threshold voltage. | 10-28-2010 |
| 20110109346 | APPARATUS AND METHODOLOGY FOR MAXIMUM POWER POINT TRACKING FOR A SOLAR PANEL - Circuitry and methodology for tracking the maximum power point (MPP) of a solar panel is disclosed. The voltage and current generated by the solar panel are monitored and used to generate a pulse signal for charging a capacitor. The changes in the voltage and current generated by the solar panel are also monitored, and that information is used to generate a pulse signal for discharging the capacitor. The charging and the discharging pulse signals are used to charge and discharge the capacitor. A reference signal indicative of the charge level of the capacitor is generated. As the current and voltage generated by the solar panel approach the maximum power point (MPP), the frequency of the discharging pulse signal becomes progressively higher, so that the capacitor charging occurs in progressively smaller increments. When the MPP is reached, the reference signal level becomes steady because the charge level of the capacitor becomes steady. | 05-12-2011 |
| 327062000 | Maximum and minimum amplitude | 6 |
| 20090072866 | Method and system for controlling amplified signals reflecting physiological characteristics - A method for controlling amplified signals in a medical diagnostic device having an amplifier system that is adapted to amplify input signals having a baseline and filter means for filtering the amplified signals, comprising the detection of the presence of an amplified signal having an amplitude that is above an upper voltage threshold or below a lower voltage threshold, and freezing the baseline of the amplified signal upon the detection thereof. | 03-19-2009 |
| 20090212826 | HYSTERESIS COMPARATOR - Disclosed herein is a hysteresis comparator for performing a binarization determination with respect to an input signal having a consecutively varying voltage level based on two threshold voltages having different voltage levels and generating an output signal based on a result of the determination. The hysteresis comparator includes a top peak detector for detecting a top peak of the input signal and generating a top peak detect voltage based on the detected top peak, a bottom peak detector for detecting a bottom peak of the input signal and generating a bottom peak detect voltage based on the detected bottom peak, a threshold voltage generator for generating the first and second threshold voltages within a range between a voltage level of the top peak detect voltage and a voltage level of the bottom peak detect voltage, and a voltage comparison circuit for comparing the voltage level of the input signal with the voltage levels of the first and second threshold voltages to perform the binarization determination with respect to the input signal, and generating the output signal based on the determination result. | 08-27-2009 |
| 20100039141 | Envelope Detector for High Speed Applications - An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit. | 02-18-2010 |
| 20130002305 | METHOD OF UTILIZING DUAL COMPARATORS TO FACILITATE A PRECISION SIGNAL RECTIFICATION AND TIMING SYSTEM WITHOUT SIGNAL FEEDBACK - A method and an associated apparatus for a signal rectification and timing circuit. A variable amplitude input signal is generated. An upper threshold level is determined and a lower threshold level is determined. The variable amplitude input signal and the upper threshold level are input into a first comparator. The variable amplitude input signal and the lower threshold level are input into a second comparator. A first digital output signal is generated in the first comparator using a hysteresis circuit and a second digital output signal is generated in the second comparator using a hysteresis circuit. The first digital output signal and the second digital output signal are input into a logic array. A digital level pulse output signal is generated in the logic array that has a digital transition where the variable amplitude input signal passed through a threshold level. | 01-03-2013 |
| 20140062533 | Adaptive Voltage Adjustment based on Temperature Value - Various embodiments of a method and apparatus for performing adaptive voltage adjustment based on temperature value are disclosed. In one embodiment, and integrated circuit (IC) includes logic circuitry having at least one temperature sensor therein. The IC also includes a power management circuit coupled to receive temperature readings from the temperature sensor. The power management circuit is configured to determine a temperature of the IC based on a temperature reading received from the temperature sensor. The power management circuit may compare the determined temperature to a temperature threshold. If the temperature exceeds a temperature threshold value, the power management circuit may cause the operating voltage to be reduced by an amount equivalent to a voltage guard band. | 03-06-2014 |
| 20160156341 | HIGH VOLTAGE SELECTOR CIRCUIT WITH NO QUIESCENT CURRENT | 06-02-2016 |
