| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327039000 | By frequency | 48 |
| 20080252336 | Non-Contacting Interrogation of System States - A device for non-contacting interrogation, without auxiliary power, of system states of a part that is rotatable relative to a fixed part comprises a coil on the rotatable part and a coil on the fixed part. The coils are mutually coupled, one being fed by a signal generator generating different frequencies, whilst the other coil is supplemented with at least one capacitance to form a resonance circuit. Further impedances can be added by means of switch elements to change a resonance frequency and form an interrogation circuit. By determining a resonance frequency on a signal generator side it is possible to draw conclusions about an impedance on an opposite side and to assign this to a switch element which is closed. | 10-16-2008 |
| 20080290904 | Frequency Monitor - A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step. | 11-27-2008 |
| 20090108878 | HIGH-FREQUENCY CLOCK DETECTION CIRCUIT - In order to provide a high frequency clock detection circuit capable to detect a high frequency clock using any period as a threshold, the high frequency clock detection circuit of the present invention includes a delay circuit having a delay time set to be longer than a clock period corresponding to the irregular high frequency state, a first flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the first flip-flop circuit, a second flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the second flip-flop circuit through the delay circuit, and a detection-result output circuit for detecting a difference between the output signal from the first flip-flop circuit and the output signal from the second flip-flop circuit and for providing the function circuit with the high frequency clock detection signal indicating the irregular high frequency state corresponding to an occurrence of the difference. | 04-30-2009 |
| 20090273372 | HALF BIN LINEAR FREQUENCY DISCRIMINATOR - Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin frequency discrimination, with few added computational burden. Two DFT shifted of half bin with respect to the zero frequency provide a linear response of the discrimination and good immunity to noise. The discriminator is particularly useful in FLL for tracking signals in a GPS receiver. | 11-05-2009 |
| 20100079171 | QUALITY OF PHASE LOCK AND LOSS OF LOCK DETECTOR - A systems and methods for providing phase lock conditions detection, such as a quality of phase lock and loss of lock detection, are described herein. One exemplary method comprises detecting an output frequency, comparing the output frequency with a first reference signal, providing a first signal and a second signal as a function of the output frequency and first reference signal comparison, receiving a predetermined threshold from a second reference signal, monitoring a deviation of the first and second signals from the predetermined threshold, generating a third signal as a function of the deviation, comparing the third signal to a window threshold wherein the window threshold is set based on a predetermined loop variable, generating a fourth signal a function of the third signal and the window threshold comparison, and providing an alarm based on the fourth signal. | 04-01-2010 |
| 20100277204 | FOR EXTERNALLY CLOCKED DIGITAL AUDIO INPUT, DETERMINING A VALID CLOCK AND MUTING AUDIO DURING SYNCHRONIZATION - Methods and apparatus for determining the existence of an external clock over a digital input port on a computer. In one embodiment, the external clock is validated, and a lock is performed when the clock is valid. Whenever a loss of the lock is detected, and, if a re-lock is likely, the apparatus is muted so that audio artifacts that would otherwise be heard are minimized. The methods and apparatus also provide automatic re-locking to the external clock when a sampling rate change is detected. | 11-04-2010 |
| 20120286825 | Method and Device for Monitoring a Frequency Signal - A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control signal (CS) from a communication interface (CLK, CS, MOSI, MISO), wherein the communication interface (CLK, CS, MOSI, MISO) is designed to transfer information according to a communication protocol. The method further comprises a step of providing the frequency signal in the unit and comparing the frequency signal to a temporal sequence of signal levels of the cycle signal (CLK) received by the communication interface (CLK, CS, MOSI, MISO) in order to obtain a comparison result or controlling a counter by the control signal (CS) and the frequency signal in order to obtain a counter status. Finally, the method according to the disclosure comprises a step of recognizing a predetermined quality of the frequency signal if the comparison result fulfills a predetermined criterion or if the counter status lies within a predetermined value range in order to monitor by the recognized quality of the frequency signal. | 11-15-2012 |
| 20120306539 | FRACTIONAL-N CLOCK GENERATOR AND METHOD THEREOF - A fractional-n clock generator includes a first digital delay line module, a second delay line module, an address generator and a selector. The first delay line module receives a frequency-divided clock signal and generates first delay signals having different phase differences with respect to the clock signal. The second delay line module receives the clock signal and generates second delay signals having different phase differences with respect to the clock signal. The address generator selects one of the first delay signals as an output signal of the first delay line module and one of the second delay signals as an output signal of the second delay line module. The selector selects one of the output signals of the first delay line module and the second delay line module as an output signal. A delay of the first delay line module is different from that of the second delay line module. | 12-06-2012 |
| 20150091617 | LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER - In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock. | 04-02-2015 |
| 327040000 | Comparison between plural inputs | 18 |
| 20090021282 | High-frequency signal detector - Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal. The circuit further includes a binarization circuit for receiving the output signal of the differential-input/single-ended output amplifier and comparing the output signal with a threshold voltage to thereby binarize and output the signal. The threshold voltage is adjustably set. | 01-22-2009 |
| 20090058468 | Method of Detecting the Frequency of an Input Clock Signal of an Integrated Circuit and Integrated Circuit - An integrated circuit includes a first switched capacitor element and a second switched capacitor element, which are coupled to form a bridge circuit, the first switched capacitor element being located in a first branch of the bridge circuit and the second switched capacitor element being located in a second branch of the bridge circuit. A detector circuit is coupled to the first branch and to the second branch of the bridge circuit. Switching signals of the first switched capacitor element and of the second switched capacitor element are generated on the basis of an input clock signal of the integrated circuit. | 03-05-2009 |
| 20090108879 | PROGRAMMABLE SENSITIVITY FREQUENCY COINCIDENCE DETECTION CIRCUIT AND METHOD - A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows. | 04-30-2009 |
| 20120105107 | VOLTAGE DETECTION DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A voltage detection device and a semiconductor device including the same are provided. The voltage detection device includes: a first clock generator which generates a first clock signal having a period that changes according to an external voltage; a second clock generator which generates a second clock signal having a predetermined period corresponding to a reference voltage; and a detector which detects a change of the external voltage by comparing the first clock signal with the second clock signal. | 05-03-2012 |
| 20130093466 | ON DIE LOW POWER HIGH ACCURACY REFERENCE CLOCK GENERATION - A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock. | 04-18-2013 |
| 20130241598 | FREQUENCY DIFFERENCE CALCULATION CIRCUIT, A SATELLITE SIGNAL RECEIVING APPARATUS AND FREQUENCY DIFFERENCE CALCULATION METHOD - In a frequency difference calculation circuit, a first frequency difference calculation section calculates a difference between the first input frequency and an oscillation frequency of the non-integer multiple oscillation section of which an oscillation frequency is a non-integer multiple of the first input frequency. Meanwhile, a second frequency difference calculation section calculates a difference between a second input frequency in which a difference between frequency having an integer multiple of the first input frequency and the second input frequency being within a predetermined error range, and the oscillation frequency of the non-integer multiple oscillation section and an addition section calculates a difference between the first input frequency and the second input frequency adding a calculation result of the first calculation section and a calculation result of the second calculation section. | 09-19-2013 |
| 20140232434 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range. | 08-21-2014 |
| 20150061728 | ELECTRONIC DEVICE AND METHOD FOR MAINTAINING FUNCTIONALITY OF AN INTEGRATED CIRCUIT DURING ELECTRICAL AGGRESSIONS - An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed. | 03-05-2015 |
| 327041000 | With synchronous detection | 1 |
| 20120056644 | MULTIPHASE CLOCK GENERATION CIRCUIT - A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error. | 03-08-2012 |
| 327042000 | Fixed frequency reference signal | 7 |
| 20080218217 | Semiconductor integrated circuit device - High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source voltage and an output node, and a first to a third NMOS transistors connected in series in three stages are provided between a ground voltage and the output node. And, the second PMOS transistor and the second NMOS transistor are driven ON when establishing conductivity between the power source voltage or the ground voltage and the output node by a first pulse signal, and the first PMOS transistor and the third NMOS transistor are driven OFF when the conductivity is shut down by a second pulse signal. Accordingly, the conduction time can be set by time difference between one edge of the first pulse signal and one edge of the second pulse signal, and therefore, short conduction time can be set, as a result, a charge amount of the charge pump circuit can be controlled precisely. | 09-11-2008 |
| 20080238489 | Fast Phase-Frequency Detector Arrangement - The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first latch means for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch means for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch means for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Thus, a simple and fast detection circuitry can be achieved based on a digital implementation. Furthermore, the charge pump circuit comprises a differential input circuit and control means for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement. This provides the advantage that behavior of the charge pump circuit can alleviate extra ripple generated by the detector arrangement. | 10-02-2008 |
| 20080238490 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a control unit for outputting an oscillation enable signal in synchronization with transitions of an input clock and buffering the input clock to output a comparison clock corresponding to an activation timing of the oscillation enable signal. A reference frequency generating unit outputs a reference clock having a predetermined frequency based on the oscillation enable signal. First and second counting units count clocking numbers of the reference clock and the comparison clock respectively until a preset count value. A comparing unit compares the clocking number of the reference clock with that of the comparison clock to generate a comparison signal. | 10-02-2008 |
| 20080297202 | SEMICONDUCTOR INTEGRATED CIRCUIT AND INFORMATION PROCESSING SYSTEM - In a semiconductor integrated circuit, a counter counts the number of high-speed clock signals that have been generated in a predetermined number of clock cycles of a low-speed clock signal. In synchronization with the low-speed clock signal, the semiconductor integrated circuit compares the counter value and a predetermined value, and judges whether the frequency of the high-speed clock signal has reaches a predetermined frequency. Since variations in the frequency become smaller as the oscillation of a high-speed oscillator stabilizes, the semiconductor integrated circuit detects that the oscillation is stable when the semiconductor integrated circuit has judged affirmatively a plurality of times. | 12-04-2008 |
| 20080315921 | DIGITAL FREQUENCY DETECTOR AND DIGITAL PHASE LOCKED LOOP USING THE DIGITAL FREQUENCY DETECTOR - A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information. | 12-25-2008 |
| 20140184272 | METHOD OF SIGNAL IDENTIFICATION BY USING RING OSCILLATOR BASED CLOCK AND RELATED APPARATUS THEREOF - A method of signal identification, including: receiving a signal; utilizing a clock generated by a ring oscillator to sample the signal continuously to generate a plurality of sampled signals; counting each sampled signal length corresponding to successive sampled signals each having an identical value; and identifying a content of the signal according to a plurality of sampled signal lengths. A signal identification apparatus, including: a receiving circuit, arranged for receiving a signal; a ring oscillator, arranged for generating a clock; a sampling circuit, arranged for sampling the signal continuously to generate a plurality of sampled signal; a counter, arranged for counting each sampled signal length corresponding to successive sampled signals each having an identical value; and a determining unit, arranged for identifying a content of the signal according to a plurality of sampled signal lengths. | 07-03-2014 |
| 20150145561 | MULTIPLEXED OSCILLATORS - An integrated circuit device for use in an automobile. The integrated circuit device includes a first oscillator configured to generate a first clock signal, a second oscillator configured to generate a second clock signal, a comparator circuit configured to compare a frequency of the first clock signal with a frequency of the second clock signal, and configured to generate a selection signal for selecting either of the first clock signal or the second clock signal, and a selector configured to output an output clock signal that is selected from among a plurality of outputs including the first clock signal and the second clock signal in response to the select signal. | 05-28-2015 |
| 327043000 | With logic or bistable circuit | 2 |
| 20100097102 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit. | 04-22-2010 |
| 20130049810 | Methods and Apparatus for Time to Current Conversion - A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided. | 02-28-2013 |
| 327044000 | With predetermined frequency selection | 5 |
| 20090115459 | Semiconductor device and operation method thereof - A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal. | 05-07-2009 |
| 20120326751 | FREQUENCY JUDGMENT DEVICE, VOLTAGE COMPARATOR CIRCUIT, AND FREQUENCY MEASUREMENT DEVICE - The frequency decision device determines frequency of the measured rectangular signal by simple and easy means. The frequency decision device inputs the measured rectangular signal that frequency (or period) changes dynamically. It generates a rectangular reference signal of predetermined on width τ synchronizing to the edge based on a positive going edge of this measured rectangle signal. And it watches the order of measured rectangle signal and falling edges of the rectangular reference signal. When this sequential order reversed, it detects that length of the ON time of ON time of the measured rectangle signal and the measured rectangular signal reversed. | 12-27-2012 |
| 20130038353 | SYSTEM AND METHOD FOR SIMULATING BIOFIDELIC SIGNALS - A system for simulating biofidelic signals includes a transducer and a neural transmitter port. The transducer is affected by a parameter and provides an alternating electrical signal based on an effect of the parameter. The neural transmitter port receives a processed electrical signal and outputs the processed electrical to a neural transmitter. The system further includes an input portion, a band-pass filter, and an integrate-and-fire mechanism. The input portion outputs a first signal based on the alternating electrical signal. The band-pass filter outputs a first filtered signal based on the first signal. The integrate-and-fire mechanism generates the processed electrical signal based on the first filtered signal. | 02-14-2013 |
| 20150137853 | DELAY PATH SELECTION FOR DIGITAL CONTROL OSCILLATOR - Among other things, one or more techniques or systems for delay path selection are provided. A digitally controlled oscillator comprises an arrangement of inverters, such as tri-state inverters, that are selectively utilized to provide a process, voltage, temperature (PVT) condition output used to generate a frequency output for the digitally controlled oscillator. Delay path interpolation is used to generate a relatively high resolution range of PVT condition outputs, which results in a reduction of frequency gain (KDOC) between PVT condition outputs for improved performance of the digitally controlled oscillator. | 05-21-2015 |
| 327045000 | Including sampling or reference frequency | 1 |
| 20160065215 | CLOCK MONITOR AND SYSTEM ON CHIP INCLUDING THE SAME - A system on chip includes a plurality of function blocks configured to perform predetermined functions, respectively, a clock control unit configured to generate a plurality of operating clock signals that are provided to the plurality of function blocks, respectively, a clock monitor configured to monitor frequencies of the operating clock signals to generate an interrupt signal, and a processor configured to control the frequencies of the operating clock signals based on the interrupt signal. The clock monitor includes a selector configured to select one of the operating clock signals to provide a selected clock signal, a frequency detector configured to detect a frequency of the selected clock signal to provide a detection frequency, and an interrupt generator configured to generate the interrupt signal based on the detection frequency, where the interrupt signal indicates a frequency abnormality of the operating clock signal corresponding to the selected clock signal. | 03-03-2016 |
| 327047000 | Frequency detection | 16 |
| 20080197885 | Circuit for detecting maximal frequency of pulse frequency modulation and method thereof - The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency modulation signals, and includes a first-half pulse-generating module and a second-half pulse-generating module. The delay circuit is connected to the second-half pulse-generating module. The master-slave register includes a clock, an input end and an output end, wherein the input end is connected to the oscillator-controlling unit, and the clock is connected to the delay circuit. | 08-21-2008 |
| 20090140774 | SYSTEM AND METHOD FOR COMMUNICATING DATA AMONG CHAINED CIRCUITS - A system and method are provided for communicating data among chained circuits. In operation, a period of a signal communicated between a chain of circuits is identified. Additionally, a state of the signal is determined, based on the period of the signal. | 06-04-2009 |
| 20100052732 | FREQUENCY DETECTION CIRCUIT - In some preferred embodiments, a switched capacitor circuit configured to change its equivalent resistance depending on the frequency of an input clock signal and a resistor element are connected in series. A power source voltage is divided by the equivalent resistance of the switched capacitor circuit and the resistance of the resistor element, and the divided voltage is inputted to a Schmitt circuit. The Schmitt circuit outputs a high-level signal when the inputted divided voltage is higher than a threshold voltage and a low-level signal when the inputted divided voltage is lower than a threshold voltage. Thus, depending on the frequency of the input clock signal, a high-level signal or a low-level signal is outputted. | 03-04-2010 |
| 20100225357 | REAL TIME CLOCK MONITORING METHOD AND SYSTEM - Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor. | 09-09-2010 |
| 20100231265 | METHOD FOR DETECTING MINIMUM OPERATIONAL FREQUENCY - A method of detecting a minimum operational frequency includes: generating a signal that becomes an oscillating signal at a first predetermined frequency; and generating a logic signal to provide a level transition when a frequency of the oscillating signal reaches a second predetermined frequency corresponding to the minimum operational frequency. The logic signal is generated by: providing a transistor that is activated at the second predetermined frequency; providing a capacitor; storing charges in the capacitor when the oscillating signal is below the second predetermined frequency; discharging the capacitor when the transistor is activated by the oscillating signal; and outputting the logic signal when the capacitor discharges. | 09-16-2010 |
| 20140327472 | FREQUENCY DETECTION APPARATUS WITH INTERNAL OUTPUT VOLTAGE WHICH CHANGES ALONG WITH INPUT SIGNAL FREQUENCY - A frequency detection apparatus includes: a constant current generator, arranged for providing a constant current to a voltage output terminal; a first capacitor, coupled between the voltage output terminal and a first reference voltage; a first transistor, which has a first connection terminal coupled to the voltage output terminal, a control terminal coupled to an input signal; a second connection terminal, coupled between the second connection terminal of the first transistor and the first reference voltage; a second transistor, which has a first connection terminal coupled to the second connection terminal of the first transistor, a second connection terminal coupled to the first reference voltage, a control terminal coupled to an inverted input signal, which is obtained by inverting the input signal; wherein a voltage output of the voltage output terminal changes with an input signal frequency of the input signal. | 11-06-2014 |
| 20150331088 | BROADBAND FREQUENCY DETECTOR - Provided is a broadband frequency detector, more particularly, to a frequency detector detecting all the signals for guiding the safe vehicle operation, and radar signals for determining vehicle speeds. The broadband frequency detector comprises: a horn antenna configured to receive signals having specific frequencies; a first amplifier configured to receive the signals having specific frequencies from the horn antenna; a mixer unit configured to receive signals from the first amplifier, wherein the signals are low noise amplified therein; and a second amplifier, arranged in parallel with the amplifier, for transferring signals to the mixer unit after low noise amplifying the signal received from the horn antenna, wherein the second amplifier includes a transistor and a first microwave circuit unit for matching the impedance of the horn antenna and the impedance of the transistor. | 11-19-2015 |
| 327048000 | With counting | 9 |
| 20090160489 | METHOD AND APPARATUS FOR TIME-DIFFERENTIAL COMPARISON OF AN ANALOG SIGNAL - A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. An evaluation circuit is coupled to the counting circuit. The evaluation circuit is responsive to the count of the cycles of the variable frequency signal after an end of the second time interval. | 06-25-2009 |
| 20100283510 | CLOCK-DETECTING CIRCUIT - A clock-detecting circuit, containing at least a microprocessor, a clock circuit, and a zero-cross detecting circuit. The clock circuit is connected to the microprocessor. The input end of the zero-cross detecting circuit is connected to the utility power AC input. The output end of the zero-cross detecting circuit is connected to the input end of the microprocessor. The zero-cross detecting circuit operates to detect zero crossing points of the utility power AC input. The microprocessor operates to count the number of oscillation periods of the clock circuit in a time interval between two adjacent zero crossing points of the utility power AC input and to detect clock precision of the microprocessor according to the counted number. The circuit according to the invention features simple structure and low production cost, and is reliable and easy to be implemented. | 11-11-2010 |
| 20110062994 | FREQUENCY LEVEL DETECTING METHOD - A frequency level detecting method includes counting pulses of a spread-spectrum clock, the spread-spectrum clock having a frequency that is modulated within a frequency range from a minimum frequency to a maximum frequency in a constant modulation period of time, the frequency range being divided into a plurality of sub-ranges each corresponding to one of a plurality of frequency levels; determining at least one to-be-counted value range corresponding to one of the plurality of sub-ranges; judging whether or not the counted pulses fall within one of the at least one to-be-counted value range; and generating a level detection signal if the counted pulses fall within the one of the at least one to-be-counted value range, the level detection signal indicating that a frequency of the spread-spectrum clock falls within one of the plurality of frequency levels that corresponds to one of the plurality of sub-ranges corresponding to the one of the at least one to-be-counted value range. | 03-17-2011 |
| 20110068828 | Method and System for Detecting Timing Characteristics in a Communications System - The present invention provides a system for detecting timing characteristics of internal signals in a communications device, the system comprising: a system clock running at a known frequency; a test counter having a test input at which an internal signal to be tested is received; a gating counter having an input arranged to receive the system clock signal; and a system controller for controlling the counters; wherein the system controller controls the gating counter to count a predetermined number of system clock cycles to define a test period, and during the test period the test counter counts the cycles of the internal signal under test, whereby timing characteristics of the internal signal may be found with reference to a time base defined by the system clock. An associated method of operation is also described. | 03-24-2011 |
| 20110140739 | FREQUENCY MODULATED SIGNAL DECODING USING A DRIVER - A system for decoding frequency modulated signals includes a glue logic module, a key matrix, and a driver coupled to the key matrix. The glue logic module provides a pre-scaled frequency signal, while the key matrix receives the pre-scaled frequency signal. The driver decodes the pre-scaled frequency signal to generate at least one event update corresponding to a frequency of the pre-scaled frequency signal. | 06-16-2011 |
| 20110140740 | Device and method for testing a frequency-modulated clock generator - A method and a device are described for testing a frequency-modulated clock generator, the device including a cycle counting unit for counting clock cycles of a clock signal of the clock generator in multiple consecutive measuring periods, which are defined, in particular, by a measuring signal having a measuring frequency, and for outputting cycle count values, and including a comparator device for receiving and comparing the cycle count values with each other and for outputting at least one output signal as a function of the comparison. In particular, ascertained maximum and minimum values may be compared with each other. | 06-16-2011 |
| 20120119786 | SEMICONDUCTOR DEVICE - A stop of a detection object clock is detected by inverting a signal level of an output signal of a level output unit at a count completion time at a counter unit operated by a detection clock and of which count value is changeable, and by determining whether or not a signal level change passes through a clock detection unit operated by the detection object clock by comparing signal levels of an output signal of a level output unit and an output signal of a clock detection unit. | 05-17-2012 |
| 20120161815 | METHOD AND APPARATUS FOR TIME-DIFFERENTIAL COMPARISON OF AN ANALOG SIGNAL - A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. The counting circuit outputs a digital count signal and an evaluation circuit is coupled to generate a decision signal in response to the digital count signal after an end of the second time interval. The first time interval is not equal to the second time interval to generate an offset in the decision signal. | 06-28-2012 |
| 20130057316 | METHOD AND APPARATUS FOR TIME-DIFFERENTIAL COMPARISON OF AN ANALOG SIGNAL - A time-differential analog comparator includes a variable frequency signal source, a timing circuit, a counting circuit, and an evaluation circuit. The variable frequency signal source provides a repeating signal having a frequency corresponding to a value of an analog input. The timing circuit defines a timing sequence including a first time interval and a second time interval and generates a mode select signal at a time between the first time interval and the second time interval to stimulate a change in the analog input. The counting circuit is coupled to the timing circuit to count the periods of the repeating signal. The evaluation circuit coupled generates a decision signal in response to a count of the periods of the repeating signal indicated by the counting circuit. The first time interval is not equal to the second time interval to generate an offset in the decision signal. | 03-07-2013 |
