| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327023000 | By pulse coincidence | 7 |
| 20100271072 | DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME - There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result. | 10-28-2010 |
| 20150123710 | CROSS-CONDUCTION DETECTOR FOR SWITCHING REGULATOR - An integrated circuit includes a detector configured to monitor a high-drive signal and a low-drive signal that drives a high-side switch and a low-side switch respectively of an integrated circuit switching regulator. The detector monitors both the rising edge and the trailing edge of each of the high-drive and the low-drive signals respectively to determine a timing overlap between the signals and generates a detection signal indicating a dead-time value proportional to the presence or absence of the timing overlap between the signals. An output circuit can be configured to process the detection signal from the detector to enable a correction of the timing overlap between the signals if timing overlap is detected. | 05-07-2015 |
| 327024000 | Edge sensing | 4 |
| 20080265946 | Electric Circuit for and Method of Generating a Clock Signal - An electric circuit ( | 10-30-2008 |
| 20090160488 | Apparatus and method for clock signal synchronization in JTAG testing in systems having modules processing clock signals at different rates - In a test and debug system in which a plurality of modules under test have different operational rates, the system clock and the return clock signals from the modules lose synchronism. An error signal is produced when the clock signal makes a transition to a logic state that is the same logic state of the return clock signal of all of the modules. Apparatus is provided for generating logic signals when all of the return clock signals are in the same logic state. Two logic states are possible for all the return clock signals. A current state is latched until all the return clock signals are in the other state, at which time the second logic signal state is latched. The apparatus can be reset by an external signal. | 06-25-2009 |
| 20100102854 | CIRCULAR EDGE DETECTOR - A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell. | 04-29-2010 |
| 20120280718 | SMART EDGE DETECTOR - This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering. | 11-08-2012 |
| 327027000 | With reference | 1 |
| 20100052731 | MULTIPLE CHANNEL BALLAST AND NETWORKABLE TOPOLOGY AND SYSTEM INCLUDING POWER LINE CARRIER APPLICATIONS - Control systems and methods for independent control of power systems, particularly lighting network branches, and separate control of individual branch components. Multi-branch systems comprise independently controllable branches that inter-communicate via PLC communications. In each branch, components such as ballasts, local control units, sensors, actuators, and repeaters, may exchange commands and queries independently of a branch remote control unit (BRCU). Alternatively, a BRCU may manage or arbitrate communications, or interact with other BRCUs, other control units and external management systems. Ballasts include a multi-channel ballast that enables close-loop control of individual fixtures, or of individual dimmable or non-dimmable lamps within a fixture. The close-loop control is facilitated by sampling circuits/sensors co-located with each controlled fixture or lamp. All controllers are preferably implemented using an integrated digital controller. The PLC communication is preferably carried out by a direct spread spectrum method that eliminates side lobes from a cross-correlation function, using an anti-collision protocol. | 03-04-2010 |
