| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327050000 |
By amplitude
| 584 |
| 327002000 |
By phase
| 103 |
| 327039000 |
By frequency
| 48 |
| 327031000 |
By pulse width or spacing
| 28 |
| 327018000 |
By presence or absence pulse detection
| 19 |
| 327099000 |
Having selection between plural continuous waveforms
| 9 |
| 327023000 |
By pulse coincidence
| 7 |
| 327098000 |
By separating composite signal | 5 |
| 20090189648 | Clock Signal Recovery Device and Method for Recovering Clock Signals - A clock signal recovery device has a digital data signal input for the input of a digital data signal and a clock signal output for the output of a recovered clock signal. The digital data signal has a given nominal clock signal frequency. The clock signal recovery device is a digital circuit. | 07-30-2009 |
| 20100013520 | CIRCUIT FOR CLOCK EXTRACTION FROM A BINARY DATA SEQUENCE - The invention relates to an electronic circuit making it possible to extract a clock signal from an incident binary data sequence arriving at a constant rate. The electronic circuit comprises an oscillator (VCO) with voltage-controlled frequency providing a sinusoidal signal, a circuit (R, Cp, RD, I | 01-21-2010 |
| 20110221478 | CIRCUIT FOR MULTIPLEXING DIGITAL AND ANALOG INFORMATION VIA SINGLE PIN OF DRIVER FOR SWITCHED MOSFETS OF DC-DC CONVERTER - Multiple characteristics of a DC-DC converter, such as its mode of operation (e.g., either forced continuous conduction mode, or discontinuous conduction mode), and an operational parameter (such as the dead-time between switching times of the output switching devices (upper and lower MOSFETs) of the converter, whose associated driver integrated circuit has a pin usage that leaves only a single pin available for auxiliary purposes, are programmed by a single pin-based digital and analog information extracting circuit that couples both digital information and analog information within the same control signal to the driver IC by way of only the one available pin. | 09-15-2011 |
| 20130147521 | METHOD AND APPARATUS FOR AN ENERGY-EFFICIENT RECEIVER - One or more circuits may comprise at least one first-type analog-to-digital converter (ADC) and at least one second-type ADC. The circuit(s) may be operable to receive a plurality of signals, each of which may comprise a plurality of channels. The circuit(s) may be operable to digitize a selected one or more of the channels. Which, if any, of the selected channels are digitized via the at least one first-type ADC and which, if any, of the selected channels are digitized via the at least one second-type ADC, may be based on which of the plurality of channels are the selected channels and/or based on power consumption of the circuit(s). A bandwidth of each first-type ADC may be on the order of the bandwidth of one of the received signals. A bandwidth of each second-type ADC may be on the order of the bandwidth of one of the plurality of channels. | 06-13-2013 |
| 20140210519 | Combined Sense Signal Generation and Detection - In an exemplary implementation, a detection circuit for regulating a power converter is configured to receive a combined sense signal comprising a first sense signal from the power converter superimposed with a second sense signal from the power converter. The detection circuit is further configured to generate a first detect signal from the combined sense signal and generate a second detect signal from the combined sense signal. The first detect signal can correspond to the first sense signal and the second detect signal can correspond to the second sense signal. The detection circuit can generate a filtered signal corresponding to the first sense signal from the combined sense signal to generate the first detect signal from the combined sense signal. Also, the detection circuit can generate an offset signal based on the combined sense signal to generate the second detect signal from the combined sense signal. | 07-31-2014 |
| 327013000 |
By shape | 4 |
| 20110140738 | Multi-Phase Integrators in Control Systems - Multi-phase integrators in control systems are described. | 06-16-2011 |
| 20110018585 | METHODS, SYSTEMS AND ARRANGEMENTS FOR EDGE DETECTION - A variety of edge-detection related devices, methods and systems are implemented in various fashions. One implementation is directed to an edge detector circuit ( | 01-27-2011 |
| 20120280717 | Method For Arc Detection And Devices Thereof - A method for arc detection includes detecting a changing rate of a signal indicative of light strength, detecting the amplitude of the signal, and indicating an occurrence of an arc if the changing rate of the signal exceeds a first predetermined threshold and the amplitude of the signal exceeds a second predetermined threshold. An arc detecting device, an arc detecting system, and an arc protecting apparatus thereof are provided. The arc detecting system includes a light collector ( | 11-08-2012 |
| 20130271182 | PROXIMITY SWITCH ASSEMBLY AND ACTIVATION METHOD USING RATE MONITORING - A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field of each proximity switch to sense activation. The control circuitry monitors the signal responsive to the activation field and determines a differential change in generated signal, and further generates an activation output when the differential signal exceeds a threshold. The control circuitry further distinguishes an activation from an exploration of the plurality of switches and determines activation upon detection of a stable signal. The control circuit further determines a rate of change and generates an output when the rate of change exceeds a threshold rate to enable activation of a switch. | 10-17-2013 |
| 327022000 |
By pulse noncoincidence | 2 |
| 20080231325 | METHOD FOR CHECKING THE INTEGRITY OF A CLOCK TREE - A method and device detect synchronization errors between logic signals of a group of logic signals. A control word is loaded into a shift register arranged in loop and clocked by resulting logic signals equal to the result of the OR logic function and to the result of the AND logic function applied to the logic signals of the group of logic signals. The value of the control word is monitored as it propagates in the shift register, and a synchronization error signal is sent if the control word changes value. Application in particular for checking the integrity of a clock tree in an integrated circuit. | 09-25-2008 |
| 20130300458 | Clock Signal Synchronization Circuit - A circuit for detecting a time skew, including: at least two comparators; a first set of paths respectively connecting a first source of a first signal to said comparators; and a second set of paths respectively connecting a second source of a second signal to said comparators, each comparator detecting a possible skew between said first and second signals. | 11-14-2013 |
| Entries |
| Document | Title | Date |
|---|
| 20080238487 | Duty cycle comparator - A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals. | 10-02-2008 |
| 20080246515 | SYSTEM TO REDUCE PROGRAMMABLE RANGE SPECIFICATIONS FOR A GIVEN TARGET ACCURACY IN CALIBRATED ELECTRONIC CIRCUITS - An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal. | 10-09-2008 |
| 20090058466 | DIFFERENTIAL PAIR CIRCUIT - A differential pair circuit includes a first transistor having a first control terminal, a first input terminal, and a first output terminal; a second transistor having a second control terminal, a second input terminal, and a second output terminal, a first buffer stage including a third transistor having a third control terminal, a third input terminal, and a third output terminal; and a second buffer stage including a fourth transistor having a fourth control terminal, a fourth input terminal, and a fourth output terminal. The first output terminal and the second output terminal are electrically connected; the third output terminal and the first control terminal are electrically connected; the fourth output terminal and the second control terminal are electrically connected; the first input terminal and the fourth input terminal are electrically connected; and the second input terminal and the third input terminal are electrically connected. | 03-05-2009 |
| 20100079170 | APPARATUS AND METHOD FOR THE ANALYSIS OF A PERIODIC SIGNAL - An apparatus and method for the analysis of a periodic signal. One embodiment provides signal values. Signs are assigned to the signal values. The signed signal values are summed to a first sum. At least one signal property is determined on the basis of the first sum. | 04-01-2010 |
| 20100182048 | MULTIFUNCTION WORD RECOGNIZER ELEMENT - A circuit includes a load; a first differential pair coupled to the load and responsive to input data; a second differential pair coupled to the load and responsive to the input data; a third differential pair coupled to the first differential pair and the second differential pair and responsive to a first control signal and a second control signal; a bias circuit configured to pull a node coupled to both the first differential pair and the second differential pair to a predetermined state; and a current source coupled to the third differential pair and the bias circuit. | 07-22-2010 |
| 20100308867 | SEMICONDUCTOR DEVICE AND ABNORMALITY PREDICTION METHOD THEREOF - A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of the first CPU with an output of the second CPU. The second CPU is made so as to have a lower operating margin than the first CPU. By supplying a same signal to the first CPU and the second CPU and then detecting a mismatch between the outputs of the first CPU and the second CPU as a result of comparison, the abnormality is predicted. The semiconductor device includes a reset control circuit that resets the device when the result of comparison by the comparator indicates an error. | 12-09-2010 |
| 20110032001 | TEMPERATURE DETECTION CIRCUIT - According to one embodiment, a temperature detection circuit is provided which requires only a small number of additional components, thus minimizing an increase in costs and which offers an insulating property and high responsiveness. A temperature detection circuit outputs a first PWM signal corresponding to a temperature of a first temperature sensor from a photointerrupter as a signal insulated from the first temperature sensor. A temperature detection circuit outputs a second PWM signal corresponding to a temperature of a second temperature sensor from a photointerrupter as a signal insulated from the second temperature sensor. A controlling arithmetic apparatus calculates a higher one of the temperatures detected by the first and second temperature sensors based on the PWM signals output from the photointerrupter. | 02-10-2011 |
| 20120019285 | METHOD AND APPARATUS FOR FAST WAKE-UP OF ANALOG BIASES - Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal. | 01-26-2012 |
| 20120200317 | FEEDFORWARD/FEEDBACK CONTROL SYSTEM FOR INDUSTRIAL WATER SYSTEMS - A control system is disclosed for monitoring and controlling an industrial water system comprising (a) obtaining a priori knowledge about the correlation between water and treatment chemistry and equipment health; (b) pre-defining a set of operating regions of more than one feed-water or system water variable and at least one chemical treatment variable, where, based on (a) above, corrosion, scaling and fouling are inhibited; (c) adjusting the at least one chemical treatment variable according to the more than one feed water or system water variable, such that based on (a), corrosion, scaling and fouling are inhibited. | 08-09-2012 |
| 20130015885 | QUBIT READOUT VIA RESONANT SCATTERING OF JOSEPHSON SOLITONSAANM NAAMAN; OFERAACI Ellicot CityAAST MDAACO USAAGP NAAMAN; OFER Ellicot City MD USAANM Park; Jae I.AACI BoulderAAST COAACO USAAGP Park; Jae I. Boulder CO USAANM Pesetski; Aaron A.AACI GambrillsAAST MDAACO USAAGP Pesetski; Aaron A. Gambrills MD US - Systems and methods are provided for reading an associated state of a qubit. A first soliton is injected along a first Josephson transmission line coupled to the qubit. A velocity of the first soliton is selected according to a physical length of the qubit and a characteristic frequency of the qubit. A second soliton is injected at the selected velocity along a second Josephson transmission line that is not coupled to the qubit. A delay associated with the first soliton is determined relative to the second soliton. | 01-17-2013 |
| 20130049809 | MICRO ELECTRO-MECHANICAL SYSTEM CIRCUIT CAPABLE OF COMPENSATING CAPACITANCE VARIATION AND METHOD THEREOF - A micro electro-mechanical system (MEMS) circuit includes a MEMS differential capacitor, a read-out circuit, a control circuit, and a compensation circuit. The MEMS differential capacitor includes a first capacitor and a second capacitor. The read-out circuit is coupled to the MEMS differential capacitor for reading a difference between the first capacitor and the second capacitor in a zero-G condition, and generating an output signal according to the difference. The control circuit is coupled to the read-out circuit for receiving the output signal and generating a control signal. The compensation circuit is coupled to the control circuit for compensating the MEMS differential capacitor according to the control signal. | 02-28-2013 |
| 20130076397 | METHOD AND CIRCUIT CONFIGURATION FOR DETERMINING POSITION MINUS TIME - A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out. | 03-28-2013 |
| 20130328594 | Divider, Method for Providing an Output Signal and Edge Tracker - A divider for providing an output signal having an output frequency by dividing a reference frequency of a reference signal by a divider value is disclosed. The divider includes at least a first divider element configured to provide a first divider output signal having a first divider output signal frequency which is half of the reference frequency and a last divider element configured to provide a last divider output signal having a last divider output signal frequency which half of the preceding divider output signal frequency. Furthermore, the divider comprises an output signal provider for providing the output signal. | 12-12-2013 |
| 20130342239 | INVALID SIGNAL FILTERING METHOD AND SHIFTER UTILIZING THE METHOD - A shifter with invalid signal filtering mechanism, comprising: a first shifting stage, for receiving and capturing an input signal in a first clock cycle; and a second shifting stage, after the first shifting stage, for receiving the input signal from the first shifting stage, and for receiving a validity signal indicating whether the input signal is valid or invalid, before a second clock cycle next to the first clock cycle occurs; wherein the second shifting stage captures the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is valid, where the second shifting stage does not capture the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is invalid. | 12-26-2013 |
| 20140049290 | INTEGRATED CIRCUIT - There is disclosed an integrated circuit comprising a management unit for managing the occurrence of predetermined events in the integrated circuit. The management unit comprises: a processing unit adapted to determine the occurrence of a predetermined event in the integrated circuit; a data storage unit adapted to store information regarding the determined event occurrence; an output interface adapted to output a signal based on the stored information regarding the determined event occurrence; and an output generating unit adapted to analyse the stored information and to generate a signal to be output by the output interface based on results of the analysis. | 02-20-2014 |
| 20140118027 | Mixed-Mode Circuits - An apparatus for processing signals, arranged on an integrated circuit, comprises at least one analog input port that receives an input signal from outside of the integrated circuit, and a detector that detects an operation state of the apparatus based on the input signal. The detector provides at least one digital control/enable signal, which is dependent on the operation state of the apparatus, to another apparatus arranged on the integrated circuit. | 05-01-2014 |
| 20160131696 | UNIT AND METHOD FOR MONITORING AN INTEGRITY OF A SIGNAL PATH, SIGNAL PROCESSING SYSTEM AND SENSOR SYSTEM - A monitoring unit ( | 05-12-2016 |
