Class / Patent application number | Description | Number of patent applications / Date published |
327018000 | By presence or absence pulse detection | 19 |
20100019803 | OSCILLATION DETECTION CIRCUIT - An oscillation detection circuit according to the present invention has a differential circuit by a bipolar transistor where oscillation output of an oscillation circuit is inputted; a capacitance element that is connected to an output terminal of this differential circuit and charges or discharges in response to potential of the output terminal; and a detection circuit that detects a desired oscillation state of an oscillation signal terminal based on potential of this capacitance element. | 01-28-2010 |
20100045345 | AC DIFFERENTIAL CONNECTION ASSEMBLY BETWEEN A TRANS-IMPEDANCE AMPLIFIER AND A POST AMPLIFIER FOR BURST MODE RECEIVING - An AC differential connection assembly between a trans-impedance amplifier and a post amplifier for burst mode receiving comprising means for coupling a differential output of the trans-impedance amplifier to a differential input of the post amplifier, the means for coupling comprises a coupling capacitor assembly; and a switching circuit coupled across the differential input of the post amplifier, the switching circuit having an ‘on’ state with low impedance and an ‘off’ state with high impedance; wherein during burst mode receiving, the switching circuit is in the ‘off’ state and the coupling capacitor assembly having a time constant to maintain a stable DC level such that a payload is received accurately by the differential input of the post amplifier; and during an idle period, the switching circuit is in the ‘on’ state and the coupling capacitor assembly having a time constant to recover a DC level of the differential output of the trans-impedance amplifier. | 02-25-2010 |
20100277203 | Edge-Missing Detector Structure - An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2π. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock. | 11-04-2010 |
20110169529 | METHOD AND APPARATUS FOR SELECTING AN OPERATING MODE BASED ON A DETERMINATION OF THE AVAILABILITY OF INTERNAL CLOCK SIGNALS - A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 07-14-2011 |
20120176159 | Systems and methods for precise event timing measurements - Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events. | 07-12-2012 |
20120206166 | CIRCUIT FOR DETECTING AND PREVENTING SETUP FAILS AND THE METHOD THEREOF - A circuit for preventing a setup fail between a first latch and a second latch according to one embodiment of the present invention comprises a mimic combinational logic module and a clock compare module. The mimic combinational logic module is configured to receive a first clock signal for the first latch and to generate a delayed first clock signal, which is a delayed version of the first clock signal. The clock compare module is configured to provide a delayed second clock signal, which is a delayed version of a second clock signal for the second latch, to the second latch after receiving the delayed first clock signal and the second clock signal. | 08-16-2012 |
327020000 | Monitoring (e.g., failure detection, etc.) | 13 |
20080238488 | Methods and apparatus for power monitoring with sequencing and supervision - Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein comprises supervising a first power rail and a second power rail, sequencing a first enable signal associated with the first power rail and a second enable signal associated with the second power rail, and determining whether the first power rail is enabled based on regulation information determined while supervising the first power rail. | 10-02-2008 |
20080272808 | Means To Detect A Missing Pulse And Reduce The Associated PLL Phase Bump - A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop. | 11-06-2008 |
20080303555 | Tone detector - A tone detector is disclosed that is realizable in digital embodiment on a single integrated circuit die and does not require external components, such as a discrete capacitor. An input connects to a comparator, which in turn connects to one or more edge detectors and a flip flop. The edge detector outputs a pulse responsive to a detected edge. A counter is reset by the pulses from the edge detectors thereby preventing the counter from reaching a maximum value, which would otherwise be output from the counter and provided to a flip flop to clock in the comparator output at the D input to the flip flop. In operation, the comparator generates a rail to rail signal responsive to a received tone, which in turn is clocked through the flip flop as a logic high output indicating presence of a tone. | 12-11-2008 |
20100052730 | METHOD AND APPARATUS FOR LATE TIMING TRANSITION DETECTION - Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed. | 03-04-2010 |
20100085082 | TERNARY SENSOR INPUTS - One of a first signal, a second signal, and a third signal is received respectively from each of three inputs. A pattern formed by the first signal, the second signal, and the third signal is compared to a set of predetermined patterns. Based on the comparing, it is determined whether an error exists. If an error condition exists, a specific one of the inputs is identified as a cause of the error. | 04-08-2010 |
20100171528 | APPARATUS FOR DETECTING CLOCK FAILURE AND METHOD THEREFOR - A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. The counter comprises a reset input arranged to receive successive reset pulses generated by at least one clock edge of the input clock signal to reset a counter value of the counter. The counter value before reset is used to identify a clock frequency error. A method of detecting a clock failure is also described. By using a counter value based on the reference clock cycles, and a reset trigger based on a clock edge of the input signal, it is possible to identify a clock frequency error in a much shorter time. | 07-08-2010 |
20100308868 | CLOCK SUPERVISION UNIT - The present invention relates to a clock supervision unit ( | 12-09-2010 |
20100327913 | DETECTION OF BAD CLOCK CONDITIONS - There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal. | 12-30-2010 |
20110018586 | SIGNAL JUDGEMENT CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC EQUIPMENT - To provide a signal judgement circuit that makes a judgement on signals received via at least four or more signal lines and enhances robustness and redundancy. | 01-27-2011 |
20120194221 | ADVANCED CONVERTERS FOR MEMORY CELL SENSING AND METHODS - A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output. | 08-02-2012 |
20130038352 | CIRCUITS AND METHODS FOR CLOCK MALFUNCTION DETECTION - Circuit for detecting malfunction of a primary clock in SoCs comprises a primary clock circuit having a GRAY code counter for generating a GRAY code sequence based on a number of clock pulses generated Primary clock. A secondary clock circuit is configured to output a secondary clock pulse on each saturation of a secondary clock counter. A clock gated register circuit is clocked by the secondary clock pulse, and is configured to store a plurality of values of the GRAY code sequence, and update the plurality of values of the GRAY code sequence on each saturation of the secondary clock counter. An error detection circuit is configured to output a detection signal for detecting the malfunction of primary clock based on a comparison of the updated plurality of values of the GRAY code sequence with at least one predetermined threshold associated with the malfunction of primary clock. | 02-14-2013 |
20140043064 | DETECTION OF BAD CLOCK CONDITIONS - There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal. | 02-13-2014 |
20150381158 | Device and method for clock signal loss detection - A device, comprises a first counter and a second counter, a control unit and a comparing unit. The first counter and the second counter are configured to alternately count a cycle number of a monitoring clock signal. The control unit is configured to generate, based on an input clock, both a first counter enable signal and a second counter enable signal that enable or disable the first and the second counters respective, and the first counter enable signal and the second counter enable signal are inverted. The comparing unit is coupled to both the first counter and the second counter and configured to detect a loss fault of the input clock if the cycle number of the monitoring signal counted by one of the first and the second counters exceed a predetermined threshold. | 12-31-2015 |