| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327003000 | Comparison between plural inputs (e.g., phase angle indication, lead-lag discriminator, etc.) | 87 |
| 20080265945 | PHASE FREQUENCY DETECTOR WITH LIMITED OUTPUT PULSE WIDTH AND METHOD THEREOF - Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first-type edges of a first signal to generate a first detection signal. The second edge detector is for detecting the first-type edges of a second signal to generate a second detection signal. The pulse reshaping controller is for receiving the first detection signal and the second detection signal, and for generating a first control signal to the first edge detector and generating a second control signal to the second edge detector. In addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller. | 10-30-2008 |
| 20090140773 | Phase detection apparatus and phase synchronization apparatus - A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit. | 06-04-2009 |
| 20090160487 | Phase and frequency detector with zero static phase error - A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced. | 06-25-2009 |
| 20090174436 | INPUT SIGNAL LEVEL DETECTION APPARATUS AND METHOD - A method and an input signal level detection apparatus that correctly detect a level of an input signal while consuming low power apparatus including: a full-wave rectifier outputting a full-wave rectified waveform by performing a full-wave rectification on a first signal corresponding to an input signal, and on a second signal having a phase difference of 180 degrees from the first signal; a common voltage detector detecting a common voltage of the first signal and the second signal; and a level detection unit detecting a level of the input signal, based on a subtraction result obtained by subtracting the common voltage from the full-wave rectified waveform. | 07-09-2009 |
| 20090219055 | Signal Comparison Circuit and Power Conversion Device - The voltage deviation is converted into the time quantity with the first integration circuit for the voltage detection and the second integration circuit for the voltage detection. The current setting value and the current measurements are converted into the time quantity with the second integration circuit for the current control to which the first integration circuit for the current control from which the voltage value of the set current value corresponding is input and the voltage value of the value of the current of the inductor corresponding are input and it controls. And, the start of the first integration circuit for the current control is delayed with operation quantity signal generation circuit only at the time that the high-resolution evaluation or more than the start of the first integration circuit for the current control and corresponds to the voltage deviation. | 09-03-2009 |
| 20090237115 | SINGLE-PHASE 3-WIRE POWER LINE CONNECTION DETERMINATION APPARATUS AND CONNECTION DETERMINATION METHOD - In a method for determining whether multiple power outlets in a 3-wire power line connection are connected to a same outer wire (P | 09-24-2009 |
| 20090237116 | RECEIVING DEVICE - A receiving device for receiving a parallel-data including a clock and a plurality of data signals, the receiving device includes a plurality of data capturing circuits for receiving the data signal and the clock, respectively, the data capturing circuit capturing the data signal of the parallel-data on the bases of the clock; a plurality of phase comparing circuits for receiving the data signal and the clock, respectively, the phase comparing circuit capturing the clock of the parallel-data on the bases of the each data in order to compare a phase between the clock and the data signal; and an aggregating circuit for monitoring a relationship between the clock and the data signals on the bases of comparison results from the plurality of phase comparing circuits. | 09-24-2009 |
| 20100001764 | Configurable Differential Lines - Embodiments related to configurable differential lines are disclosed herein. | 01-07-2010 |
| 20100007383 | METHOD AND APPARATUS FOR GENERATING A PHASE DEPENDENT CONTROL SIGNAL - A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship. | 01-14-2010 |
| 20100019800 | VERNIER PHASE ERROR DETECTION METHOD - A vernier phase error detection method is provided. The method comprises providing a first signal having a first cycle T | 01-28-2010 |
| 20100090723 | Symmetric Phase Detector - In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases. | 04-15-2010 |
| 20100194440 | Phase Error De-Glitching Circuit and Method of Operating - A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal. | 08-05-2010 |
| 20100201402 | Phase Error De-Glitching Circuit and Method of Operating - A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal. | 08-12-2010 |
| 20110068827 | PASSIVE CAPACITIVELY INJECTED PHASE INTERPOLATOR - A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal. Additionally, the phase-interpolator circuit may include a biasing circuit that provides a DC bias to the weighting circuit, and which amplifies the output of the weighting circuit to provide the output signal. | 03-24-2011 |
| 20110156757 | INTER-PHASE SKEW DETECTION CIRCUIT FOR MULTI-PHASE CLOCK, INTER-PHASE SKEW ADJUSTMENT CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - An inter-phase skew detection circuit includes a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks; a phase comparison target clock generation circuit that generates N phase comparison target clocks by using predetermined N frequency-divided clocks among the N+2 frequency-divided clocks; a phase comparison reference clock generation circuit that generates N reference clocks by using the N+2 frequency-divided clocks, in accordance with predetermined combinations between the N+2 frequency-divided clocks and an operation criterion; and a phase comparison circuit that detects respective phase differences between the N phase comparison target clocks and the corresponding N reference clocks. | 06-30-2011 |
| 20110221476 | PHASE FREQUENCY DETECTOR - The present invention relates to a phase frequency detector (PFD) ( | 09-15-2011 |
| 20110279147 | APPARATUS AND METHOD FOR PHASE SYNCHRONIZATION IN RADIO FREQUENCY TRANSMITTERS - Apparatus and methods are disclosed related to phase synchronization in transmitters. One such apparatus includes a wireless transmitter with two or more separate and unrelated local oscillators. The apparatus can provide RF signals to multiple antenna elements, which can be implemented in systems such as beamforming systems or multiple input multiple output (MIMO) systems. A phase difference between local oscillators is determined using outputs of receivers. The phase difference can be used to adjust a phase of signals associated with one or more of the local oscillators, such that the phase of each signal provided to the multiple antenna elements can be aligned. | 11-17-2011 |
| 20120001656 | Apparatus, System, and Method for Direct Phase Probing and Mapping of Electromagnetic Signals - An apparatus, system, and method for phase detection of electromagnetic signals are presented. The apparatus may include a magnetic element, one or more first signal contacts coupled to the magnetic element for receiving a first signal, and one or more output contacts coupled to the magnetic element for providing a variable level voltage generated by the magnetic element, the level of the voltage being responsive to a phase difference between the first signal and a second signal. In a further embodiment, the apparatus may include a substrate for mechanically supporting the magnetic element. Additionally, the apparatus may include a conductor mechanically supported by substrate, the conductor configured to receive the second signal. | 01-05-2012 |
| 20120126854 | FREQUENCY REGENERATION CIRCUIT AND FREQUENCY REGENERATION METHOD - A frequency regeneration circuit according to the present invention compares a width of a single pulse of input data with a time width of a 1/n clock cycle defined by a phase difference of multi-phase clock signals (where n is a natural number) in order to regenerate a frequency that is 1/n of a rate of the input data. | 05-24-2012 |
| 20120319734 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A PHASED-LOCKED LOOP CIRCUIT - A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal. Based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal. Based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled. | 12-20-2012 |
| 20130027086 | CHARGE PUMP - A charge pump includes a first current source unit and a second current source unit. The first current source unit is connected between a first voltage terminal and the control node. The second current source unit is connected between the control node and a second voltage terminal. According to a phase comparing signal, the first current source unit provides a first switching current to the control node. The second current source unit includes a first sub-switching current generator, a second sub-switching current generator and a select circuit. According to a voltage level of the phase comparing signal, the first sub-switching current generator generates a first sub-switching current. According to the voltage level of the phase comparing signal, the second sub-switching current generator generates a second sub-switching current. By the select circuit, the first sub-switching current or the second sub-switching current is provided to the control node. | 01-31-2013 |
| 20130038351 | PHASE DETECTOR - A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals. | 02-14-2013 |
| 20130222013 | PHYSICAL UNCLONABLE FUNCTION CELL AND ARRAY - A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value. | 08-29-2013 |
| 20130257482 | Sub-band Processing Complexity Reduction - A sub-band processing system that reduces computational complexity and memory requirements includes a processor and a local or distributed memory. Logic stored in the memory partitions a frequency spectrum of bins into a smaller number of sub-bands. The logic enables a lossy compression by designating a magnitude and a designated or derived phase of each bin in the frequency spectrum as representative. The logic renders a lossless compression by decompressing the lossy compressed data and providing lost data based on original spectral relationships contained within the frequency spectrum. | 10-03-2013 |
| 20140077841 | PHASE FREQUENCY DETECTOR - Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference. | 03-20-2014 |
| 20140159775 | CLOCK PHASE SHIFT DETECTOR - A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal. | 06-12-2014 |
| 20140340120 | Techniques for Phase Detection - A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase. | 11-20-2014 |
| 20150109028 | CONTINUOUS FREQUENCY MEASUREMENT FOR PREDICTIVE PERIODIC SYNCHRONIZATION - Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous system using an array of digital frequency measurement circuits that provide overlapping frequency and detection interval measurements within single counter periods required for a single frequency measurement circuit to complete a frequency measurement. Embodiments may be used in a predictive synchronizer to provide low latency, continuous frequency measurements for system-on-chip (SOC) devices that employ frequency drift or ramping to reduce power consumption and overheating conditions. | 04-23-2015 |
| 327005000 | With input derived from feedback | 7 |
| 20080290903 | METHOD AND RADIATION HARDENED PHASE FREQUENCY DETECTOR FOR IMPLEMENTING ENHANCED RADIATION IMMUNITY PERFORMANCE - A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD. | 11-27-2008 |
| 20090273371 | PHASE COMPARATOR, PHASE SYNCHRONIZING CIRCUIT, AND PHASE-COMPARISON CONTROL METHOD - A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the referred signal. The phase comparator also includes a phase-difference detecting unit that detects a phase difference between the edge of the reference signal and the edge of the referred signal. The phase comparator also includes a phase-difference-signal output unit that outputs a phase-difference signal for current control based on the phase difference. The phase comparator also includes an input-break detecting unit that detects an input break of the reference signal when an edge of the referred signal is again detected after an edge of the referred signal is detected and before an edge of the reference signal is detected. | 11-05-2009 |
| 20100327912 | DIGITAL PHASE-LOCKED LOOP AND DIGITAL PHASE-FREQUENCY DETECTOR THEREOF - A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal. | 12-30-2010 |
| 20110128044 | TEST APPARATUS, TEST METHOD, AND PHASE SHIFTER - A test apparatus includes a recovered clock generating circuit generating a recovered clock having substantially the same phase as an output of a device under test (DUT), a data acquiring section acquiring a value of the output data at a timing indicated by a strobe signal based on the recovered clock, a comparator comparing the value acquired by the data acquiring section to a prescribed expected value, and a judging section judging pass/fail of the DUT based on a comparison result. The recovered clock generating circuit includes a phase comparator comparing the phase of the output data of the DUT to the phase of the recovered clock, a control signal generating section generating a control signal such that the phase of the recovered clock is synchronized with the phase of the output data, and a phase shifter continuously shifting the phase of the reference clock based on the control signal. | 06-02-2011 |
| 20120306538 | Phase Detection Circuits and Methods - A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit causes the fourth periodic signal to be based on a second combination of the first periodic signal and the second periodic signal to provide a different relative phase shift. The phase detector also includes a comparison circuit that compares a measure of the power of the third periodic signal to a measure of the power of the fourth periodic signal to generate the phase comparison output signal. | 12-06-2012 |
| 20140333346 | PHASE-ROTATING PHASE LOCKED LOOP AND METHOD OF CONTROLLING OPERATION THEREOF - A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code. | 11-13-2014 |
| 20150008960 | DIGITAL PHASE DETECTOR - According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase. | 01-08-2015 |
| 327007000 | With reference signal | 25 |
| 20090121746 | FRACTIONAL-N FREQUENCY SYNTHESIZER - A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value. | 05-14-2009 |
| 20090243660 | Mutual charge cancelling sample-reset loop filter for phase locked loops - In general, in one aspect, an apparatus includes a phase frequency detector, a charge pump, a voltage controlled oscillator, an integral capacitor to maintain an integral charge and provide an integral voltage, and a mutual-charge canceling sample reset (MCSR) capacitor to maintain a proportional charge and provide a proportional voltage each reference clock cycle. The MCSR includes a first proportional capacitor, a second proportional capacitor in parallel to, and having substantially identical capacitance value as, the first proportional capacitor, a first set of switches to provide direct coupling of the first and second proportional capacitors, and a second set of switches to provide cross coupling of the first and second proportional capacitors. The first and second set of switches alternatively turn on and off every reference clock cycle so that set of switches coupling the first and second proportional capacitors alternates every reference clock cycle. | 10-01-2009 |
| 20100019801 | APPARATUS, TEST APPARATUS AND METHOD FOR DETECTING A CHANGING POINT OF MEASURED SIGNAL - Provided is an apparatus comprising a delaying section that generates a plurality of delayed signals by delaying a single first input signal by different delay amounts; a first acquiring section that acquires each of a plurality of input second input signals at a first phase of a reference clock; a second acquiring section that acquires each of the plurality of second input signals at a second phase of the reference clock, which is different from the first phase; and a change point detecting section that detects a change point of one of the first input signal and a second input signal, based on values of the plurality of signals acquired by the first acquiring section and values of the plurality of signals acquired by the second acquiring section. | 01-28-2010 |
| 20100123482 | PHASE DETECTOR CIRCUITRY - Phase detector circuitry for a phase-locked loop frequency synthesizer, the phase detector circuitry comprising
| 05-20-2010 |
| 20100171526 | PHASE-DISCRIMINATING DEVICE AND METHOD - A high-accuracy and computational efficient phase-discriminating device is provided and includes a phase-discriminating unit. The phase-discriminating unit converts an input and a reference signals into an input and a reference sequences respectively by a one-bit A/D conversion operation, determines a first value, an in-phase component and a quadrature component of the input signal in response to the input and the reference sequences, and produces an estimated phase of the input signal according to a relation among the first value, the in-phase component and a polarity of the quadrature component, wherein the first value is a certain integer being one of a first integer and a second integer, the first integer is a sampling count of the one-bit A/D conversion operation for producing the input sequence, and the second integer is a summation of an absolute value of the in-phase component and that of the quadrature component. | 07-08-2010 |
| 20100171527 | PHASE COMPARATOR AND PHASE-LOCKED LOOP - A phase comparator is provided that solves the problem that a VCO cannot be controlled with high precision. A frequency divider frequency-divides a VCO signal applied as input to an input terminal ( | 07-08-2010 |
| 20100176845 | METHOD FOR DETECTING THE LOCKING OF A PHASE-LOCKED LOOP AND ASSOCIATED DEVICE - A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected. | 07-15-2010 |
| 20100182049 | Digital Phase Detection - A method of detecting a phase difference between a circuit output signal and a reference signal is useful in all digital phase locked loops. A plurality of feedback signals are generated from the circuit output signal by means of a process that includes phase interpolation, wherein the feedback signals are spaced apart from one another by a duration of time less than a period of the circuit output signal. At a moment in time, the number of feedback signals that are asserted (logic 1 or in alternative embodiments, logic 0) is counted. The count is indicative of the phase difference between the circuit output signal and the reference signal. | 07-22-2010 |
| 20110050283 | SYNCHRONOUS PHASE DETECTION CIRCUIT - A phase detection circuit arranged as sigma-delta modulator for determining a phase difference between a periodic signal and a reference signal, the periodic signal and the reference signal having a substantially equal frequency, includes: a source input configured to receive the periodic signal whose phase relationship with respect to the reference signal is to be determined; a feedback signal generator configured to provide a feedback signal, the feedback signal and reference signal having substantially the same frequency; a phase difference circuit coupled to the source input node and a second signal input node coupled to the feedback signal generator, and configured to determine an error signal as a function of the phase difference between the periodic signal and the feedback signal; an integrator circuit coupled to the phase difference circuit, configured to receive the error signal and to integrate the error signal to provide an integration signal; a digitizing circuit coupled to the integration circuit, configured to digitize the integration signal; wherein the feedback signal generator is coupled to the digitizing circuit, configured to provide the feedback signal based on the digitized integration signal from the digitizing circuit; and configured to select the phase of the feedback signal from a number of fixed phases, wherein the phase detection circuit is arranged for generating a time-average of the phase of the feedback signal as selected from the plurality of fixed phases. | 03-03-2011 |
| 20110175648 | PHASE-FREQUENCY COMPARATOR AND SERIAL TRANSMISSION DEVICE - Disclosed is a phase-frequency comparator stabilizing a loop band width by a simple circuit, there is provided a phase-frequency comparator which is a phase-frequency comparator of inputting a reference clock and a feedback clock and outputting an up signal to a frequency synthesizer and a down signal to the frequency synthesizer, which is provided with a first phase-frequency comparing circuit, a second phase comparing circuit, and a delay circuit portion inputting the reference clock and the feedback clock and providing a predetermined relative delay to an input of the first phase-frequency comparing circuit and an input of the second phase comparing circuit, in which frequency comparison is carried out by the first phase-frequency comparing circuit, and phase comparison is carried out by the first phase-frequency comparing circuit and the second phase comparing circuit controlling a latch. | 07-21-2011 |
| 20120098570 | PLL DUAL EDGE LOCK DETECTOR - A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal. | 04-26-2012 |
| 20130043907 | Method and system for measuring amplitude and phase difference between two sinusoidal signals - A method and a system for measuring amplitude and phase difference between two sinusoidal signals, using an adaptive filter. The method generally comprises measuring a sample of an output signal of a system excited by a sample of a reference signal; using an adaptive filter and the sample of the reference signal to determine a and b coefficients that minimize a prediction error on the sample of the output signal, iteratively, and determining the amplitude and/or phase of the output of the system using the a and b coefficients. | 02-21-2013 |
| 20130063181 | METHOD AND APPARATUS FOR SIGNAL PHASE CALIBRATION - A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison. | 03-14-2013 |
| 20160191035 | Frequency Comparator and Early-Late Detector - In a receiver facility in an ultra-wideband communication system, a dual-mode circuit adapted to operate in a selected one of three operating modes without changes in circuit topology: a calibration mode adapted to render the circuit substantially independent of circuit component mismatches; a frequency comparator mode adapted to indicate whether the frequency of a first periodic signal is larger or smaller than the frequency of a second periodic signal; and an early-late detector mode adapted to indicate whether the 1 | 06-30-2016 |
| 327008000 | With varying frequency | 1 |
| 20100019802 | Phase/Frequency Detector - PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module. | 01-28-2010 |
| 327009000 | With sampling | 7 |
| 20090184735 | AUTOMATIC PHASE-DETECTION CIRCUIT FOR CLOCKS WITH KNOWN RATIOS - An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared. | 07-23-2009 |
| 20090212824 | Method and Apparatus for Automatic Optimal Sampling Phase Detection - A system for determining an optimal sampling phase is provided. The system includes a plurality of analog to digital converters, each receiving an analog signal and a clock phase signal and generating an output. A clock generator receives a reference clock and generates a plurality of clock phase signals. A sampling phase system receives the plurality of outputs of the analog to digital converters and generates an optimal sampling phase. | 08-27-2009 |
| 20110095786 | PHASE COMPARATOR, PLL CIRCUIT, INFORMATION REPRODUCTION PROCESSING DEVICE, OPTICAL DISK PLAYBACK DEVICE AND MAGNETIC DISK PLAYBACK DEVICE - In a phase comparator used for a sync clock extraction circuit for extracting a clock synchronizing with reproduction data, a zero cross detection section | 04-28-2011 |
| 20120218001 | Techniques for Phase Detection - A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase. | 08-30-2012 |
| 20140139266 | METHOD OF STATIC PHASE OFFSET CORRECTION FOR A LINEAR PHASE DETECTOR - A method for calibrating a clock and data recovery circuit may include configuring a phase detector as a bang-bang phase detector. The bang-bang phase detector may be used to determine a phase difference between a sampling clock provided by an interpolator and a calibration signal. The phase detector may also be configured as a linear phase detector. While using the linear phase detector, a linear phase detector parameter may be adjusted such that the phase difference between the calibration signal and the sampling clock is zero, while keeping the phase of the sampling clock fixed. | 05-22-2014 |
| 20140285238 | PLL CIRCUIT AND PHASE COMPARISON METHOD IN PLL CIRCUIT - A PLL circuit includes a divider configured to generate a divided signal having a cycle of T/M (where M is an integer greater than or equal to two) by dividing an oscillation signal; a phase comparator configured to generate a phase comparison result by calculating an exclusive logical OR of M reference signals and the divided signal, the M reference signals having the cycle of T and respective time intervals shifted sequentially by T/2M; a loop filter configured to generate a voltage signal using the phase comparison result as input; and a voltage-controlled oscillator configured to generate the oscillation signal by oscillating at a frequency depending on the voltage signal. | 09-25-2014 |
| 20150116002 | SEMICONDUCTOR APPARATUS - A method for comparing phases between first and second clock signal includes the first clock signals to a first precharge circuit coupled between a first node and a first terminal to which a first voltage is applied. The first clock signal is supplied to a second precharge circuit coupled between a second node and the first terminal. The second clock signal is supplied to a first discharge circuit coupled between the first node and a second terminal to which a second voltage different from the first voltage is applied. The second clock signal is supplied to a second discharge circuit coupled between the second node and the second terminal. | 04-30-2015 |
| 327010000 | Uniform pulse waveform | 3 |
| 20090045848 | PHASE-FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE - A phase-frequency detection system and method for enhancing performance of the frequency detector in a phase-frequency detection system. Filtering of the frequency detector inputs makes operation of the frequency detector more robust in the presence of intersymbol interference within the incoming data signal and other non-ideal characteristics such as noise and crosstalk. | 02-19-2009 |
| 20120098571 | METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS - Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed. | 04-26-2012 |
| 20140070849 | METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS - Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed | 03-13-2014 |
| 327012000 | With logic or bistable circuit | 27 |
| 20080218216 | Metastable-resistant phase comparing circuit - A phase comparing circuit includes a first storage circuit for reading an external clock signal based on a control clock signal; first and second inverters for inverting a signal from the first storage circuit based respectively on first and second threshold levels; third and fourth inverters for inverting respective signals output from the first and second inverters; a delay circuit for delaying the control clock signal by a specific time; a coincidence control circuit for setting the delayed control clock signal to be active when the signals from the third and fourth inverters coincide with each other, and setting it to be inactive when the signals from the third and fourth inverters do not coincide with each other; and a second storage circuit for reading a signal output form the first storage circuit when the delayed control clock signal is active, and outputting the read signal as the control signal. | 09-11-2008 |
| 20080231324 | PHASE FREQUENCY DETECTOR AND PHASE-LOCKED LOOP - A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay. | 09-25-2008 |
| 20080246516 | Phase Frequency Detectors Generating Minimum Pulse Widths - A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector. | 10-09-2008 |
| 20080297200 | Methods for eliminating phase distortion in signals - A circuit for reducing phase distortion of a first signal and a second signal is provided, wherein the first and the second signals are complementary. The circuit includes a detecting circuit for detecting a first edge of the first signal and a second edge of the second signal, wherein the second edge immediately follows the first edge and is in a same direction as the first edge; an output node; and a signal regenerator connected to the detecting circuit and the output node. The signal regenerator is configured to generate an output signal having an additional first edge and an additional second edge. The additional first edge and the additional second edge are opposite edges substantially aligned to the first edge and the second edge, respectively. The additional first edge and the additional second edge are immediate neighboring edges. | 12-04-2008 |
| 20080309377 | BALANCED PHASE DETECTOR - Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection. | 12-18-2008 |
| 20090058467 | PHASE DETECTION APPARATUS - There is provided a phase detection apparatus that can accurately detect a phase difference between an input signal and a reference signal even when the input signal and the reference signal have different duty cycles. A phase detection apparatus according to an aspect of the invention may include: a pulse generation unit generating a first pulse signal on an edge of an input pulse signal, and a second pulse signal based on an edge of a reference pulse signal having a predetermined phase; and a detection unit detecting a phase difference between the first pulse signal and the second pulse signal from the pulse generation unit. | 03-05-2009 |
| 20090243661 | SYSTEM AND METHOD TO DETECT ORDER AND LINEARITY OF SIGNALS - A method comprises applying a first delay to a first signal that is ahead of a second signal in a series of signals and determining a first number of delay units that provides the first delay to change an order between the delayed first signal and the second signal that has a phase difference with the first signal. The method further comprises determining a similar number for any other pair of signals in the series of signals that have the phase difference. The method further comprises determining a maximum and a minimum from the obtained numbers and determining linearity of the seriels of signals based on a difference between the maximum and the minimum. | 10-01-2009 |
| 20090295433 | METHOD AND APPARATUS FOR MEASURING AND COMPENSATING FOR STATIC PHASE ERROR IN PHASE LOCKED LOOPS - A method and circuit for static phase error measurement includes a reference clock delay chain having a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a reference clock signal. A feedback signal delay chain also has a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a feedback signal. A latch tests phase alignment between the delayed reference clock signal and the delayed feedback signal and outputs a measurement of static phase error. | 12-03-2009 |
| 20100231264 | PASSIVE CLOCK DETECTOR - A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to receive a clock signal and is coupled to a low threshold inverter in the first branch and a high threshold inverter in the second branch. The latch is adapted to receive the clock signal and is coupled to the first branch, while the logic is coupled to the node between the first branch and the latch, an output of the latch, and the second branch so that it can output a clock detection signal. | 09-16-2010 |
| 20110043253 | METHOD FOR SAMPLING DATA AND APPARATUS THEREFOR - A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase. | 02-24-2011 |
| 20110102020 | BALANCED PHASE DETECTOR - Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection. | 05-05-2011 |
| 20110140737 | APPARATUS AND METHOD FOR ESTIMATING DATA RELATING TO A TIME DIFFERENCE AND APPARATUS AND METHOD FOR CALIBRATING A DELAY LINE - An apparatus for estimating data relating to a time difference between two events includes a delay line having a plurality of stages. Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device is provided for summing over the indication signals of the plurality of stages to obtain a sum value. The sum value indicates a time difference estimate. | 06-16-2011 |
| 20110187413 | PHASE DETECTING CIRCUIT AND PLL CIRCUIT - A phase detecting circuit includes a latch circuit that switches, based on an OR signal and an AND signal of two clock signals to be subjected to phase comparison, one of outputs used for generation of two pulse signals on an advance phase side and a delay phase side to a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and holds the output in the states. | 08-04-2011 |
| 20110304357 | DIGITAL PHASE COMPARATOR - A digital phase comparator is provided in which first phase difference signals and second phase difference signals are used as digital phase difference information. The first phase difference signals are generated by sampling a second clock signal with a first group of clock signals having regular intervals. The second phase difference signals are generated, using a second group of clock signals and a first group of signals which are obtained by delaying a second clock signal and a first signal generated by performing a logic operation on the first phase difference signal respectively at different regular intervals, by sampling the second group of clock signals with the first group of signals. | 12-15-2011 |
| 20120133394 | DATA JUDGMENT/PHASE COMPARISON CIRCUIT - The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C GOOD and C BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted. Depending on a relation among data outputs of total three symbols obtained by combining a symbol and symbols previous and subsequent thereto, it is selected that either the Early or the Late is to be outputted by a decision logic EL_LOGIC. | 05-31-2012 |
| 20120139585 | PHASE DETECTING CIRCUIT AND PLL CIRCUIT - A phase detecting circuit includes a latch circuit that switches, based on an OR signal and an NAND signal of two clock signals to be subjected to phase comparison, one of outputs used for generation of two pulse signals on an advance phase side and a delay phase side to a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and holds the output in the states. | 06-07-2012 |
| 20120176158 | TIME-DOMAIN VOLTAGE COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER - A time-domain voltage comparator for an analog-to-digital converter includes a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase comparator configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter. | 07-12-2012 |
| 20120280716 | Fractional-Rate Phase Frequency Detector - A phase frequency detector detects the difference between the edges of a fractional-rate recovered clock signal and the edges within a serial data bit stream, where the edges within the serial data bit stream correspond with the edges of a full-rate clock signal that was used to clock the serial data bit stream. | 11-08-2012 |
| 20130135011 | PHASE FREQUENCY DETECTOR CIRCUIT - A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal. | 05-30-2013 |
| 20130200922 | PHASE FREQUENCY DETECTOR AND CHARGE PUMP FOR PHASE LOCK LOOP FAST-LOCKING - The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques. | 08-08-2013 |
| 20140103961 | PHASE FREQUENCY DETECTOR CIRCUIT - A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal. | 04-17-2014 |
| 20140203842 | PHASE COMPARISON CIRCUIT AND DATA RECEIVING UNIT - A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop. | 07-24-2014 |
| 20140240003 | PHASE LOCK LOOP LOCK INDICATOR - A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one or more phase detectors and to determine from the first up and down outputs and the second up and down outputs how well the phase-locked loop is locked on to a reference clock. | 08-28-2014 |
| 20140340121 | PHASE-DETECTOR CIRCUIT AND CLOCK-DATA RECOVERY CIRCUIT - A phase-detector circuit is disclosed. The phase-detector circuit comprises a plurality of phase comparators which detects a phase difference between receipt data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase. The phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-time difference and a predetermined delay time. | 11-20-2014 |
| 20150008961 | PHASE DETECTOR, PHASE-FREQUENCY DETECTOR, AND DIGITAL PHASE LOCKED LOOP - A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal. | 01-08-2015 |
| 20150070051 | HIGH SPEED PHASE SELECTOR WITH A GLITCHLESS OUTPUT USED IN PHASE LOCKED LOOP APPLICATIONS - A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown. | 03-12-2015 |
| 20160126963 | PHASE DETECTOR AND PHASE-LOCKED LOOP - A phase detector for generating a phase difference signal indicative of a phase difference between a first bi-level signal of frequency F1 and a second bi-level signal of frequency F2 is proposed. The phase detector may include first and second detector inputs first and second flip-flops, a NAND gate, and a first and second overphase detection units. An output of the first overphase detection unit may be connected to a direct input of the second flip-flop and may be arranged to output the level “1” in response to F1≦F2 and the level “0” in response to F1>F2. An output of the second overphase detection unit may be connected to a direct input of the first flip-flop and may be arranged to output the level “1” in response to F2≦F1 and the level “0” in response to F2>F1. | 05-05-2016 |
