| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 324760520 | By phase comparison | 18 |
| 20080211482 | Method and Apparatus for Measuring the Frequency of a Received Signal - A method of measuring the frequency of a received signal comprising the steps of: generating a first phase signal by digitising the phase of the received signal; delaying the first phase signal by a predetermined amount to generate a second phase signal; calculating a phase difference between the first and the second phase signals; and calculating the frequency of the input signal from the phase difference. | 09-04-2008 |
| 20080303508 | Apparatus and Method for Estimating Carrier Frequency Offset in Communication Terminal, and Communication Terminal for Performing the Method - Provided are an apparatus and method for estimating carrier frequency offset in a communication terminal operating in a communication system supporting Orthogonal Frequency Division Multiplexing (OFDM) or Orthogonal Frequency Division Multiplexing Access (OFDMA). More particularly, provided are a method of estimating carrier frequency offset in a communication terminal supporting DownLink (DL) Full Usage of SubChannel (FUSC) and DL Band-Adaptive Modulation and Coding (AMC) channel modes in a wireless communication system based on one of Institute of Electrical and Electronic Engineers (IEEE) 802.16 | 12-11-2008 |
| 20090096439 | BUILT-IN JITTER MEASUREMENT CIRCUIT - A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal. | 04-16-2009 |
| 20100148751 | NOISE MEASUREMENT APPARATUS AND TEST APPARATUS - Provided is a noise measurement apparatus that measures noise at a location under measurement, comprising a self-excited oscillator that is provided at the location under measurement and that outputs an oscillation signal in which is sequentially accumulated, in each cycle, the noise at the location under measurement; a transmission path that transmits the oscillation signal output by the self-excited oscillator; and a measuring unit that measures noise added to the oscillation signal transmitted through the transmission path. The measuring unit may measure the noise at the location under measurement by differentiating noise added to the oscillation signal transmitted through the transmission path. | 06-17-2010 |
| 20100231194 | METHOD AND DEVICE FOR MONITORING PLASMA DISCHARGES - A method and a device (MON) for monitoring plasma-discharges during a surface treatment process are described. In this process electrodes within a gaseous medium are provided with an alternating voltage (U | 09-16-2010 |
| 20110285381 | PHASE TRANSIENT RESPONSE MEASUREMENTS USING AUTOMATIC FREQUENCY ESTIMATION - A method of measuring the phase transient response of a device under test automatically provides a flattened phase transient response without any user intervention. The method comprises the steps of calculating an instantaneous phase waveform based on an instantaneous voltage waveform that represents an output signal of the device under test as it steps from a first frequency to a second frequency, calculating an instantaneous frequency waveform based on the instantaneous phase waveform, automatically estimating the second frequency based on the instantaneous frequency waveform without any user intervention, and flattening the instantaneous phase waveform based on the estimate of the second frequency. | 11-24-2011 |
| 20120274311 | SYSTEM AND METHOD FOR DETECTING A FUNDAMENTAL FREQUENCY OF AN ELECTRIC POWER SYSTEM - A system and method to detect the fundamental frequency of an electric input signal using a feedback control loop including a phase error detector, a loop controller, and a digitally controlled oscillator. The frequency detector may detect the fundamental frequency of an electric input signal and produce an output signal representing the fundamental frequency of the electric input signal. The frequency detector may further include a filter that may be coupled to the frequency detector output signal in order to remove spurious tones or noise from the output signal. | 11-01-2012 |
| 20140125315 | DETERMINING HIGH FREQUENCY OPERATING PARAMETERS IN A PLASMA SYSTEM - Determining a high frequency operating parameter in a plasma system including a plasma power supply device coupled to a plasma load using a hybrid coupler having four ports is accomplished by: generating two high frequency source signals of identical frequency, the signals phase shifted by 90° with respect to one another; generating a high frequency output signal by combining the high frequency source signals in the hybrid coupler; transmitting the high frequency output signal to the plasma load; detecting two or more signals, each signal corresponding to a respective port of the hybrid coupler and related to an amplitude of a high frequency signal present at the respective port; and based on an evaluation of the two or more signals, determining the high frequency operating parameter. | 05-08-2014 |
| 20150054491 | SYSTEM AND METHOD FOR DETECTING A FUNDAMENTAL FREQUENCY OF AN ELECTRIC POWER SYSTEM - A system and method to detect the fundamental frequency of an electric input signal using a feedback control loop including a phase error detector, a loop controller, and a digitally controlled oscillator. The frequency detector may detect the fundamental frequency of an electric input signal and produce an output signal representing the fundamental frequency of the electric input signal. The frequency detector may further include a filter that may be coupled to the frequency detector output signal in order to remove spurious tones or noise from the output signal. | 02-26-2015 |
| 324760530 | With phase lock | 5 |
| 20090102452 | CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT - Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements. | 04-23-2009 |
| 20120200284 | POWER MEASUREMENT DEVICE - A power measurement device for sampling current or voltage signals of a power system to produce a 1-bit delta-sigma bitstream. The power measurement device includes a frequency locked loop for determining the power system frequency directly from the 1-bit delta-sigma bitstream. The frequency locked loop includes a 1-bit rotate CORDIC that is configured to produce difference signals having a multi-bit word for each bit of the 1-bit delta-sigma bitstream, and a phase error calculator that determines the difference between the phase of the power system frequency and a phase ramp generated from a frequency measurement value in a frequency register. The phase error calculator feeds back a phase correction signal to the frequency register to lock the frequency measurement value to the power system frequency. | 08-09-2012 |
| 20120306475 | SYSTEM AND METHOD FOR IMPLEMENTING LOW-COST ELECTRONIC GYROSCOPES AND ACCELEROMETER - Accelerometers have a number of wide-ranging uses, and it is desirable to both increase their accuracy while decreasing size. Here, millimeter or sub-millimeter wavelength accelerometers are provided which has the advantage of having the high accuracy of an optical accelerometer, while being compact. Additionally, because millimeter or sub-millimeter wavelength signals are employed, cumbersome and awkward on-chip optical devices and bulky optical mediums can be avoided. | 12-06-2012 |
| 20140312882 | Anti-Islanding Protection in Three-Phase Converters Using Grid Synchronization Small-Signal Stability - A small signal feedback loop or feed-forward loop having gain provides substantially unconditional instability in a phase locked loop when a reference phase signal is lost. The small signal feedback or feed-forward also modifies phase locked loop bandwidth when the reference phase signal is lost to increase rapidity of response to loss of reference phase signal while maintaining insensitivity to reference voltage amplitude change while the reference phase signal is present. The performance thus achieved is particularly suitable for rapid condition detection response and control of a grid connected power converter under islanding conditions. | 10-23-2014 |
| 20160084891 | ISLANDING DETECTION APPARATUS FOR PARALLEL DISTRIBUTED GENERATION SYSTEM - An islanding detection apparatus minimizes a reduction in power quality and detects islanding when distributed generations are operated in parallel. Also, another islanding detection apparatus for parallel distributed generations synchronizes parallel distributed generations by periodically applying a reactive current at a half cycle. Further, another islanding detection apparatus for parallel distributed generations easily synchronizes parallel distributed generations even when inverters installed in the respective distributed generations are fabricated through different makers. | 03-24-2016 |
| 324760540 | With delay line | 2 |
| 20080246461 | Methods and Apparatus for Testing Delay Locked Loops and Clock Skew - According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip. | 10-09-2008 |
| 20090051347 | HIGH FREQUENCY DELAY CIRCUIT AND TEST APPARATUS - A high frequency delay circuit operable to output a high frequency signal delayed for a desired delay time. The high frequency delay circuit includes: a variable delay circuit operable to receive a reference signal of which a frequency is lower than the high frequency signal, and to output a delay reference signal delayed from the reference signal for the desired delay time in advance; and a multiplier operable to generate the high frequency signal, of which a frequency is a frequency of the delay reference signal multiplied by a predetermined value, and to output the generated high frequency signal at timing according to a phase of the delay reference signal. | 02-26-2009 |
| 324760550 | Digital output | 1 |
| 324760570 | With tone detection | 1 |
| 20130229170 | TONE DETECTOR - A tone detector is disclosed that is realizable in digital embodiment on a single integrated circuit die and does not require external components, such as a discrete capacitor. An input connects to a comparator, which in turn connects to one or more edge detectors and a flip flop. The edge detector outputs a pulse responsive to a detected edge. A counter is reset by the pulses from the edge detectors thereby preventing the counter from reaching a maximum value, which would otherwise be output from the counter and provided to a flip flop to clock in the comparator output at the D input to the flip flop. In operation, the comparator generates a rail to rail signal responsive to a received tone, which in turn is clocked through the flip flop as a logic high output indicating presence of a tone. | 09-05-2013 |
| 324760710 | Nulling circuit | 1 |
| 20130300400 | SYNCHRONOUS RECTIFICATION CIRCUIT AND ASSOCIATED ZERO-CROSSING DETECTION METHOD - The embodiments of the present invention disclose a synchronous rectification circuit and associated zero-crossing detection method. The synchronous rectification circuit includes a synchronous rectifier having a source, a drain, and at least two gates. The synchronous rectifier having N MOS cells connected in parallel, wherein N is an integer greater than or equal to 2. Through comparing a voltage signal across the drain and the source of the synchronous rectifier with a first and a second threshold voltage, part of the N MOS cells is turned off once the voltage signal is equal to the first threshold voltage, and the left part of the N MOS cells is turned off once the voltage signal is equal to the second threshold voltage. Thus, the accuracy of zero-crossing detection is improved. | 11-14-2013 |
