Class / Patent application number | Description | Number of patent applications / Date published |
257780000 | Ball or nail head type contact, lead, or bond | 26 |
20080197510 | Semiconductor device and wire bonding method - A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion. | 08-21-2008 |
20080224326 | Chip structure with bumps and testing pads - A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad. | 09-18-2008 |
20080296780 | MEMORY DEVICES INCLUDING SEPARATING INSULATING STRUCTURES ON WIRES AND METHODS OF FORMING - Wires included in integrated circuit devices can have separate insulating structures formed thereon. The separate insulating structures on the wires can surround respective cross sectional portions of the wires, which can function as “stand-offs” to prevent immediately neighboring wires (or other neighboring components) from shorting together to thereby allow a reduction in defects associated with devices having reduced pitch between the wires (or other components). | 12-04-2008 |
20090001608 | Semiconductor device and wire bonding method - After bonding a wire to a pad on a surface of a semiconductor chip, a capillary is moved toward a lead and toward a direction opposite to the lead as the wire is fed out, and a first kink that is convex in a direction opposite to the lead, a second kink that is convex toward the lead, and a straight portion that continues from the second kink are formed in the wire. Then, the capillary is moved to form a loop and bonds the wire to the lead. During this bonding, the straight portion is formed into a linear portion in a direction along the surface of the lead, and the linear portion is pressed to the surface of the lead. | 01-01-2009 |
20090115074 | Method of Processing a Contact Pad, Method of Manufacturing a Contact Pad, and Integrated Circuit Element - In a method of processing a contact pad, a passivation layer stack including at least one passivation layer is formed on at least an upper surface of a contact pad region. A first portion of the passivation layer stack is removed from above the contact pad region, wherein a second portion of the passivation layer remains on the contact pad region and covers the contact pad region. An adhesion layer is formed on the passivation layer stack. The adhesion layer is patterned, wherein the adhesion layer is removed from above the contact pad region. Furthermore, the second portion of the passivation layer stack is removed. | 05-07-2009 |
20090294994 | BOND PAD STRUCTURE - A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit structure. The passivation layer covers the bond pad and has an opening, and the opening exposes a part of the bond pad. The part of the topmost metal layer located under the opening serves as a supporting layer. The supporting layer has at least a slot, and the topmost metal layer is electrically connected to the bond pad through a plurality of via plugs. | 12-03-2009 |
20090302485 | LAMINATE SUBSTRATE AND SEMICONDUCTOR PACKAGE UTILIZING THE SUBSTRATE - A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching. | 12-10-2009 |
20100213619 | BONDING STRUCTURE OF BONDING WIRE AND METHOD FOR FORMING SAME - Provided is a bonding structure of a bonding wire and a method for forming the same which can solve problems of conventional technologies in practical application of a multilayer copper wire, improve the formability and bonding characteristic of a ball portion, improve the bonding strength of wedge connection, and have a superior industrial productivity. A bonding wire mainly composed of copper, and a concentrated layer where the concentration of a conductive metal other than copper is high is formed at a ball bonded portion. The concentrated layer is formed in the vicinity of the ball bonded portion or at the interface thereof. An area where the concentration of the conductive metal is 0.05 to 20 mol % has a thickness greater than or equal to 0.1 μm, and it is preferable that the concentration of the conductive metal in the concentrated layer should be five times as much as the average concentration of the conductive metal at the ball bonded portion other than the concentrated layer. | 08-26-2010 |
20100225008 | WIRE BOND INTERCONNECTION - A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal. | 09-09-2010 |
20120139129 | WIRE BONDING METHOD AND SEMICONDUCTOR DEVICE - After forming a pressure-bonded ball and a ball neck by bonding an initial ball to a pad, a capillary is moved upward, away from a lead, and then downward, thereby the ball neck is trodden on by a face portion that is on the lead side of the capillary. Subsequently, the capillary is moved upward and then toward the lead until the face portion of the capillary is positioned above the ball neck, thereby a wire is folded back toward the lead. Then, the capillary is moved downward such that a side of the wire is pressed by the capillary against the ball neck that has been trodden on. After the capillary is moved obliquely upward toward the lead and then looped toward the lead, the wire is pressure-bonded to the lead. | 06-07-2012 |
20130026657 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a dielectric layer having opposite first and second surfaces; a semiconductor chip disposed on the first surface; at least two conductive pads embedded in and exposed from the first surface of the dielectric layer, and electrically connected to the semiconductor chip; a plurality of ball-implanting pads formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer, each of the conductive pillars having a first end electrically connected to one of the ball-implanting pads and a second end opposing the first end and electrically connected to one of the conductive pads. Through the installation of the conductive pillars, it is not necessary for the ball-implanting pads to be associated with the conductive pads in position, and the semiconductor package thus has an adjustable ball-implanting area. | 01-31-2013 |
20130241083 | Joint Structure for Substrates and Methods of Forming - Disclosed embodiments include wire joints and methods of forming wire joints that can enable realization of fine pitch joints and collapse control for various packages. A first embodiment is a structure comprising a first substrate, a second substrate, and a wire joint. The first substrate comprises a first bonding surface, and the second substrate comprises a second bonding surface. The first bonding surface is opposite and faces the second bonding surface. The wire joint is attached to and between the first bonding surface and the second bonding surface. | 09-19-2013 |
20130285263 | SENSOR ARRAY PACKAGE - A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board. | 10-31-2013 |
20130292856 | METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES - The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. | 11-07-2013 |
20150035172 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To enhance the reliability of a semiconductor device. The semiconductor device includes a wiring substrate having a plurality of bonding fingers (terminal) formed on a chip-mounting surface, a semiconductor chip mounted on the wiring substrate, a plurality of wires having a ball part and a stitch part respectively. The bonding fingers have a first bonding finger to which the stitch part of the first wire is coupled respectively, and the second bonding finger to which a ball part of the second wire is coupled. In addition, in plan view, the second bonding finger is arranged at a position different from the arrangement of a plurality of first bonding fingers, and the width of the second bonding finger is larger than the width of the first bonding finger. | 02-05-2015 |
20150137390 | ALUMINUM COATED COPPER RIBBON - A ribbon, preferably a bonding ribbon for bonding in microelectronics, contains a first layer containing copper, a coating layer containing aluminum superimposed over the first layer, and an intermediate layer. In a cross-sectional view of the ribbon, the area share of the first layer is from 50 to 96% and the aspect ratio between the width and the height of the ribbon in a cross-sectional view is from 0.03 to less than 0.8. The ribbon has a cross-sectional area of 25,000 μm | 05-21-2015 |
20150145148 | Copper Ball Bond Interface Structure and Formation - An integrated circuit copper wire bond connection is provided having a copper ball ( | 05-28-2015 |
20150303169 | SYSTEMS AND METHODS FOR MULTIPLE BALL BOND STRUCTURES - A method for forming a semiconductor device includes forming a first ball bond on a first contact pad, in which the first ball bond has a first wire segment of a bonding wire extending from the ball bond; forming a mid-span ball in the first wire segment at a first distance from the ball bond; and after the forming the mid-span ball, attaching the mid-span ball to a second contact pad to form a second ball bond. | 10-22-2015 |
257781000 | Layered contact, lead or bond | 8 |
20080211112 | Carbon Nanotube Bond Pad Structure and Method Therefor - A bond pad structure ( | 09-04-2008 |
20080237893 | Anti Pad To Reduce Parasitic Capacitance And Improve Return Loss In A Semiconductor Die And Package - An apparatus for minimizing parasitic capacitance on a semiconductor die includes a semiconductor die having a least one signal line and at least one plane and an anti pad located between the at least one signal line and the at least one plane. | 10-02-2008 |
20090108471 | Wiring board of semiconductor device, semiconductor device, electronic apparatus, mother board, method of manufacturing wiring board of semiconductor device, method of manufacturing mother board and method of manufacturing electronic apparatus - In a wiring board of a semiconductor device according to the present invention, a land | 04-30-2009 |
20090283920 | BALL-BUMP BONDED RIBBON-WIRE INTERCONNECT - A ball-bump bonded ribbon-wire interconnect has a ball-bump attached to an integrated circuit's bond pad. A ribbon-wire has one end attached to the ball-bump and its opposing end attached to a substrate's metallized surface. The ribbon-wire may be wider than the ball-bump, and the ball-bump may separate the ribbon-wire from the integrated circuit's surface. The ribbon-wire may interconnect multiple integrated circuits, each of which has a ball-bump or a suitably wide metallized surface, to a substrate's metallized surface. The present invention also includes a method of electrically connecting an electronic component to a substrate. | 11-19-2009 |
20100038803 | LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE - The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed. | 02-18-2010 |
20100072632 | BOND PAD STRUCTURE HAVING DUMMY PLUGS AND/OR PATTERNS FORMED THEREAROUND - A semiconductor structure is provided. In one embodiment, a bond pad is formed above one or more underlying layers of a substrate. A plurality of dummy plugs are spaced around the bond pad, the plurality of dummy plugs substantially vertically traversing the one or more underlying layers, wherein the plurality of dummy plugs anchor at least two of the underlying layers together to achieve improved mechanical strength. | 03-25-2010 |
20100109167 | CONDUCTIVE PATHS FOR TRANSMITTING AN ELECTRICAL SIGNAL THROUGH AN ELECTRICAL CONNECTOR - The claimed invention relates to structures suitable for improving the performance and reliability of electrical connectors. One embodiment of the claimed invention includes an integrated circuit die having an electrical contact coupled with electrically conductive paths that share a common electrical source. The conductive paths are configured to transmit the same electrical signal to the electrical contact, which supports an electrical connector, such as a solder bump. The electrical connector couples the die with an outside component, such as a circuit board. Each of the conductive paths connect to the electrical contact at different interface locations. When the electrical signal passes through the interface locations, the paths are configured to have non-zero current densities at those locations. The electrical resistance of the conductive paths may be substantially similar. Thus, instead of being concentrated at a single point, current is more evenly distributed along the junction between the die and solder bump, which may reduce voiding and localized heating. | 05-06-2010 |
20120326336 | BOND PAD DESIGN FOR IMPROVED ROUTING AND REDUCED PACKAGE STRESS - A bond pad design comprises a plurality of bond pads on a semiconductor chip and a plurality of under-bump metallurgy (UBM) layers formed on respective bond pads of the plurality. At least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center to the periphery of the chip. | 12-27-2012 |