Class / Patent application number | Description | Number of patent applications / Date published |
257779000 | Solder wettable contact, lead, or bond | 51 |
20080230926 | Surface Treatments for Contact Pads Used in Semiconductor Chip Packagages and Methods of Providing Such Surface Treatments - An inorganic solder mask ( | 09-25-2008 |
20080251945 | Semiconductor package that has electronic component and its fabrication method - A semiconductor device having at least an electronic component and its fabrication method are disclosed. The fabrication method comprises: applying a conductive material on each one of at least a paired solder pads arranged on a substrate by screen printing, with a recess formed in the conductive material on each one of the at least a paired solder pads, so as to expose a portion of each one of the at least a paired solder pads, wherein the recesses on the at least a paired solder pads are formed in position corresponding to each other; and mounting at least an electronic component having two opposing conductive terminals on the at least a paired solder pads, in a manner that the two opposing conductive terminals are introduced into the corresponding recesses of the conductive material so as for the electronic component to be electrically connected to the at least a paired solder pads via the conductive material by reflow. The recesses of the conductive material are capable of effectively securing the electronic component in position. Furthermore, both terminals of the electronic component are not formed with conductive material underneath so as to prevent the electronic components from tilting in level resulted from the uniform applying of the conductive material. | 10-16-2008 |
20080290528 | SEMICONDUCTOR PACKAGE SUBSTRATE HAVING ELECTRICAL CONNECTING PADS - A semiconductor package substrate having electrical connecting pads includes: a substrate body having a plurality of electrical connecting pads formed on surface thereof, and a plurality of protruding lumps or concave areas of any geometric shape respectively formed on surfaces of the electrical connecting pads for increasing contact surfaces of the electrical connecting pads, thereby preventing detaching of conductive elements from surfaces of the electrical connecting pads caused by poor bonding force. | 11-27-2008 |
20090001607 | Electronic Device Comprising an esd Device - The electronic device comprises an ESD device ( | 01-01-2009 |
20090014898 | SOLDER CAP APPLICATION PROCESS ON COPPER BUMP USING SOLDER POWDER FILM - A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad. | 01-15-2009 |
20090014899 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING STACKED DIE - An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to expose a portion of the solder bump. The wafer is singulated into individual die structures at the groove. | 01-15-2009 |
20090134529 | CIRCUIT BOARD MODULE, ELECTRIC DEVICE, AND METHOD FOR PRODUCING CIRCUIT BOARD MODULE - A circuit board module includes: a printed wiring board that is provided with a plurality of solder bonding pads; a semiconductor package that is provided with a plurality of solder bonding portions on a back face thereof to be mounted on the printed wiring board by soldering the solder bonding portions onto the respective solder bonding pads on the printed wiring board; a plurality of reinforcement pads that are provided on the printed wiring board at positions along peripheral edges of the semiconductor package, each of the reinforcement pads having a solder coated layer formed thereon; and a plurality of reinforcing adhesive agents that are disposed on each of the reinforcement pads to adhere the semiconductor package to the reinforcement pads. | 05-28-2009 |
20090179333 | SOLDER CONTACTS AND METHODS OF FORMING SAME - An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material. | 07-16-2009 |
20090212444 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including a substrate, a circuit pattern, a chip, at least one conductive material and an adhesive is provided. The substrate has a first surface, a second surface opposite thereto, and at least one through hole which penetrates the first surface and the second surface. The circuit pattern structure is disposed on the second surface and has at least one connecting pad disposed at the through hole. The chip is disposed on the first surface of the substrate. The chip has at least one conductive post, wherein the conductive post and the conductive material are disposed inside the through hole, and the conductive post is electrically connected with the pattern circuit structure through the conductive material. The adhesive is disposed between the chip and the substrate. A manufacturing method of the semiconductor structure is also provided. | 08-27-2009 |
20090261481 | WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost. | 10-22-2009 |
20090278264 | Semiconductor Chip Bump Connection Apparatus and Method - Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad. | 11-12-2009 |
20090294993 | Packaging substrate structure - A packaging substrate structure is disclosed, which comprises a dielectric material with Young's Modulus less than 1 Gpa and moisture absorption ratio less than 1.0% in a solder mask, an outer dielectric layer or the combination. The package substrate structure improves the stability and the integration of the product. | 12-03-2009 |
20090321962 | MICROELECTRONIC PACKAGE WITH SELF-HEATING INTERCONNECT - A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate. | 12-31-2009 |
20100032848 | BOND PAD STRUCTURE AND METHOD FOR PRODUCING SAME - It is described a bond pad structure and a method for producing the same, the bond pad structure ( | 02-11-2010 |
20100044884 | INTEGRATED CIRCUIT PACKAGE EMPLOYING PREDETERMINED THREE-DIMENSIONAL SOLDER PAD SURFACE AND METHOD FOR MAKING SAME - An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described. | 02-25-2010 |
20100072631 | CONNECTION BY FITTING TOGETHER TWO SOLDERED INSERTS - A connection device between two components includes a hollow conductive insert, into which is fitted another conductive insert, the electrical connection between the two inserts being provided by means of a solder element. | 03-25-2010 |
20100127408 | BONDING PAD STRUCTURE FOR BACK ILLUMINATED OPTOELECTRONIC DEVICE AND FABRICATING METHOD THEREOF - A bonding pad structure for an optoelectronic device. The bonding pad structure comprises a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same. | 05-27-2010 |
20100181687 | SEMICONDUCTOR DEVICE INCLUDING SINGLE CIRCUIT ELEMENT - A semiconductor device includes a chip. The chip includes a single circuit element formed in a semiconductor substrate, a first metal layer on a first face of the semiconductor substrate, and a second metal layer on a second face of the semiconductor substrate opposite the first face. The first metal layer and the second metal layer are configured for accessing the single circuit element. A smaller of a first width of the first face of the semiconductor substrate and a second width of the first face of the semiconductor substrate perpendicular to the first width is less than or equal to a distance between an exposed face of the first metal layer parallel to the first face of the semiconductor substrate and an exposed face of the second metal layer parallel to the second face of the semiconductor substrate. | 07-22-2010 |
20100201002 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING SAME - Provided is a semiconductor device including: a base plate; a thermally conductive resin layer formed on an upper surface of the base plate; an integrated layer which is formed on an upper surface of the thermally conductive resin layer, and includes an electrode and an insulating resin layer covering all side surfaces of the electrode; and a semiconductor element formed on an upper surface of the electrode, in which the integrated layer is thermocompression bonded to the base plate through the thermally conductive resin layer. This semiconductor device excels in insulating properties and reliability. | 08-12-2010 |
20100252939 | CHIP MODULE AND METHOD FOR PRODUCING A CHIP MODULE - A chip module having a substrate and at least one chip connected to the substrate is provided, the substrate featuring a first main plane of extension and the chip featuring a second main plane of extension, and an acute angle being provided between the first main plane of extension and the second main plane of extension, and the substrate also comprising a mold housing. | 10-07-2010 |
20100289157 | CIRCUIT BOARD HAVING BYPASS PAD - An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided. | 11-18-2010 |
20110042831 | Layered Chip For Use In Soldering - A layer assemblage for a semiconductor chip having a chip body for producing a soldering connection for the chip. The assemblage is provided on a side of a chip body formed from a semiconducting material, wherein the layer assemblage is formed from a plurality of sequential metal layers which follow one above another and are produced by means of a physical coating method, and wherein a solderable soldering layer is provided between a noble metal layer situated at a surface of the layer assemblage and the chip body. In order to avoid an undesired penetration of a solder through the layer assemblage the soldering layer has at least one internal interface formed by an interruption of the coating method. | 02-24-2011 |
20110049729 | METHOD FOR PRODUCING A HERMETICALLY SEALED, ELECTRICAL FEEDTHROUGH USING EXOTHERMIC NANOFILM - A method generates at least one electrical connection from at least one electronic component, which is positioned on a substrate inside an encapsulation, to outside the encapsulation. The functional capability of the electrical connection is to be provided at ambient temperatures greater than 140° C. and in the event of large power losses and extreme environmental influences. A reactive nanofilm, having targeted reaction, which can be triggered exothermically by laser, is used to produce hermetically sealed electrical connections. Using the nanofilm, an output of an electrical connection and a contact of the electrical connection to at least one further electrical contact can be provided. | 03-03-2011 |
20110057329 | ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - It is desired to provide an electronic device which can be easily taken out of a mold after resin sealing processing. The electronic device includes: an insulating layer; a wiring layer formed on a surface of the insulating layer; a first solder resist formed to cover the insulating layer and the wiring layer and including a particle of a first elastomer; and a second solder resist formed to cover a surface of the first solder resist. A surface of the second solder resist has smaller adhesive strength than the surface of the second solder resist at a glass transition point of the first elastomer. | 03-10-2011 |
20110057330 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - It is desired to provide an electronic device which can be easily taken out of a mold after a resin sealing processing. The electronic device include: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed to cover the insulation layer and the wiring and including particles of an elastomer. An asperity is formed on a surface of the solder resist layer. | 03-10-2011 |
20110108996 | JOINT STRUCTURE, JOINING MATERIAL AND METHOD FOR PRODUCING JOINING MATERIAL - The present invention provides a semiconductor component having a joint structure including a semiconductor device, an electrode disposed opposite the semiconductor device, and a joining material which contains Bi as main component and connects the semiconductor device to the electrode. Since the joining material contains a carbon compound, joint failure due to the difference in linear expansion coefficient between the semiconductor device and the electrode can be reduced compared with conventional materials. The joining material which contains Bi as main component enables provision of a joint structure in which a semiconductor device and an electrode are joined by a joint more reliable than a conventional joint. | 05-12-2011 |
20110127680 | SPACER, AND ITS MANUFACTURING METHOD - Provided are a spacer capable of avoiding a poor connection due to the suction of solder when the clearance width between a soldered semiconductor device and a printed circuit board is made constant, and a manufacturing method for the spacer. The spacer includes an electrically insulating base member, and at least one solder guiding terminal. The base member has a bottom face, a top face and at least one side face, of which the bottom face and the top face are out of contact with each other whereas the side face contacts one or both the bottom face and the top face. The solder guiding terminal covers the bottom face partially, the top face partially, and the side face partially or wholly. A solder guiding face as the surface of a portion of the solder guiding terminal covering the side face is not normal to the bottom face. | 06-02-2011 |
20110215483 | Flux-free chip to substrate joint serial linear thermal processor arrangement - A linear, serial chip/substrate assembly processing machine for stepwise advancing a pre-assembled chip/die substrate on a support plate through a series of sealable chambers beginning at a loading station and ending up at an unloading station after various melting and vacuuming of chip/substrate components has been stepwise indexed through those various chambers to the final joining thereof. | 09-08-2011 |
20110221075 | METHOD OF MANUFACTURING ELECTRONIC DEVICE AND ELECTRONIC DEVICE - Provided is a method of manufacturing an electronic device comprising a first electronic component having a first terminal and a second electronic component having a second terminal, wherein said first electric component is electrically connected to said second electronic component by connecting said first terminal to said second terminal with solder, | 09-15-2011 |
20110233793 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a preliminary solder layer made of a Sn alloy is formed on a connecting pad of a wiring substrate. A solder bump made of a Sn alloy is formed on an electrode pad of a semiconductor chip. After contacting the preliminary solder layer and the solder bump, the preliminary solder layer and the solder bump are melted by heating to a temperature of their melting points or higher to form a solder connecting part made of a Sn alloy containing Ag and Cu. Only the preliminary solder layer of the preliminary solder layer and the solder bump is composed of a Sn alloy containing Ag. | 09-29-2011 |
20110260339 | SEMICONDUCTOR DEVICE - A semiconductor device includes a supporting board having a protection film thereon; a semiconductor chip provided on the supporting board; a first internal connecting terminal formed on the supporting board; a second internal connecting terminal formed on the semiconductor chip; a first insulation layer for covering an upper surface of the supporting board and upper and lateral surfaces of the semiconductor chip; a wiring pattern provided on the first insulation layer, the wiring pattern connecting the first and second internal connecting terminals; a solder resist layer provided on the first insulation layer and the wiring pattern, the solder resist layer having an opening part; an external connecting terminal provided so as to connect to the wiring pattern through the opening part; a groove part formed on outer peripheries of the supporting board, the protection film, and the first insulation layer; and a resin layer formed in the groove part. | 10-27-2011 |
20110285033 | Chip Carrier - Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location. | 11-24-2011 |
20120286433 | Robust FEBOL and UBM Structure of C4 Interconnects - An electrical conductor is connected to a first microcircuit element having a first connector site axis and a second microcircuit having a second connector site axis. The first microcircuit and the second microcircuit are separated by and operatively associated with a first electrical insulator layer. The conductor and the first microcircuit element are separated by and operatively associated with a second electrical insulator layer. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric material. The microcircuit includes a UBM and solder connection to a FBEOL via opening. Sufficiently separating the first connector site axis and the second connector site axis so they are not concentric, decouples the UBM and solder connection to the FBEOL via opening. This eliminates or minimizes electromigration and the white bump problems. A process comprises manufacturing the microcircuit. | 11-15-2012 |
20120299202 | MOUNTING STRUCTURE OF SEMICONDUCTOR PACKAGE COMPONENT AND MANUFACTURING METHOD THEREFOR - A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity η | 11-29-2012 |
20130069250 | DIE SUBSTRATE WITH REINFORCEMENT STRUCTURE - Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate. | 03-21-2013 |
20130200532 | Semiconductor Device Using Diffusion Soldering - A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip. | 08-08-2013 |
20130277863 | SOLDERABLE PAD FABRICATION FOR MICROELECTRONIC COMPONENTS - Two microelectronic components can be attached by flowing solder between solderable pads patterned on interfacing surfaces. According to one implementation, the microelectronic components can include the solderable pads patterned onto first respective surfaces and other surface features patterned onto second respective surfaces. In another implementation, the solderable pads can include an adhesion layer, a diffusion barrier layer, and surface oxidation layer. | 10-24-2013 |
20140091481 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die. | 04-03-2014 |
20140183759 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member. | 07-03-2014 |
20140210110 | ATTACHMENT OF MICROELECTRONIC COMPONENTS - Sub-micron precision alignment between two microelectronic components can be achieved by applying energy to incite an exothermic reaction in alternating thin film reactive layers between the two microelectronic components. Such a reaction rapidly distributes localized heat to melt a solder layer and form a joint without significant shifting of components. | 07-31-2014 |
20140312512 | Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer - A semiconductor device has a substrate with a plurality of contact pads. A first insulation layer is formed over the substrate and contact pads. A portion of the first insulating layer is removed to form a toroid-shaped SRO over the contact pads while retaining a central portion of the first insulating layer over the contact pads. The central portion of the first insulating layer can extend above a surface of the first insulating layer outside the first conductive layer. A first conductive layer is formed over the central portion of the first insulating layer and through the SRO in the first insulating layer over the contact pads. The first conductive layer may extend above a surface of the first insulating layer outside the second conductive layer. A semiconductor die is mounted to the substrate with the bumps electrically connected to the first conductive layer. | 10-23-2014 |
20140339709 | HIGH POWER DIELECTRIC CARRIER WITH ACCURATE DIE ATTACH LAYER - A system for bonding a die to a high power dielectric carrier such as a ceramic dielectric core with double-sided conductive layers is described. In the system, the upper conductive layer has a first area whose surface has a first wettability. A second area that at least partially surrounds the first area has a surface with a second wettability that is greater than the first wettability. During bonding, an adhesive material bonding a chip to the substrate spreads among the first area by a downward force placed on the chip. Due to the difference in wettability, the adhesive material then spreads among the second area by a wetting force generated by the greater second wettability of the second area surface causing the chip to be drawn down until reaching a predetermined position. The predetermined position can be determined by substrate protrusions or substrate cavities. | 11-20-2014 |
20150035171 | Segmented Bond Pads and Methods of Fabrication Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments. | 02-05-2015 |
20150061158 | JOINING A CHIP TO A SUBSTRATE WITH TWO OR MORE DIFFERENT SOLDER ALLOYS - A method including forming a first solder bump on a chip, the first solder bump made of a first alloy, and forming a second solder bump on a chip, the second solder bump made of a second alloy, where the first alloy has a different alloy concentration and is different from the second alloy. | 03-05-2015 |
20150076712 | ELECTRONIC DEVICE WITH BIMETALLIC INTERFACE ELEMENT FOR WIRE BONDING - An electronic device includes a chip with an integrated electronic component and a terminal made of a first metal material. The device further includes a lead made of a second metal material different from the first metal material. A bonding wire made of a selected one of the first and second metal materials has opposite ends coupled with the terminal and the lead. An interface element having a first layer made of a selected one of the first and second metal materials and a second layer made of an unselected one of the first and second metal materials has the first layer coupled with the bonding wire and the second layer coupled with a component, wherein the component is ether the terminal or the lead. | 03-19-2015 |
20150084211 | Package Assembly and Methods for Forming the Same - A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector. | 03-26-2015 |
20150097300 | JUNCTION AND ELECTRICAL CONNECTION - A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor. | 04-09-2015 |
20150130084 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A fan-out package structure including a heat radiating side edge that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a redistribution layer connected with the bond pad and located on the semiconductor substrate, wherein an end of the redistribution layer extends to a sidewall of the semiconductor substrate, and the end is coplanar with the sidewall. | 05-14-2015 |
20160005703 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An element electrode is located on a surface of a semiconductor element. A metal film is located on the element electrode and includes an inner region and an outer region located around the inner region. The metal film has an opening that exposes the element electrode between the inner region and the outer region. The element electrode has solder wettability lower than solder wettability of the metal film. An external electrode is solder-bonded to the inner region of the metal film. | 01-07-2016 |
20160064341 | MICROELECTRONIC PACKAGES HAVING TEXTURIZED SOLDER PADS AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions. | 03-03-2016 |
20160093564 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - An apparatus for a manufacturing semiconductor device including a plate member and a joint member. The apparatus includes a plate-type tool having the plate member mounted thereon, a first fixing tool and a second fixing tool having an inclined surface for abutting an upper edge of an end part in a width direction of plate member. The second fixing tool is fixed onto the plate-type tool adjacent to the end part. An ultrasonic horn applies ultrasonic vibration in the width direction of plate member while pressing the joint member toward the plate member. | 03-31-2016 |