| Entries |
| Document | Title | Date |
|---|
| 20080197508 | PLATED PILLAR PACKAGE FORMATION - A method involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package. | 08-21-2008 |
| 20080211106 | VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF - A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer. | 09-04-2008 |
| 20080211107 | Via hole structure and manufacturing method thereof - A via hole structure and a manufacturing method thereof are provided. The via hole structure is disposed on a substrate. The substrate has a through hole, which passes through the substrate from a top surface to a bottom surface. The via hole structure comprises a conductive layer, several first conductive lines and several second conductive lines. The conductive layer having several conductive sections is disposed on the inner wall of the through hole. The first conductive lines are adjacent to the top surface for connecting the top ends of the conductive sections. The second conductive lines are adjacent to the bottom surface for connecting the bottom ends of the conductive sections. The conductive sections, the first conductive lines and the second conductive lines are serially connected to form a three-dimension layout. | 09-04-2008 |
| 20080211108 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 09-04-2008 |
| 20080211109 | SEMICONDUCTOR DEVICE AND METHOD OF VISUAL INSPECTION AND APPARATUS FOR VISUAL INSPECTION - A semiconductor device having the structure, which is adopted for the highly precise visual inspection with a lower cost, is achieved. A semiconductor device is a semiconductor device having a region for forming an electric circuit, and includes seal rings provided in an interconnect layer and surrounding the region for forming an electric circuit, and a dummy metal via provided in the interconnect layer and located outside of the seal rings. In a cross section perpendicular to an elongating direction of the seal ring, the width of the dummy metal via is smaller than the width of the seal ring. | 09-04-2008 |
| 20080217788 | METHOD OF FABRICATING SELF-ALIGNED CONTACT - A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region thereon. Next, a lower opening corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper opening self-aligned to and communicated with the lower opening is formed in the second dielectric layer, wherein the upper opening and the lower opening constitute a self-aligned contact opening. Afterwards, the self-aligned contact opening is filled with a conductive layer. | 09-11-2008 |
| 20080217789 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL LINE OF SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced. | 09-11-2008 |
| 20080217790 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a vertical conductive structure which includes a first inter-layer insulating film; a second inter-layer insulating film formed on the first inter-layer insulating film; a lower-layer contact plug which passes through the first inter-layer insulating film and the second inter-layer insulating film, wherein in the lower-layer contact plug, the outer diameter of the upper surface is smaller than the outer diameter at the boundary position between the first inter-layer insulating film and the second inter-layer insulating film; a third inter-layer insulating film formed on the second inter-layer insulating film; and an upper-layer contact plug which passes through the third inter-layer insulating film on the lower-layer contact plug, and is electrically connected to the lower-layer contact plug. Typically, a wiring line, which is insulated from the lower-layer contact plug and the upper-layer contact plug, is formed between the second inter-layer insulating film and the third inter-layer insulating film. | 09-11-2008 |
| 20080217791 | SEMICONDUCTOR DEVICE - In a semiconductor device of the present invention, an electrode pad is formed on a surface of a semiconductor substrate, and in the electrode pad, two different areas: a connection area of through wiring electrically connected to a through wiring; and a pad area for inspection that keeps away from an opening on the surface of a through hole, are set. Accordingly, the electrode pad can be adequately prevented from being damaged due to contact of a probe, providing a high yield and reliability of the semiconductor device. That is, because the through hole is not opened directly below the pad area for inspection with which the probe is in contact upon operation inspection of devices, a mechanical strength of the electrode pad against the probe can be maintained in a high level. | 09-11-2008 |
| 20080230917 | METHOD OF FABRICATING TWO-STEP SELF-ALIGNED CONTACT - A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper hole self-aligned to and communicated with the lower hole is formed in the second dielectric layer, wherein the upper hole and the lower hole constitute a self-aligned contact hole. Afterwards, the self-aligned contact hole is filled with a conductive layer. | 09-25-2008 |
| 20080230918 | SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD OF SIGNAL TERMINALS ON INPUT/OUTPUT CELL - A semiconductor integrated circuit, including an input/output cell including signal terminals, wherein the signal terminal of the input/output cell is connected to an internal circuit via an interconnect wiring. The signal terminal of the I/O cell includes a plurality of (e.g., four) conductive layers. Each pair of adjacent ones of the plurality of conductive layers are connected together by a via. One of the plurality of conductive layers to which a via of the largest diameter is connected (e.g., the fourth conductive layer) is formed with a width such that only one of the largest-diameter via can be accommodated. Therefore, it is possible to suppress the migration of atoms from the interconnect wiring to the input terminal of the I/O cell, and to suppress the open failure of the via formed on the interconnect wiring. | 09-25-2008 |
| 20080230919 | Dual damascene with via liner - A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in the first dielectric insulator; lining the opening with a second dielectric; forming a second dielectric insulator over the first dielectric insulator; forming a second opening in the second dielectric insulator overlying and communicating with the first opening; and, filling the first and second openings with a conductive material to electrically communicate with the conductive area. | 09-25-2008 |
| 20080237879 | SEMICONDUCTOR DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND DUAL BUILD-UP LAYERS OVER BOTH SIDE-SURFACES FOR WLP AND METHOD OF THE SAME - A structure of a semiconductor device package having a substrate with a die receiving through hole, a connecting through hole structure and a contact pad. A die is disposed within the die receiving through hole. A surrounding material is formed under the die and filled in the gap between the die and the sidewall of the die receiving though hole. Dielectric layers are formed on the both side surface of the die and the substrate. Re-distribution layers (RDL) are formed on the dielectric layers and coupled to the contact pads. Protection layers are formed over the RDLs. | 10-02-2008 |
| 20080237880 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTECTED CONDUCTIVE LAYERS - An integrated circuit package system is provided including providing an integrated circuit die having a contact pad, forming a protection cover over the contact pad, forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover, developing a conductive layer over the passivation layer, and forming a pad opening in the protection cover for exposing the contact pad. | 10-02-2008 |
| 20080237881 | RECESSED SOLDER SOCKET IN A SEMICONDUCTOR SUBSTRATE - Electronic devices and their formation are described. In one embodiment, a device includes a plurality of stacked semiconductor substrates. The device includes a first semiconductor substrate having a recess extending into a first surface thereof and a via extending from the recess to a second surface opposite the first surface of the first semiconductor substrate. The device also includes a solder positioned in the recess of the first semiconductor substrate. The device also includes an electrically conducting material in the via and electrically coupled to the solder positioned in the recess of the first semiconductor substrate. The device also includes a second semiconductor substrate having bonding pad extending therefrom, the bonding pad electrically coupled to the solder. The device is configured so that at least a portion of the second substrate bonding pad extends a distance into the recess in the first substrate. Other embodiments are described and claimed. | 10-02-2008 |
| 20080237882 | Annular via drilling (AVD) technology - In some embodiments, annular via drilling (AVD) technology is presented. In this regard, an annular via is introduced comprising an inner wall and an outer wall, the inner wall and the outer wall coupled with a dielectric layer and extending linearly from a surface of a conductor to a top of the dielectric layer. Other embodiments are also disclosed and claimed. | 10-02-2008 |
| 20080237883 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - First semiconductor element | 10-02-2008 |
| 20080237884 | Packaging substrate structure - A packaging substrate structure is disclosed, which at least comprises a build-up structure including a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is disposed between the first dielectric layer and the third dielectric layer. The characteristic is that the Young's modulus of the second dielectric layer is lower then the first dielectric layer and the third dielectric layer so as to form a sandwich structure of high-low-high of Young's modulus. The packaging substrate structure of the present invention can improve the quality of the product. | 10-02-2008 |
| 20080237885 | Method for Improving Design Window - A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks. | 10-02-2008 |
| 20080246161 | Damascene conductive line for contacting an underlying memory element - A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element. | 10-09-2008 |
| 20080251931 | MULTI CAP LAYER AND MANUFACTURING METHOD THEREOF - A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performing an etching process to etch the multi cap layer through the patterned hard mask layer and to form an opening in the second cap layer. | 10-16-2008 |
| 20080251932 | Method of forming through-silicon vias with stress buffer collars and resulting devices - A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed. | 10-16-2008 |
| 20080258308 | Method of controlled low-k via etch for Cu interconnections - An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer. | 10-23-2008 |
| 20080258309 | Three-dimensional semiconductor device - A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device. | 10-23-2008 |
| 20080258310 | Semiconductor device having a tapered plug - A semiconductor device includes: first and second interlayer dielectric films consecutively deposited to overlie a silicon substrate; contact plugs penetrating the first interlayer dielectric film and having a top surface located within the second interlayer dielectric film; and via-plugs having a first portion, the diameter of which reduces from the top of the second interlevel dielectric film toward the bottom thereof and a second portion extending between the first portion and the first plug, the second portion having a diameter increasing from the first portion to the first plug. | 10-23-2008 |
| 20080265428 | VIA AND SOLDER BALL SHAPES TO MAXIMIZE CHIP OR SILICON CARRIER STRENGTH RELATIVE TO THERMAL OR BENDING LOAD ZERO POINT - A method of modifying via and solder ball shapes for maximizing semiconductor chip or silicon carrier strengths relative to thermal expansion and bending load zero points. The method entails modifying circular annular vias into elliptical annular vias so as to reduce stress concentration factors in the chip or carrier at the vias and solder balls. The reduction in the stress concentration is effected in the semiconductor chip or silicon carrier in regions proximate the vias and in wiring layers at the ends of the vias. | 10-30-2008 |
| 20080265429 | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - An electronic component is provided with a first conductor, an insulator for covering a surface of the first conductor, a via hole penetrating the insulator, and a second conductor located on a surface of the insulator and electrically connected to the first conductor through the via hole, and includes a shielding film having conductivity, being interposed between the first conductor and the second conductor, and covering an interface between the first conductor and the insulator in the via hole by extending continuously at least from the surface of the first conductor constituting a bottom surface of the via hole to an inner wall surface of the via hole. | 10-30-2008 |
| 20080272496 | PLANAR INTERCONNECT STRUCTURE FOR HYBRID CIRCUITS - Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces for electrically connecting sets of interconnection points of each of the hybrid circuits. | 11-06-2008 |
| 20080272497 | METHODS OF FORMING CONDUCTIVE VIAS THROUGH SUBSTRATES, AND STRUCTURES AND ASSEMBLIES RESULTING THEREFROM - Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods are also disclosed. | 11-06-2008 |
| 20080272498 | Method of fabricating a semiconductor device - A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap. | 11-06-2008 |
| 20080272499 | Through-wafer vias - A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within the metal layer in the circuit portion, the metal is removably distributed such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region. | 11-06-2008 |
| 20080277799 | LOW TEMPERATURE METHODS OF FORMING BACK SIDE REDISTRIBUTION LAYERS IN ASSOCIATION WITH THROUGH WAFER INTERCONNECTS, SEMICONDUCTOR DEVICES INCLUDING SAME, AND ASSEMBLIES - Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to forming the RDLs, after forming the RDLs, or substantially simultaneously to forming the RDLs. The material for the back side RDLs and various other associated materials, such as dielectrics and conductive via filler materials, are processed at temperatures sufficiently low so as to not damage the semiconductor devices or associated components contained on the active surface of the semiconductor substrate. The low temperature processed back side RDLs of the present invention may be employed with optically interactive semiconductor devices and semiconductor memory devices, among many others. Semiconductor devices employing the RDLs of the present invention may be stacked and electrically connected theretogether. | 11-13-2008 |
| 20080284037 | Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration. | 11-20-2008 |
| 20080284038 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE - An integrated circuit package system is provided including forming a perimeter paddle having a first external interconnect extending therefrom, mounting an integrated circuit die over the perimeter paddle, connecting a second external interconnect and the integrated circuit die, and encapsulating the integrated circuit die and the perimeter paddle with the first external interconnect exposed. | 11-20-2008 |
| 20080284039 | INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES - A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level. | 11-20-2008 |
| 20080284040 | Semiconductor device and method of manufacturing same - A semiconductor device in a packaged form including a semiconductor includes a semiconductor substrate with an active component disposed thereon and pads disposed on a surface thereof and connected to the active component, a first interconnection disposed on the semiconductor substrate and connected to the pads, a first insulating layer disposed on the semiconductor substrate in covering relation to the first interconnection and having an opening reaching a portion of the first interconnection, and a second interconnection disposed in the opening and on the first insulating layer and connected to the first interconnection. | 11-20-2008 |
| 20080284041 | SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIA AND RELATED METHOD OF FABRICATION - In a semiconductor package, an electrode has a first part extending through a semiconductor substrate and a second part extending from the first part through a compositional layer to reach a conductive pad. | 11-20-2008 |
| 20080290525 | SILICON-ON-INSULATOR STRUCTURES FOR THROUGH VIA IN SILICON CARRIERS - A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride lo separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material. | 11-27-2008 |
| 20080290526 | Test patterns for detecting misalignment of through-wafer vias - A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top surface of the through-wafer via are substantially coplanar. The through-wafer via is at least adjacent to the plurality of conductive patterns. The semiconductor chip further includes a plurality of bonding pads on a surface of the semiconductor chip, each being connected to one of the plurality of conductive patterns. | 11-27-2008 |
| 20080290527 | METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES - Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. | 11-27-2008 |
| 20080296778 | Interconnection Structure and Integrated Circuit - A method of manufacturing an integrated circuit and an interconnection structure includes forming a conductive portion along a first direction and conductive lines along a second direction. | 12-04-2008 |
| 20080303169 | Integrated Circuit Arrangment Including Vias Having Two Sections, and Method For Producing the Same - An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via. | 12-11-2008 |
| 20080303170 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device | 12-11-2008 |
| 20080303171 | Semiconductor device and a fabrication process thereof - A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film. | 12-11-2008 |
| 20080308944 | Method for eliminating duo loading effect using a via plug - Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug. | 12-18-2008 |
| 20080308945 | Semiconductor Integrated Circuit - A semiconductor integrated circuit according to an example of the present invention includes a first interconnect extending in a first direction, a second interconnect arranged over the first interconnect and extending in a second direction intersecting the first direction, a first via for connecting a first contact part of the first interconnect and a second contact part of the second interconnect, and a second via for connecting a third contact part of the first interconnect and a fourth contact part of the second interconnect. The first and third contact parts are arranged by being aligned in the first direction, and the second and fourth contact parts are arranged by being aligned in the second direction. | 12-18-2008 |
| 20080315430 | NANOWIRE VIAS - A method of fabricating an integrated circuit including arranging a nanowire with a first end portion thereof at a first contact surface of a first electrical contact and with a second end portion sticking up from the first contact surface, and embedding at least part of the nanowire in dielectric material. | 12-25-2008 |
| 20080315431 | Mounting substrate and manufacturing method thereof - A mounting substrate and a method of manufacturing the mounting substrate. The mounting substrate can include an insulation layer, a bonding pad buried in one side of the insulation layer in correspondence with a mounting position of a chip, and a circuit pattern electrically connected to the bonding pad. By utilizing certain embodiments of the invention, the process for stacking a solder resist layer can be omitted, as the bonding pads can be implemented in a form recessed from the surface of the insulation layer. In this way, the manufacturing process can be simplified and manufacturing costs can be reduced. Since the surface of the mounting-substrate on which to mount a chip can be kept flat without any protuberances, the occurrence of voids in the underfill can be minimized. This is correlated to obtaining a high degree of reliability, and leads to a greater likelihood of successful mounting. | 12-25-2008 |
| 20090008789 | Method of manufacturing micro tunnel-junction circuit and micro tunnel-junction circuit - A method of manufacturing a micro tunnel-junction circuit capable of remarkably relieving the limitation of a circuit pattern to be manufactured and remarkably relieving the limitation of a metallic material to be used. In the method, a three-layer structure is formed by laminating a first metal, an insulator, and a second metal on a substrate in this order, a narrow wall part is formed by cutting the three-layer structure in the depth direction by using a converging ion beam, at least one laterally passed through-hole is formed in the wall part by using the converging ion beam, and at least one recessed portion positioned adjacent to the hole is formed by cutting the upper surface of the wall part in the depth direction. The hole is a through-hole starting at the position of the head of the second metal to the position of the head of the substrate and the recessed part is formed to be recessed from the upper surface of the wall part into the first metal. | 01-08-2009 |
| 20090008790 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole. | 01-08-2009 |
| 20090008791 | Circuit Structure with Low Dielectric Constant Regions - A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects. | 01-08-2009 |
| 20090008792 | Three-dimensional chip-stack package and active component on a substrate - The 3D chip-stack package comprises a component-embedded plate and a side IC. The PCB has a plurality of conductive contacts. The component-embedded plate comprises a dielectric layer; an active component embedded in the dielectric layer, one surface of each active component exposed outside the dielectric layer, the active components having a plurality of TSVs (Through Silicon Via), one ends of the TSVs exposed outside the exposed surface, the other ends of the TSVs corresponding to the conductive contacts of the PCB; and an electrical circuit on the dielectric layer and in electrical connection between the other ends of the TSVs of the active component and the corresponding conductive contacts of the PCB, respectively. The side IC has a plurality of pads. The pads are electrically connected with the exposed ends of the TSVs of the active component. | 01-08-2009 |
| 20090014885 | Four-Terminal Reconfigurable Devices - Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided. The reconfigurable device comprises a substrate, a first dielectric layer on the substrate; a conductive layer recessed into at least a portion of a side of the first dielectric layer opposite the substrate; at least one second dielectric layer over the side of the first dielectric layer opposite the substrate, so as to cover the conductive layer; a heater within the second dielectric layer; at least one programmable via extending through the second dielectric layer, extending through and surrounded by the heater and in contact with the conductive layer the programmable via comprising at least one phase change material; a capping layer over the programmable via; a first conductive via and a second conductive via, each extending through the second dielectric layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive layer. | 01-15-2009 |
| 20090014886 | DYNAMIC RANDOM ACCESS MEMORY WITH AN ELECTROSTATIC DISCHARGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin. | 01-15-2009 |
| 20090014887 | METHOD OF PRODUCING MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE - In an insulating film structure having a barrier insulating film, a via interlayer insulating film, a wiring interlayer insulating film, and a hard mask film stacked in this order on an underlayer wiring, a via hole pattern is formed in the insulating film structure, then a groove pattern is formed in the hard mask film, and a grove is formed in the insulating film structure using this as a mask. According to the prior art, the via side wall is oxidized equally severely in the both processes. The trench side wall is oxidized severely in the via first process according to the prior art, whereas, according to the present invention, the oxidation thereof is suppressed to such an extent that an almost non-oxidized state can be created. | 01-15-2009 |
| 20090014888 | SEMICONDUCTOR CHIP, METHOD OF FABRICATING THE SAME AND STACK PACKAGE HAVING THE SAME - A semiconductor chip may include a wafer, a semiconductor device formed on the wafer, a first dielectric layer formed on the wafer and the semiconductor device, a first metal interconnection formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and the lower interconnection, and a third dielectric layer formed on the second dielectric layer. A second metal interconnection may be formed in the third dielectric layer, a first nitride layer formed on the third dielectric layer and the first metal interconnection, a via hole extending through the wafer, the first dielectric layer, the second dielectric layer, the third dielectric layer and the first nitride layer, a via formed in the via hole and a third metal interconnection formed on the first oxide layer, an exposed upper end of the via and the second metal interconnection. | 01-15-2009 |
| 20090020883 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a first contact plug arranged above a semiconductor substrate and using aluminum (Al) as a material; a second contact plug arranged on and in contact with the first contact plug and using a refractory metal material; a first dielectric film arranged on a flank side of the first and second contact plugs; a wire arranged above the second contact plug and using copper (Cu) as a material; a second dielectric film arranged on a flank side of the wire; and a barrier film arranged at least between the wire and the first dielectric film and between the wire and the second dielectric film. | 01-22-2009 |
| 20090020884 | SURFACE TREATMENT METHOD, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - Provided are methods of surface treatment, semiconductor devices and methods of forming the semiconductor device. The methods of forming the semiconductor device include forming a first oxide layer and a second oxide layer on a substrate. The first and second oxide layers are patterned to form a contact hole exposing the substrate. A sidewall of the first oxide layer exposed by the contact hole reacts with HF to form a first reaction layer and a sidewall of the second oxide layer exposed by the contact hole reacts with NH | 01-22-2009 |
| 20090026627 | Support Structures for On-Wafer Testing of Wafer-Level Packages and Multiple Wafer Stacked Structures - A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged. | 01-29-2009 |
| 20090032963 | SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS AND METHODS TO FORM SAME - Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines. | 02-05-2009 |
| 20090032964 | System and method for providing semiconductor device features using a protective layer - Present embodiments relate to systems and methods for providing semiconductor device features using a protective layer during coating operations. One embodiment includes a method comprising providing a substrate with a hole formed partially therethrough, the hole comprising an opening in a first side of the substrate. Additionally, the method comprises disposing a protective layer over the first side of the substrate, removing a portion of the protective layer over at least a portion of the opening to provide access to the hole, and filling at least a portion of the hole with a fill material. | 02-05-2009 |
| 20090032965 | Seminconductor device having P-N column portion - A semiconductor device includes: a first semiconductor layer; a p-n column portion over the first semiconductor layer and including second and third semiconductor layers, which are alternately arranged; and a peripheral portion adjacently to the p-n column portion and including a fourth semiconductor layer. An end second semiconductor layer has an impurity amount equal to or larger than a half of other second semiconductor layers. The third semiconductor layers include a large impurity amount portion adjacent to the end second semiconductor layer. The large impurity amount portion includes at least one third semiconductor layer having an impurity amount larger than an impurity amount of other third semiconductor layers. | 02-05-2009 |
| 20090032966 | Method of fabricating a 3-D device and device made thereby - A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern. | 02-05-2009 |
| 20090039522 | BIPOLAR AND CMOS INTEGRATION WITH REDUCED CONTACT HEIGHT - Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer. | 02-12-2009 |
| 20090045521 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an interlayer insulation film; a lower interconnection layer; an upper interconnection layer; and a via hole extending through the interlayer insulation film to establish electric connection between the lower and upper interconnections; wherein a plurality of interconnection lines is provided in the lower interconnection layer, and a contact region is formed for contact with the via hole by partially joining at least two interconnection lines, and a void exists in a first region of the interlayer insulation film located between adjacent interconnection lines, and no void exists in a second region of the interlayer insulation film located between a contacting portion of the via hole in the contact region and an interconnection line adjacent to the contact region, whereby reliably preventing any contact between a via hole and a void formed in an interlayer insulation film even when the via hole is greatly displaced. | 02-19-2009 |
| 20090045522 | SEMICONDUCTOR DEVICE HAVING VIA CONNECTING BETWEEN INTERCONNECTS - A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via. | 02-19-2009 |
| 20090051039 | THROUGH-SUBSTRATE VIA FOR SEMICONDUCTOR DEVICE - A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the plurality of interconnect layers to the back surface of the substrate. In one embodiment, a insulating layer is formed on the substrate and includes an opening, and wherein the opening includes conductive material providing contact to the tapered profile via. | 02-26-2009 |
| 20090051040 | POWER LAYOUT OF INTEGRATED CIRCUITS AND DESIGNING METHOD THEREOF - The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of metal rings, which are formed by arranging denser layout of the metal trunks with uniform line width. The power ring serves as a function of receiving and providing a power source to the elements of the integrated circuit. | 02-26-2009 |
| 20090051041 | MULTILAYER WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND SUBSTRATE FOR USE IN IC INSPECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - A multilayer wiring substrate includes one or more resin dielectric layers ( | 02-26-2009 |
| 20090057912 | PARTITIONED THROUGH-LAYER VIA AND ASSOCIATED SYSTEMS AND METHODS - Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole. | 03-05-2009 |
| 20090057913 | Packaging substrate structure with electronic components embedded therein and method for fabricating the same - A packaging substrate structure with electronic components embedded therein and a method for fabricating the same are disclosed. The packaging substrate structure comprises a core board with a wiring layer on the two opposite surfaces thereof; a first built-up structure disposed on at least one surface of the core board and having a cavity to expose the surface of the core board; an electronic component disposed in the cavity and having an active surface and an inactive surface, where the active surface has pluralities of electrode pads and the inactive surface faces the surface of the core board; and a solder mask disposed on the surfaces of the first built-up structure and the electronic component, where the solder mask has pluralities of first openings to expose the electrode pads of the electronic component. Accordingly, the packaging substrate disclosed by the present invention can efficiently enhance electrical performance and product reliability. | 03-05-2009 |
| 20090065947 | Semiconductor device having circularly connected plural pads via through holes and method of evaluating the same - A semiconductor device includes a plurality of wiring layers, a plurality of via layers, and a plurality of electrode pads. The electrode pads are circularly connected to each other through the wiring layers and the via layers. | 03-12-2009 |
| 20090072409 | Interconnect Structures Incorporating Air-Gap Spacers - A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. | 03-19-2009 |
| 20090072410 | MICROELECTRONIC CIRCUIT STRUCTURE WITH LAYERED LOW DIELECTRIC CONSTANT REGIONS - The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes. | 03-19-2009 |
| 20090085217 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a semiconductor chip formed on the carrier, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip. | 04-02-2009 |
| 20090085218 | FLASH MEMORY DEVICE AND FABRICATING METHOD THEREOF - A flash memory device may include a first insulating layer on a base insulating layer on a substrate, a lower wire layer that fills a trench in the first insulating layer, a first insulating interlayer and a second insulating layer stacked in sequence on the first insulating layer and the lower wire layer, a middle wire layer that fills a trench in the second insulating layer, and a second insulating interlayer and an upper wire layer stacked in sequence on the middle wire layer, wherein the lower wire layer. The middle wire layer and the upper wire layer may be electrically connected to each other and the first insulating layer may include a low-k layer in contact with the base insulating layer. In addition, each of the first insulating interlayer, the second insulating layer, and the second insulating interlayer may include an FSG layer. | 04-02-2009 |
| 20090096109 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first insulation film formed over a semiconductor substrate; and a plurality of first interconnects selectively formed in the first insulation film. A plurality of gaps are formed in part of the first insulation film located between adjacent ones of the first interconnects so that each of the gaps has a cylindrical shape extending vertically to a principal surface of the semiconductor substrate. A cap film is formed of metal or a material containing metal in upper part of each of the first interconnects. | 04-16-2009 |
| 20090102058 | METHOD FOR FORMING A PLUG STRUCTURE AND RELATED PLUG STRUCTURE THEREOF - A method for forming a plug structure by utilizing a punching through process and the related plug structure are provided. An opening is defined in a substrate, and an unwanted oxide residue is disposed on a bottom of the opening. A glue layer is subsequently formed over the substrate. Portions of the glue layer are disposed on the sidewall and bottom of the opening, and cover the oxide. Thereafter, the portion of the first glue layer disposed at the bottom of the opening is punched through until the substrate is exposed so as to remove the oxide. Next, the opening is filled with a conductive structure. | 04-23-2009 |
| 20090102059 | SEMICONDUCTOR DEVICE - Increase in the chip size of a semiconductor device is suppressed. The semiconductor device includes: circuit vias provided in an interlayer insulating film between upper and lower wiring layers and coupling these wiring layers together; a planar ring-shaped protecting via that is provided in the interlayer insulating film under an electrode pad and one side of which is coupled with the electrode pad; a protecting wiring layer comprised of a wiring layer coupled only with the other side of the protecting via; and a semiconductor element provided over the principal surface of a semiconductor substrate under the protecting wiring layer. The lower part of the electrode pad whose surface is exposed is encircled with the protecting via and the protecting wiring layer. The width of the protecting via is equal to or larger than the width of each circuit via. | 04-23-2009 |
| 20090108460 | DEVICE INCLUDING A SEMICONDUCTOR CHIP HAVING A PLURALITY OF ELECTRODES - A device, including a semiconductor chip having a plurality of first electrodes is disclosed. A plurality of second electrodes is arranged on a first surface of the semiconductor chip. A first electrically conductive layer is applied over a first section of the first surface and electrically coupled to the first electrodes arranged within the first section. A second electrically conductive layer is applied over the first electrically conductive layer and electrically coupled to the second electrodes arranged within the first section. | 04-30-2009 |
| 20090108461 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes providing a semiconductor substrate including a first landing plug and a second landing plug. A bit line is formed over the semiconductor substrate. The bit line is electrically coupled to the first landing plug. A stacked structure of an etch stop film and an interlayer insulating film is deposited over the semiconductor substrate including the bit line. The stacked structure is selectively etched using a contact mask to form a contact hole having an upper part that is wider than a lower part of the contact hole. The contact hole exposes the second landing plug. A contact plug is formed over the contact hole. The contact plug is electrically coupled to the second landing plug. | 04-30-2009 |
| 20090108462 | DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS - By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density. | 04-30-2009 |
| 20090108463 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a wiring layer over a substrate, forming a first film over the wiring layer, forming a second film over the first film, selectively etching the first and second films to form an first end of the first and second films over the wiring layer, forming a third film over the second film, selectively etching the third film to form a second end of the third film tapered off over the first end of the first and second films, forming an interlayer insulating film over the second and third films, forming a contact hole by selectively etching the interlayer insulating film, the first film, the second film and the third film, and forming a contact plug connected to the wiring layer in the contact holes. | 04-30-2009 |
| 20090108464 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first insulating layer including a first contact pad made of conductive polysilicon and a second insulating layer including a second contact pad are formed over a semiconductor silicon layer. After this, a via hole for a through-hole electrode is formed until the via hole penetrates through at least the semiconductor silicon layer and the first contact pad and reaches to the second contact pad. | 04-30-2009 |
| 20090108465 | CERAMIC SUBSTRATE GRID STRUCTURE FOR THE CREATION OF VIRTUAL COAX ARRANGEMENT - Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines. | 04-30-2009 |
| 20090115067 | MODULE HAVING BUILT-IN ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING SUCH MODULE - An electronic component embedded module that can improve reliability of electric connection of inner vias, and a manufacturing method therefor are provided. A first electronic component ( | 05-07-2009 |
| 20090115068 | Semiconductor Device and Method of Manufacturing the Same - Provided are a semiconductor device and a method of manufacturing the same. In the method, a metal interconnection can be formed on a substrate. A dielectric can be formed on the metal interconnection. A photoresist pattern can be formed on the dielectric. The dielectric can be etched using the photoresist pattern as an etch mask to form a dense region of contact holes exposing the metal interconnection and dummy patterns surrounding the region of contact holes. In the semiconductor device, the dummy patterns are disposed around the dense contact holes to minimize a difference between etching rates of the contact holes, thereby inhibiting an etching defect such as an under-etch or over-etch defect. | 05-07-2009 |
| 20090127714 | CONTACT PLUG OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The present invention relates to a contact plug of a semiconductor device and a method of forming the same. The method includes forming an insulating layer over a semiconductor substrate, forming contact holes in the insulating layer, forming a first conductive layer over the insulating layer including the contact holes, etching the first conductive layer so that the first conductive layer remains at lower portions of the contact holes, wherein the insulating layer is also etched in order to widen upper widths of the contact holes, and forming a second conductive layer over the first conductive layer of the contact holes, thus forming the contact plugs. | 05-21-2009 |
| 20090134525 | Semiconductor device having a filling pattern around a storage structure and method of forming the same - A semiconductor device includes an interlayer insulating layer on a semiconductor substrate, at least one plug on the semiconductor substrate, the plug extending through the interlayer insulating layer toward an upper portion of the semiconductor substrate, the plug having a lower part with a first diameter and an upper part with a second diameter different from the first diameter, a filling pattern on the interlayer insulating layer, the filling pattern surrounding the upper part of the plug, and an upper surface of the filling pattern being substantially coplanar with an upper surface of the plug, the upper surface of the plug facing away from the semiconductor substrate, and a protection pattern on the upper part of the plug, the protection pattern being between the plug, the filling pattern, and the interlayer insulating layer. | 05-28-2009 |
| 20090134526 | Interconnect Structure to Reduce Stress Induced Voiding Effect - An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via. | 05-28-2009 |
| 20090140435 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF PROTOTYPING A SEMICONDUCTOR CHIP - In a semiconductor integrated circuit device comprising a semiconductor chip having a number of conductor layers and a number of via layers between the conductor layers, a routing matrix is provided in a small area of the chip to act as a revision number register. The routing matrix includes a matrix block having, in each metal layer of the chip, conductor tracks, the tracks in each metal layer running in a respective direction different from the direction of the tracks in the adjacent metal layers so that the tracks of each consecutive pair of metal layers cross over each other. In each via layer between consecutive metal layers, the matrix block includes selectively placed vias interconnecting the tracks in the adjacent metal layers on each side of the respective via layer. The tracks in each metal layer comprise source tracks and output tracks, the source tracks being coupled respectively to logic level sources of opposite polarity and the output tracks providing register outputs which carry a high or low logic level depending on their individual connections in the routing matrix block to the supply lines. The arrangement is such that when a change in the primary circuits of the chip is required, a new revision number output can be generated by altering the interconnections of the conductor tracks of the routing matrix only in the respective metal layer or via layer which has been changed in the primary circuits. | 06-04-2009 |
| 20090140436 | METHOD FOR FORMING A VIA IN A SUBSTRATE AND SUBSTRATE WITH A VIA - The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method for forming a via in a substrate includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the second surface of the substrate to expose the first conductive metal, the center insulating material and the first insulating material. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even. | 06-04-2009 |
| 20090146312 | METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC WORKPIECES AND MICROELECTRONIC WORKPIECES FORMED USING SUCH METHODS - Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The individual dies include integrated circuitry and a terminal electrically coupled to the integrated circuitry. The method can include forming a first opening in the substrate from a back side of the substrate toward a front side and in alignment with the terminal. The first opening has a generally annular cross-sectional profile and separates an island of substrate material from the substrate. The method can also include depositing an insulating material into at least a portion of the first opening, and then removing the island of substrate material to form a second opening aligned with at least a portion of the terminal. In several embodiments, the method may include constructing an electrically conductive interconnect in at least a portion of the second opening and in electrical contact with the terminal. | 06-11-2009 |
| 20090146313 | SEMICONDUCTOR DEVICE - In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML | 06-11-2009 |
| 20090152734 | Super-Self-Aligned Contacts and Method for Making the Same - A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact. | 06-18-2009 |
| 20090152735 | Metal Interconnection and Method for Manufacturing the Same in a Semiconductor Device - Provided is a method for manufacturing a metal interconnection in a semiconductor device. The semiconductor device fabricated according to one embodiment comprises a copper interconnection having reduced sheet and contact resistance. In the method for manufacturing the copper interconnection, a dielectric comprising a via hole is formed on a semiconductor substrate. A diffusion barrier is deposited in the via hole of the dielectric using a process including a plasma enhanced atomic layer deposition (PEALD) process. A copper metal layer can be formed on the via hole through an electroplating process. | 06-18-2009 |
| 20090152736 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming an insulating film above a semiconductor substrate, forming a concave portion in the insulating film, forming a precursor film including a predetermined metallic element on a surface of the insulating film, carrying out a heat treatment on the precursor film and the insulating film to react with each other, thereby forming an insulative barrier film mainly comprising a compound of the predetermined metallic element and a constituent element of the insulating film in a self-aligned manner at a boundary surface between the precursor film and the insulating film, removing an unreacted part of the precursor film after forming the barrier film, forming a conductive film comprising at least one of Ru and Co on the barrier film, depositing a wiring material film on the conductive film, and forming a wiring from the wiring material film to provide a wiring structure. | 06-18-2009 |
| 20090152737 | MEMORY DEVICES HAVING CONTACT FEATURES - Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching. | 06-18-2009 |
| 20090160064 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an interlayer insulating film on a semiconductor substrate, and then forming a first via hole in the interlayer insulating film, and then forming a resin material in the first via hole, and then forming a plurality of second via holes in the interlayer insulating film laterally, and then forming a resin material in the second via holes, and then simultaneously forming a plurality of third via holes in the interlayer insulating film and a trench spatially above and corresponding to the first via hole, and then removing the resin formed in the first via hole and the second via holes, and then simultaneously forming metal layers in the first via hole and the second and third via holes and the trench. | 06-25-2009 |
| 20090166881 | AIR-GAP ILD WITH UNLANDED VIAS - A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer. | 07-02-2009 |
| 20090166882 | METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE - A method for forming a metal line in a semiconductor device includes patterning a part of a first interlayer insulating film over a semiconductor substrate to form a contact hole therein, depositing a first metal in the contact hole to form a metal contact plug, forming a second interlayer insulating film over a semiconductor substrate where the metal contact plug is formed, etching the second interlayer insulating film to form a trench, removing residual gases from the formation of the metal contact plug after the formation of the trench, and depositing a second metal in the trench to form a metal film connected to the metal contact plug. Accordingly, it is possible to avoid the etching of the contact plug by removing the residual gases such as carbon and fluorine, after the formation of a trench. | 07-02-2009 |
| 20090166883 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING IMPROVED POWER SUPPLY WIRING - In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration). | 07-02-2009 |
| 20090166884 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole's upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer. | 07-02-2009 |
| 20090174080 | SEMICONDUCTOR DEVICE - In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves ( | 07-09-2009 |
| 20090189289 | EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC SUBSTRATES - A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer disc is disposed between two layers of resin. The constrainer discs may be made of copper. The constrainer disc may be circular or square-shaped. Preferably there is a dielectric gap between the constrainer disc and the via. | 07-30-2009 |
| 20090189290 | CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES - A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias. | 07-30-2009 |
| 20090194886 | PASS THROUGH VIA TECHNOLOGY FOR USE DURING TEH MANUFACTURE OF A SEMICONDUCTOR DEVICE - Via structures are described which pass through a semiconductor substrate assembly such as a semiconductor die or wafer and allows for two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer, while the other connection electrically connects to a conductive pad. To connect to a pad, a larger opening is etched into an overlying dielectric layer, while to pass through a pad without connection, a narrower opening is etched into the overlying dielectric layer. | 08-06-2009 |
| 20090200682 | VIA IN VIA CIRCUIT BOARD STRUCTURE - Methods, systems, and apparatuses for electrical connections through circuit boards are described. A via-in-via structure in a circuit board provides two electrical signal paths. The circuit board includes a dielectric layer having opposing first and second planar surfaces. A first opening extends through the dielectric layer. An electrically conductive coating coats a surface of the dielectric layer in the first opening. An electrically insulating material substantially fills the first opening. The circuit board includes a first additional dielectric layer attached to the first planar surface, and a second additional dielectric layer attached to the second planar surface. A second opening extends through the first additional dielectric layer, the electrically insulating material filling the first opening, and the second additional dielectric layer. An electrically conductive material coats a surface of the first additional dielectric layer, the electrically insulating material, and the second additional dielectric layer in the second opening. | 08-13-2009 |
| 20090200683 | INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME - An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias by depositing an interlayer dielectric layer onto a substrate, depositing at least one hardmask onto the interlayer dielectric layer, lithographically forming a via pattern with elongated via features and lithographically forming a line pattern in either order, then either transferring the line patterns first into the interlayer dielectric layer forming line features or transferring the via pattern first into the interlayer dielectric layer as long as the patterns overlap to forming self aligned via features, depositing conducting metals and filling regions corresponding to the line and via features, and planarizing and removing excess metal from the line and via features. | 08-13-2009 |
| 20090206488 | THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER - A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer. | 08-20-2009 |
| 20090206489 | DUAL DAMASCENE METAL INTERCONNECT STRUCTURE HAVING A SELF-ALIGNED VIA - A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line. | 08-20-2009 |
| 20090206490 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAE - A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%. | 08-20-2009 |
| 20090206491 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region. | 08-20-2009 |
| 20090212441 | Semiconductor Interconnect Structure with Stacked Vias Separated by Signal Line and Method Therefor - A semiconductor device is made by forming a first conductive layer over a substrate, forming a first passivation layer over the first conductive layer, forming a first via in the first passivation layer to expose the first conductive layer, forming a second conductive layer over the first passivation layer and within the first via to electrically connect to the first conductive layer, forming a second passivation layer over the second conductive layer, and forming a second via in the second passivation layer to expose the second conductive layer. The second via is smaller than the first via. The second via is either physically separate from or disposed over the first via. The second conductive layer within the second via has a flat surface which is wider than the second via. An under bump metallization is formed in the second via and electrically connected to the second conductive layer. | 08-27-2009 |
| 20090218699 | METAL INTERCONNECTS IN A DIELECTRIC MATERIAL - A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material. | 09-03-2009 |
| 20090230561 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active area having a source and a gate. A gate metal contact is deposited above and forms an electrical contact with the gate and a source metal contact is deposited above and forms an electrical contact with the source. The source metal contact includes a plurality of metal through contacts positioned adjacent a side of the active area, the plurality of metal through contacts being spaced at intervals from one another and arranged in two or more rows. | 09-17-2009 |
| 20090230562 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device including a dummy via is disclosed. In the semiconductor integrated circuit device, problems such as reduction in the designability and increase in fabrication cost which result from the existence of a dummy wire connected to the dummy via are suppressed. The semiconductor integrated circuit device includes a substrate and three or more wiring layers formed on the substrate. The dummy via connects between a first wiring layer and a second wiring layer. The dummy wire connected to the dummy via exists in the second wiring layer. A protrusion amount of the dummy wire is smaller than a protrusion amount of an intermediate wire included in a stacked via structure. | 09-17-2009 |
| 20090230563 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of preventing a crack from occurring in an electrode layer exposed through a through hole which is formed in a semiconductor substrate and a method of manufacturing the semiconductor device. In exemplary embodiments, a through via and an opening in a passivation film are disposed so that an opening diameter of the through via is larger than an opening diameter of the opening of the passivation film, and an opening edge of the through via is located outside an opening edge of the opening of the passivation film. In other embodiments, the through via and the opening of the passivation film are disposed so that the opening edge of the through via is disposed at a location which does not overlap with the opening edge (opening edge of a portion in contact with a pad electrode) of the opening of the passivation film. | 09-17-2009 |
| 20090236749 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two semiconductor chips to the carrier; applying a second insulating layer over the carrier; opening the second insulating layer until the carrier is exposed; depositing a metal layer over the opened second insulating layer; and separating the at least two semiconductor chips after depositing the metal layer. | 09-24-2009 |
| 20090236750 | Package structure in which coreless substrate has direct electrical connections to semiconductor chip and manufacturing method thereof - A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip and a manufacturing method thereof are disclosed. The method includes the following steps: providing a metal carrier board having a cavity; placing a chip having a plurality of electrode pads on an active surface in the cavity of a board; filling the cavity with an adhesive for fixing the chip; forming a solder mask on the active surface of the chip and the surface of the metal carrier board at the same side, wherein the solder mask has a plurality of openings to expose the electrode pads of the chip; forming a built-up structure on the solder mask and the exposed active surface of the chip in the openings; and removing the metal carrier board. In this method the metal carrier board can support the built-up structure to thereby avoid warpage. | 09-24-2009 |
| 20090243119 | Semiconductor integrated circuit - Power wiring comprises a first-layer power wiring cluster in which VDD wiring trace and VSS wiring trace of different potentials at single trace width are arranged alternatingly; a second-layer power wiring cluster, disposed in a layer overlying the first-layer power wiring cluster, in which a VDD wiring trace and a VSS wiring trace of different potentials at single trace width are arranged alternatingly; and vias, placed in areas where the first-layer power wiring cluster and second-layer power wiring clusters intersect three-dimensionally, for electrically connecting wiring traces of the same potential in the first-layer power wiring cluster and wiring traces of the same potential in the second-layer power wiring cluster. A signal-wiring formation area is provided between mutually adjacent first-layer power wiring clusters and between mutually adjacent second-layer power wiring clusters. Design rule violation regarding via density is avoided without decline in integration or an increase in chip area. | 10-01-2009 |
| 20090243120 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT FABRICATION METHOD - A semiconductor element is provided that includes a semiconductor substrate, a circuit element disposed on the substrate, and a through-hole formed in the substrate having a stripe-like concavo-convex structure on its sidewall with stripes formed in the direction of the thickness of the semiconductor substrate. | 10-01-2009 |
| 20090243121 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD FOR THE SAME - A semi conductor integrated circuit includes a first via-contact configured to connect a first interconnection pattern provided for a first interconnection layer and a second interconnection pattern provided for a second interconnection layer, and a second via-contact configured to connect a third interconnection pattern provided for the first interconnection layer and the second interconnection pattern. A redundant interconnection pattern is formed in the first interconnection layer and configured to connect the first interconnection pattern and the third interconnection pattern to overlap above the second interconnection pattern. | 10-01-2009 |
| 20090256266 | APPARATUS AND METHOD FOR A CHIP ASSEMBLY INCLUDING A FREQUENCY EXTENDING DEVICE - A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands. | 10-15-2009 |
| 20090261478 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention constitutes a semiconductor device wherein a Ni-containing metal silicide layer is formed on a semiconductor substrate and its uppermost surface is nitrided. According to this structure, a dangling bond of silicon existing in the metal silicide layer and nitrogen are bonded by nitridation of the uppermost surface of the metal silicide layer. Therefore, diffusion of oxygen into the metal silicide layer can be suppressed. As a result, electrical insulation due to oxidation of the metal silicide layer can be reduced and the contact resistance can be stabilized. | 10-22-2009 |
| 20090267236 | Through-Hole Via on Saw Streets - A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes. | 10-29-2009 |
| 20090267237 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the trench pattern; forming a spacer film over the insulation film having the trench; etching the space film to form a spacer by using a blanket etching process, the spacer remaining over an edge of an inner portion of the trench; etching the insulation film to form a via hole by using as a mask the spacer; completely removing the spacer; forming a barrier film over sidewalls of the trench and the via hole; and forming a metal line with which fills inner portions of the trench and the via hole. | 10-29-2009 |
| 20090273093 | PLANAR PACKAGELESS SEMICONDUCTOR STRUCTURE WITH VIA AND COPLANAR CONTACTS - A semiconductor device includes a substrate having a first side and a second side and an epitaxial layer disposed over the second side. The device also includes a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and a bond pad disposed over the epitaxial layer and comprising a conductive material, wherein the semiconductor is not provided in a package. | 11-05-2009 |
| 20090278261 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An interlayer insulating film is formed on the upper surface of a semiconductor substrate, and lower-level interconnects are formed in the interlayer insulating film. A liner insulating film is formed on the upper surfaces of the interlayer insulating film and lower-level interconnects. An interlayer insulating film is formed on the upper surface of the liner insulating film. Upper-level interconnects are formed in the interlayer insulating film. The lower-level interconnects and the upper-level interconnects are connected with each other through vias. Parts of the liner insulating film formed in via-adjacent regions have a greater thickness than a part thereof formed outside the via-adjacent regions. | 11-12-2009 |
| 20090289375 | Dual Stress Liner Device and Method - A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure. | 11-26-2009 |
| 20090294983 | HYBRID CONDUCTIVE VIAS INCLUDING SMALL DIMENSION ACTIVE SURFACE ENDS AND LARGER DIMENSION BACK SIDE ENDS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND ASSOCIATED METHODS - A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed. | 12-03-2009 |
| 20090294984 | THREE-DIMENSIONAL INTEGRATED HETEROGENEOUS SEMICONDUCTOR STRUCTURE - A first set of semiconductor devices is formed on a first semiconductor substrate comprising a first semiconductor material having a first melting point. A first via-level dielectric layer containing first contact vias is formed on the first semiconductor substrate. A second semiconductor substrate comprising a second semiconductor material having a second melting point lower than the first melting point is formed either by bonding or deposition. A second set of semiconductor devices is formed on the second semiconductor substrate. A second via-level dielectric layer, second contact vias contacting the second set of semiconductor devices, and inter-substrate vias electrically connecting the first contact vias are thereafter formed. A metal interconnect layer containing a metal interconnect structure is formed over the second via-level dielectric layer to electrically connect the first and second set of semiconductor devices through the second contact vias and the inter-substrate vias. | 12-03-2009 |
| 20090294985 | THIN CHIP SCALE SEMICONDUCTOR PACKAGE - Chip scale semiconductor packages and methods for making and using such semiconductor packages are described. The chip scale packages include multiple terminals that are each disposed on a die back surface that is located opposite to an active area of a semiconductor substrate in the package. The active area can be electrically connected to a plurality of terminals by using traces that may be electrically isolated from the die substrate. In some designs, the terminals can comprise a gate terminal that electrically connected with a gate region of the active area, a source terminal electrically connected with a source region of the active area, and a drain terminal may electrically connected with the die substrate. Other embodiments are also described. | 12-03-2009 |
| 20090294986 | Methods of Forming Conductive Features and Structures Thereof - Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material. | 12-03-2009 |
| 20090294987 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To improve connection reliability of a through electrode in a semiconductor device, and prevent deterioration of electrical characteristics due to a residue generated from a pad at the time of forming the through electrode. A contact area between a pad | 12-03-2009 |
| 20090294988 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided. | 12-03-2009 |
| 20090294989 | FORMATION OF VERTICAL DEVICES BY ELECTROPLATING - The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures. | 12-03-2009 |
| 20090302478 | Semiconductor device and method of forming recessed conductive vias in saw streets - A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on the semiconductor die. A protective layer is formed over the front side of the semiconductor die. A portion of the insulating material and conductive via is removed from a backside of the semiconductor die opposite the front side of the semiconductor die so that a thickness of the conductive via is less than a thickness of the semiconductor wafer. The insulating material and conductive via are tapered. The wafer is singulated through the gap to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically interconnected through the conductive vias. | 12-10-2009 |
| 20090302479 | SEMICONDUCTOR STRUCTURES HAVING VIAS - A semiconductor structure comprises a substrate having a front surface and a back surface and a via extending from the first surface, the via comprising. The via comprises: a first side; a second side parallel to the first side; a first end extending between the first side and the second side; a second end opposite to the first end and extending between the first side and the second side. The first and second ends form oblique angles with the first and second sides. A method of fabricating the vias is also described. | 12-10-2009 |
| 20090302480 | Through Substrate Via Semiconductor Components - A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening. | 12-10-2009 |
| 20090302481 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a technology for manufacturing a higher performance and higher reliability semiconductor device at low cost and with high yield. The semiconductor device of the invention has a first conductive layer over a first insulating layer; a second insulating layer over the first conductive layer, which includes an opening extending to the first conductive layer; and a signal wiring layer for electrically connecting an integrated circuit portion to an antenna and a second conductive layer adjacent to the signal wiring layer, which are formed over the second insulating layer. The second conductive layer is in contact with the first conductive layer through the opening, and the first conductive layer overlaps the signal wiring layer with the second insulating layer interposed therebetween. | 12-10-2009 |
| 20090309232 | METHOD OF MAKING CONNECTIONS IN A BACK-LIT CIRCUIT - A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, including the steps of: forming, on the side of a first surface of a substrate, an insulating region penetrating into the substrate and coated with a conductive region and with an insulating layer crossed by conductive vias, the vias connecting a metal track of the interconnect stack to the conductive region; gluing the external surface of the interconnect stack on a support and thinning down the substrate; etching the external surface of the thinned-down substrate and stopping on the insulating region; etching the insulating region and stopping on the conductive region; and filling the etched opening with a metal. | 12-17-2009 |
| 20090309233 | SEMICONDUCTOR DEVICE - The semiconductor device includes an interconnect having a width of 0.1 μm or less and formed in an insulating layer constituted of a low relative dielectric constant film having a relative dielectric constant of 3.0 or lower, a via having a diameter of 0.1 μm or less and connected to the interconnect, and a dummy metal provided in the insulating layer. The dummy metal is located close to an end portion of the interconnect along an extension thereof, and the dummy metal and the interconnect are spaced by a distance of 0.3 μm or less. | 12-17-2009 |
| 20090309234 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip. | 12-17-2009 |
| 20090315188 | SILICON-ON-INSULATOR STRUCTURES FOR THROUGH VIA IN SILICON CARRIERS - A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material. | 12-24-2009 |
| 20090321945 | SIDE WALL PORE SEALING FOR LOW-K DIELECTRICS - A dual damascene process for forming conductive interconnects on an integrated circuit die. The process comprises providing a layer ( | 12-31-2009 |
| 20090321946 | PROCESS FOR FABRICATING AN INTEGRATED ELECTRONIC CIRCUIT INCORPORATING A PROCESS REQUIRING A VOLTAGE THRESHOLD BETWEEN A METAL LAYER AND A SUBSTRATE - A process for fabricating an electronic integrated circuit comprising a multi-layer interconnect stack. A structure ( | 12-31-2009 |
| 20100001405 | INTEGRATED CIRCUIT STRUCTURE - An integrated circuit and corresponding method of manufacture. The integrated circuit has a die comprising: an outer strengthening ring around a periphery of the die, the outer ring having one or more gaps; and an inner strengthening ring within the outer ring and around interior circuitry of the die, the inner ring having one or more gaps offset from the gaps of the outer ring. One or more conducting members are electrically isolated from said rings and electrically connected to the interior circuitry, each member passing through a gap of the inner ring and through a gap of the outer ring. | 01-07-2010 |
| 20100001406 | ARTIFICIALLY TILTED VIA CONNECTION - A semiconductor integrated circuit with tilted via connection and related method are provided, the circuit including a via layer having at least one tilted via, and a wireway layer having at least one elongated wireway disposed above the via layer, wherein the wireway connects to and partially overlaps the tilted via; and the method including forming a via layer, patterning a via trench in the via layer, forming a wireway layer, patterning an elongated wireway in the wireway layer, etching the patterned wireway and the patterned via, and filling the etched wireway and the etched via with a conductive material, wherein the filled wireway partially overlaps the filled via. | 01-07-2010 |
| 20100001407 | GALVANIC MASK - A method for the production of a contact structure of a semiconductor component comprises the masking of at least one side of a semiconductor substrate with a coating and the partial removal thereof in at least one pre-determined region. | 01-07-2010 |
| 20100001408 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor chip including a wire and a passivation film formed on the outermost surface with an opening partially exposing the wire; a resin layer stacked on the semiconductor chip and provided with a through-hole in a position opposed to a portion of the wire facing the opening; and a pad formed on a peripheral portion of the through-hole in the resin layer and in the through-hole so that an external connection terminal is arranged on the surface thereof. The peripheral portion of the resin layer is formed more thickly than the remaining portion of the resin layer other than the peripheral portion. | 01-07-2010 |
| 20100001409 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - The invention relates to a semiconductor device comprising: a substrate ( | 01-07-2010 |
| 20100007028 | DEVICE INCLUDING AN IMIDE LAYER WITH NON-CONTACT OPENINGS AND METHOD - A device including an imide layer with non-contact openings and the method for producing the device. One embodiment provides a substrate on a main surface of the substrate, an imide layer on the metallization layer, at least one contact opening through the imide layer and a plurality of non-contact openings in the imide layer. The non-contact openings are dimensioned to provide for an increased surface area of the imide layer or a surface area of the imide layer which is not reduced by more than 10 percent. | 01-14-2010 |
| 20100007029 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED-DOWN RDL AND RECESSED THV IN PERIPHERAL REGION OF THE DEVICE - A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer. | 01-14-2010 |
| 20100007030 | Semiconductor device, method for manufacturing semiconductor device, method for manufacturing semiconductor package - There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section. | 01-14-2010 |
| 20100007031 | AGENT FOR POST-ETCH TREATMENT OF SILICON DIELECTRIC FILM, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The invention provides an agent for post-etch treating a silicon dielectric film, including: at least one nitrogen-containing substance selected from the group consisting of ammonium bases and amine compounds; an acid; and at least one silicon-containing compound containing silicon, carbon and hydrogen. According to the present invention, it becomes possible to suppress an increase in the dielectric constant of a silicon dielectric film caused by etching. | 01-14-2010 |
| 20100013102 | Semiconductor Device and Method of Providing a Thermal Dissipation Path Through RDL and Conductive Via - A semiconductor device has a conductive via formed around a perimeter of the semiconductor die. First and second conductive layers are formed on opposite sides of the semiconductor die and thermally connected to the conductive via. An insulating layer is formed over the semiconductor die. A portion of the insulating layer is removed to expose the first conductive layer and a thermal dissipation region of semiconductor die. A thermal via is formed through the insulating layer to the first conductive layer. A thermally conductive layer is formed over the thermal dissipation region and thermal via. A thermal conduction path is formed from the thermal dissipation region through the thermally conductive layer, thermal via, first conductive layer, conductive via, and second conductive layer. The thermal conduction path terminates in an external thermal ground point. The thermally conductive layer provides shielding for electromagnetic interference. | 01-21-2010 |
| 20100013103 | Semiconductor embedded module and method for producing the same - A semiconductor embedded module | 01-21-2010 |
| 20100013104 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening. | 01-21-2010 |
| 20100013105 | METHOD OF MANUFACTURING PHOTOMASK AND METHOD OF REPAIRING OPTICAL PROXIMITY CORRECTION - A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data. | 01-21-2010 |
| 20100019390 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, MANUFACTURING METHODS THEREOF, AND STACK PACKAGE - A manufacturing method includes sequentially forming first and second material layers having different etch selectivities in a laminated fashion, patterning the second material layer, to form an etch mask, etching the first material layer using the etch mask, to form a via hole in the first material layer, forming a photo mask over the etch mask such that a region larger than the via hole is exposed through the photo mask, etching the etch mask using the photo mask, removing the photo mask, and forming a metal material over the first material layer, to fill the via hole. Accordingly, it is possible to prevent formation of a side wall undercut in a deep via etching process, and thus to ease subsequent processes for forming an oxide barrier film, a barrier metal film, and a metal layer. | 01-28-2010 |
| 20100025857 | IC CHIP AND DESIGN STRUCTURE WITH THROUGH WAFER VIAS DISHING CORRECTION - An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact. | 02-04-2010 |
| 20100025858 | WINGED VIAS TO INCREASE OVERLAY MARGIN - Winged via structures to increase overlay margin are generally described. In one example, a method comprises depositing a sacrificial layer to an interlayer dielectric, the interlayer dielectric being coupled with a semiconductor substrate, forming at least one trench structure in the sacrificial layer wherein the trench structure comprises a first direction along a length of the trench structure and a second direction along a width of the trench structure wherein the second direction is substantially perpendicular to the first direction, depositing a light sensitive material to the trench structure and the sacrificial layer, and patterning at least one winged via structure in the light sensitive material to overlay the trench structure wherein the winged via structure extends in the second direction beyond the width of the trench structure onto the sacrificial layer. | 02-04-2010 |
| 20100025859 | METHOD FOR DESIGNING SEMICONDUCTOR DEVICE, PROGRAM THEREFOR, AND SEMICONDUCTOR DEVICE - A method for designing a semiconductor device includes computing a contact resistance value based on an allowable power supply voltage drop set for a second position corresponding to a given region of a second power supply line on a second wiring layer different from a first wiring layer, and computing a number of vias for the given region based on a result of a comparison between a resistance value of a via coupling a first power supply line and the second power supply line and the contact resistance value. | 02-04-2010 |
| 20100025860 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device, may include
| 02-04-2010 |
| 20100032846 | IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD - An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer. | 02-11-2010 |
| 20100038800 | THROUGH-SILICON VIA STRUCTURES INCLUDING CONDUCTIVE PROTECTIVE LAYERS AND METHODS OF FORMING THE SAME - Through-Silicon-Via (TSV) structures can include a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate opposite the upper surface, a conductive protective layer including Ni and/or Co can be at a bottom of the conductive via, and a separate polymer insulating layer can be on the backside surface of the substrate in contact with the conductive protective layer. | 02-18-2010 |
| 20100044876 | CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES - Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate. | 02-25-2010 |
| 20100052184 | INTERCONNECTS WITH IMPROVED TDDB - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material. | 03-04-2010 |
| 20100052185 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a semiconductor element, a first electrode of the semiconductor chip being configured on a first surface of the semiconductor element, a second electrode of the semiconductor element being configured on a second surface opposed to the first surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, a first hole and a second hole being configured in the encapsulating material, a portion of the first electrode and a portion of the second electrode being exposed, a first conductive material being connected to the first surface of the semiconductor chip via the first hole, a second conductive material being connected to the second surface of the semiconductor chip via the second hole, and a plating film covering five surfaces of the first conductive material other than one surface contacting with the encapsulating material and five surfaces of the second conductive material other than one surface contacting with the encapsulating material. | 03-04-2010 |
| 20100059894 | METHOD OF MANUFACTURING OPENINGS IN A SUBSTRATE, A VIA IN SUBSTRATE, AND A SEMICONDUCTOR DEVICE COMPRISING SUCH A VIA - The invention relates to a method of manufacturing openings in a substrate ( | 03-11-2010 |
| 20100059895 | SEMICONDUCTOR DEVICE HAVING AN INTERLAYER INSULATING FILM WIRING LAMINATED STRUCTURE SECTION AND METHOD OF FABRICATING THE SAME - In the manufacture of a semiconductor, in unnecessary semiconductor device formation areas | 03-11-2010 |
| 20100065970 | MICROFEATURE WORKPIECES HAVING CONDUCTIVE INTERCONNECT STRUCTURES FORMED BY CHEMICALLY REACTIVE PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide. | 03-18-2010 |
| 20100072626 | WAFER LEVEL PACKAGED MEMS INTEGRATED CIRCUIT - A wafer-level packaged integrated circuit includes a semiconductor substrate including a first silicon layer. A micro-electromechanical system (MEMS) device is integrated into the first silicon layer. A thin-film deposited sealing member is deposited over the first silicon layer and is configured to seal a cavity in the first silicon layer. At least one additional layer is formed over the sealing member. At least one under bump metallization (UBM) is formed over the at least one additional layer. | 03-25-2010 |
| 20100072627 | WAFER INCLUDING INTERCEPTING THROUGH-VIAS AND METHOD OF MAKING INTERCEPTING THROUGH-VIAS IN A WAFER - A semiconductor device includes a substrate; a first via provided in the substrate extending from a first side of the substrate to a first depth into the substrate, the first depth being less than a thickness of the substrate and the first via having a first width in one direction; a first conductive material provided in the first via; a second via provided in the substrate extending from a second side of the substrate to a second depth into the substrate, the second via having a second width in one direction, the second width being greater than the first width; and a second conductive material provided in the second via so as to form an electrical connection with the first conductive material provided in the first via. | 03-25-2010 |
| 20100072628 | SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip. | 03-25-2010 |
| 20100072629 | Wiring Structure, Semiconductor Device Having the Wiring Structure, and Method for Manufacturing the Semiconductor Device - A wiring structure, a semiconductor device having the structure, and a method for manufacturing the semiconductor device are disclosed. The wiring structure includes a first metal layer, a second metal layer on the first metal layer, an insulating layer between the first metal layer and the second metal layer, and a metal via pattern formed in the insulating layer to electrically connect the first and second metal layers to each other. The metal via pattern includes a plurality of metal vias spaced apart from one another, and each of the metal vias includes a vertical via line extending in a vertical direction and a horizontal via line extending in a horizontal direction to cross the vertical via line. The wiring structure may achieve minimized chip defects, fewer cracks in the insulating layer, effective use of the occupation area of a semiconductor chip, and reduced chip size and manufacturing costs. | 03-25-2010 |
| 20100078825 | METHOD FOR FABRICATING INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES - Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer. | 04-01-2010 |
| 20100078826 | SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE - An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads. | 04-01-2010 |
| 20100078827 | MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION - A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated. | 04-01-2010 |
| 20100084770 | SEMICONDUCTOR DEVICE WHICH INCLUDES CONTACT PLUG AND EMBEDDED INTERCONNECTION CONNECTED TO CONTACT PLUG - A semiconductor memory device includes: a first dielectric formed on top of a semiconductor substrate; a contact plug embedded in the first dielectric; a second dielectric formed on top of the first interlayer dielectric; an interconnection layer embedded in a groove formed in the second dielectric on top of the contact plug; and an insulating film formed in the second dielectric adjacent to a side surface of the interconnection layer. The contact plug has a notch in a part of a top surface of the contact plug. The insulating film is formed to extend from a top surface of the second dielectric to the notch included in the contact plug. | 04-08-2010 |
| 20100096759 | SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate. | 04-22-2010 |
| 20100096760 | Bond Pad Design with Reduced Dishing Effect - An integrated circuit structure includes a semiconductor chip, which further includes a first surface; and a patterned bond pad exposed through the first surface. The patterned bond pad includes a plurality of portions electrically connected to each other, and at least one opening therein. The integrated circuit further includes a dielectric material filled into at least a portion of the at least one opening. | 04-22-2010 |
| 20100102453 | Three-Dimensional Integrated Circuit Stacking-Joint Interface Structure - A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV. | 04-29-2010 |
| 20100102454 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - When an etch stopper film is stacked on a pad electrode in which an opening is provided and a through electrode is embedded in a through hole formed in a semiconductor substrate, a distal end of the through electrode penetrates a part of the pad electrode via the opening and is stopped by the etch stopper film. | 04-29-2010 |
| 20100102455 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first layer; a second layer above the first layer; first and second multi-layered structures; and a supporter. The first and second multi-layered structures extend from the first layer to connect to the second layer. The supporter extends from the first layer to connect to the second layer. The supporter is between the first and second multi-layered structures. The supporter is separated from the first and second multi-layered structures by empty space. | 04-29-2010 |
| 20100102456 | Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets - A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die. | 04-29-2010 |
| 20100109164 | STACKED INTEGRATED CIRCUIT PACKAGE FABRICATION METHODS THAT USE VIAS FORMED AND FILLED AFTER STACKING, AND RELATED STACKED INTEGRATED CIRCUIT PACKAGE STRUCTURES - Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages arc also described. | 05-06-2010 |
| 20100123256 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core. | 05-20-2010 |
| 20100127403 | SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS - There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning. | 05-27-2010 |
| 20100127404 | SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device, insulation resistance of the porous film is stabilized, and leakage current between adjacent interconnects provides an improved reliability in signal propagation therethrough. The method includes: sequentially forming over a semiconductor substrate a porous film and a patterned resist film; forming a concave exposed surface of the substrate; forming a non-porous film covering the interior wall of the concave portion and the porous film; selectively removing the non-porous film from the bottom of the concave portion and the non-porous film by anisotropic etch; forming a barrier metal film covering the porous film and the interior wall; and forming a metallic film on the barrier metal film to fill the concave portion. The anisotropic etch process uses an etching gas with mixing ratio MR, 45≦MR≦100, where MR=((gaseous “nitrogen” containing compound)+(inert gas))/(gaseous “fluorine” containing compound). | 05-27-2010 |
| 20100133696 | Isolation Structure for Protecting Dielectric Layers from Degradation - An integrated circuit structure includes a semiconductor substrate; and an interconnect structure overlying the semiconductor substrate. A solid metal ring is formed in the interconnect structure, with substantially no active circuit being inside the solid metal ring. The integrated circuit structure further includes a through-silicon via (TSV) having a portion encircled by the solid metal ring. The TSV extends through the interconnect structure into the semiconductor substrate. | 06-03-2010 |
| 20100133697 | LOW RESISTANCE THROUGH-WAFER VIA - The present invention provides a wafer ( | 06-03-2010 |
| 20100133698 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which enables reduction of material costs and manufacturing costs of the semiconductor device includes forming a silicon cermet film, forming a protective film that protects the silicon cermet film, making a contact hole by plasma etching of the protective film. In this method, an etching detection layer for detecting an end point of plasma etching is formed in contact with the protective film, at least one of the protective film and the etching detection layer contains an element not common to both of the protective film and the etching detection layer, and an end point of plasma etching of the protective film is detected based on plasma emission of the element not common to the both when making the contact hole. | 06-03-2010 |
| 20100133699 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH AIR GAPS FORMED COMMONLY WITH VIAS - Air gaps may be formed in a metallization layer of a microstructure device on the basis of a patterning sequence in which respective via openings are also formed. Thereafter, the via openings and the air gaps may be closed by a deposition process without significantly affecting the interior of the corresponding openings. Thereafter, the further processing may be continued by forming respective trenches while maintaining integrity of the covered air gaps. Thus, the relative permittivity of the interlayer dielectric material may be efficiently reduced without adding additional process complexity. | 06-03-2010 |
| 20100133700 | PERFORMANCE ENHANCEMENT IN METALLIZATION SYSTEMS OF MICROSTRUCTURE DEVICES BY INCORPORATING GRAIN SIZE INCREASING METAL FEATURES - In a sophisticated metallization system, enhanced electromigration behavior may be accomplished by incorporating electromigration barriers into metal lines after a given distance, which may be accomplished by providing an increased width in order to obtain an enhanced average grain size in the intermediate metal regions of increased lateral width. Consequently, the electromigration induced material diffusion may encounter an overall increased grain size along the entire depth of the metal lines, thereby resulting in a significantly reduced electromigration effect and thus enhanced reliability of the critical metal lines. | 06-03-2010 |
| 20100133701 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits. | 06-03-2010 |
| 20100133702 | METHOD FOR ELIMINATING LOADING EFFECT USING A VIA PLUG - Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug. | 06-03-2010 |
| 20100140807 | INSULATING FILM MATERIAL, MULTILAYER WIRING BOARD AND PRODUCTION METHOD THEREOF, AND SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - An insulating film material, which contains a polycarbosilane compound expressed by the following structural formula 1; | 06-10-2010 |
| 20100140808 | Power Distribution In A Vertically Integrated Circuit - A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path. | 06-10-2010 |
| 20100148370 | THROUGH-SILICON VIA AND METHOD FOR FORMING THE SAME - A method for forming a through-silicon via includes the steps of defining a groove in each chip of a wafer which has a plurality of semiconductor chips; applying liquid polymer on the wafer to fill the groove; forming an insulation layer on a sidewall of the groove through patterning the polymer; forming a metal layer to fill the groove which is formed with the insulation layer on the sidewall thereof; and back-grinding a backside of the wafer to expose the metal layer filled in the groove. | 06-17-2010 |
| 20100155961 | MICROMECHANICAL COMPONENT HAVING WAFER THROUGH-PLATING AND CORRESPONDING PRODUCTION METHOD - A wafer through-plating through a semiconductor substrate and a method for producing this wafer through-plating. At least one via hole is inserted in the front side of a semiconductor substrate, in this context, in order to form the wafer through-plating using a trench etching process. The semiconductor material of the side wall of the via hole is then porously etched in an electrochemical etching process. A metal is introduced into the via hole in order to produce the electrical contact-making connection. In order to enable the electrical connection from the front side to the back side of the semiconductor substrate, the via hole is opened from the back side, for example, by thinning the semiconductor substrate. This opening may be made, in this context, before or after the metal is introduced into the via hole. | 06-24-2010 |
| 20100155962 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a diffusion region provided on a surface portion of a first surface of the semiconductor substrate, a first line provided on the first surface of the semiconductor substrate, a through-hole penetrating the semiconductor substrate in the thickness direction, and a through-hole electrode provided in the through-hole, and contacting a rear surface of the first line and extending to a second surface opposite the first surface of the semiconductor substrate. The semiconductor device further includes a recess provided on the second surface of the semiconductor substrate and a second line provided in the recess and electrically connected to the through-hole electrode. | 06-24-2010 |
| 20100155963 | DUMMY VIAS FOR DAMASCENE PROCESS - An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer. | 06-24-2010 |
| 20100164116 | ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT - A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations. | 07-01-2010 |
| 20100164117 | Through-Silicon Via With Air Gap - A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the liner, which is subsequently removed to form an air gap around the conductive material of the through-silicon via. A dielectric layer is formed of the backside of the semiconductor substrate to seal the air gap. | 07-01-2010 |
| 20100164118 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING METAL CONTACT - A method for fabricating a semiconductor device includes: forming first landing metal contacts over a substrate; forming a plurality of bit lines over the first landing metal contacts, the bit lines insulated from the first landing metal contacts by an inter-layer insulation layer; forming second landing metal through-hole contacts passing between adjacent bit lines to be coupled to the first landing metal contacts; forming metal contacts over the second landing metal contacts; and forming a metal line over the metal contacts. | 07-01-2010 |
| 20100164119 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes steps of forming an organic insulating film over a semiconductor substrate, irradiating an electron beam to a surface of the organic insulating film, forming recesses in the organic insulating film, forming a conductive material over the organic insulating film and in the recesses, and removing the conductive material on the organic insulating film by a polishing to expose the surface of the organic insulating film and to leave the conductive material buried in recesses of the organic insulating film. | 07-01-2010 |
| 20100164120 | THROUGH-HOLE ELECTRODE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A through-hole electrode substrate related to an embodiment of the present invention is arranged with a semiconductor substrate having a plurality of through-holes, an insulating layer formed with an insulating material on the inner walls of the plurality of through-holes and on at least one surface of the semiconductor substrate, a plurality of through-hole electrodes formed with a metal material inside the through-hole, and a plurality of gas discharge parts formed to contact with each of the plurality of through-hole electrodes which is exposed on at least one surface of the semiconductor substrate, the plurality of gas discharge parts externally discharges gas which is discharged from the inside of the plurality of through-hole electrodes. | 07-01-2010 |
| 20100164121 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING EXTRA-TAPERED TRANSITION VIAS - In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto. | 07-01-2010 |
| 20100164122 | METHOD OF FORMING CONDUCTIVE LAYER AND SEMICONDUCTOR DEVICE - Provided are a method of forming a conductive layer on an inner portion of a through-electrode in which uniform adhesion property of plating in the inner portion of a through-hole is enhanced and a tact time is short, and a semiconductor device. The method of forming a conductive layer includes: a first plating step of forming a first plating layer on the inner portion of the through-hole; a plating suppression layer forming step of forming a plating suppression layer including a material different from a material of the first plating layer in an opening portion of the through-hole after the first plating step; and a second plating step of forming a second plating layer by plating on the inner portion of the through-hole after the plating suppression layer forming step. | 07-01-2010 |
| 20100164123 | LOCAL SILICIDATION OF VIA BOTTOMS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof. | 07-01-2010 |
| 20100171226 | IC HAVING TSV ARRAYS WITH REDUCED TSV INDUCED STRESS - An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively. | 07-08-2010 |
| 20100176515 | CONTACT PAD SUPPORTING STRUCTURE AND INTEGRATED CIRCUIT - The invention provides a contact pad supporting structure. The contact pad supporting structure includes an underlying first conductive plate and an overlying second conductive plate, wherein the first and second conductive plates are separated by a first dielectric layer. A plurality of circular ring-shaped via plug groups comprising a plurality of circular ring-shaped via plugs is through the first dielectric layer, electrically connecting to the first and second conductive plates. All of the circular ring-shaped via plugs of each of the circular ring-shaped via plug groups are disorderly arranged. | 07-15-2010 |
| 20100181682 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device, includes forming an insulating film of a material having a low relative dielectric constant on a substrate, forming an SiOCH film on the insulating film in a chamber, forming an SiO | 07-22-2010 |
| 20100181683 | VIA DEFINITION FOR SEMICONDUCTOR DIE - A semiconductor die includes a first set of metal lines and a second set of metal lines. The first set of metal lines and the second set of metal lines are placed in alternate planes and are orthogonal to each other. A via is used to connect a first metal line from the first set of metal lines with a second metal line from the second set of metal lines. The via location is offset such that a side of the first metal line is aligned with a side of the second metal line. Consequently, a metal line adjacent to the first metal line does not need to detour around the via. | 07-22-2010 |
| 20100181684 | RESIN COMPOSITION, FILLING MATERIAL, INSULATING LAYER AND SEMICONDUCTOR DEVICE - A resin composition of the present invention is used for forming a filling material which fills at least a through-hole of a semiconductor substrate, the through-hole extending through the semiconductor substrate in a thickness direction thereof and having a conductive portion therein. The resin composition is composed of: a resin having a radical-polymerizable double bond, a thermosetting resin and a resin which differs from the resin having the radical-polymerizable double bond and has an alkali-soluble group and a double bond; or a cyclic olefin resin. A filling material of the present invention is formed of a cured product of the above resin composition. An insulating layer of the present invention is formed of a cured product of the above resin composition. The insulating layer includes: a layer-shaped insulating portion provided on a surface opposite to a functional surface of the semiconductor substrate; and a filling portion integrally formed with the insulating portion and filling the through-hole. A semiconductor device of the present invention includes the above insulating layer. | 07-22-2010 |
| 20100187698 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first wiring layer, a first interlayer insulating film over the first wiring layer, a second wiring layer crossing the first wiring layer and provided on the first interlayer insulating film, a second interlayer insulating film over the second wiring layer, and a via conductor electrically connecting the first wiring layer and the second wiring layer together. The second wiring layer includes a space separating the second wiring layer into pieces, the space being located at a position where the second wiring layer crosses the first wiring layer. The via conductor passes through the separation space such that the separated pieces of the second wiring layer are electrically connected together, the via conductor extending to the first wiring layer through the second interlayer insulating film and the first interlayer insulating film. | 07-29-2010 |
| 20100193963 | VOID SEALING IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE COMPRISING CLOSELY SPACED TRANSISTORS - In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved. | 08-05-2010 |
| 20100193964 | METHOD OF MAKING 3D INTEGRATED CIRCUITS AND STRUCTURES FORMED THEREBY - A method and structure of connecting at least two integrated circuits in a 3D arrangement by a through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit. | 08-05-2010 |
| 20100193965 | SEMICONDUCTOR DEVICE HAVING WIRINGS FORMED BY DAMASCENE - An insulating film is formed over a semiconductor substrate. A wiring trench formed in the insulating film reaches partway in a thickness direction of the insulating film. A via hole is disposed at an end of the wiring trench. A barrier metal film covers inner surfaces of the wiring trench and via hole. A bottom of the wiring trench and a sidewall of the via hole are connected via an inclined plane. A length of a portion of the inclined plane having an inclination angle range of 40° to 50° relative to a surface of the semiconductor substrate is equal to or shorter than a maximum size of a plan shape of the via hole, in a cross section which is parallel to a longitudinal direction of the wiring trench, passes a center of the via hole and perpendicular to the surface of the semiconductor surface. | 08-05-2010 |
| 20100193966 | Contact Structures and Semiconductor Devices Including the Same - Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are is etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes. | 08-05-2010 |
| 20100200996 | Structural feature formation within an integrated circuit - An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts | 08-12-2010 |
| 20100200997 | SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first plug formed on a semiconductor substrate and exposed on side and upper surfaces of an upper part thereof and a second plug formed on the first plug to contact the exposed side and upper surfaces of the upper part of the first plug. | 08-12-2010 |
| 20100200998 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted. | 08-12-2010 |
| 20100200999 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex. | 08-12-2010 |
| 20100213618 | Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material - A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die. | 08-26-2010 |
| 20100225002 | Three-Dimensional System-in-Package Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies. | 09-09-2010 |
| 20100225003 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINABLE WITH SUCH A METHOD - A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a semiconductor intermediate product. The hard-mask layer covers the exposed surface in covered areas of the one or more layers to be patterned and does not cover the exposed surface in bared areas of the one or more layers to be patterned. One or more recesses are formed in the layers to be patterned by at least partially removing the layers to be patterned in the bared areas. The hard-mask layer is ten removed. After removing the hard-mask layer the recess is filled with a filling material. | 09-09-2010 |
| 20100225004 | SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A semiconductor apparatus including a semiconductor substrate having a first principal surface on which an electric circuit is formed and a second principal surface opposed to the first principal surface, and a through hole that penetrates the first principal surface and the second principal surface, a multilayered wiring layer having a plurality of conductive wiring layers connected to the electric circuit and a plurality of inter-layer insulating layers having an insulating layer opening of a same size and at a same position as a through hole opening which is an opening of the first principal surface of the through hole, an electrode pad that covers the insulating layer opening connected to the conductive wiring layer and a lead-out wiring layer having a through wiring layer connected to the electrode pad formed inside the through hole and a connection wiring layer formed integral with the through wiring layer. | 09-09-2010 |
| 20100225005 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions. | 09-09-2010 |
| 20100225006 | CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS - A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias. | 09-09-2010 |
| 20100230824 | Metal Interconnect of Semiconductor Device - Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device. | 09-16-2010 |
| 20100237508 | POWER-SUPPLY WIRING STRUCTURE FOR MULTILAYER WIRING AND METHOD OF MANUFACTURING MULTILAYER WIRING - A power-supply wiring structure for a multilayer wiring according to an embodiment of the present invention includes one intermediate wiring layer with a first direction set as a priority wiring direction including a position converting and connecting wire, which has crossing-position forming sections formed in crossing positions of upper-layer power supply wires and lower-layer power supply wires of the same kind and projecting sections projecting from the crossing-position forming sections to sides of upper-layer power supply wires of different kinds, and includes a wire connecting section that connects between the upper layer wires and the crossing-position forming section and connects between the projecting section and the lower layer wires via vias. | 09-23-2010 |
| 20100244274 | WIRING BOARD - A wiring board includes a first conductor constituting a signal line, a second conductor constituting a ground conductor or a power conductor, a dielectric layer disposed between and separately the first and second conductors, and a third conductor arranged between the first and second conductor, the third conductor being connected to the second conductor, and having a width narrower than that of the first conductor, the third conductor entirely opposing the first conductor, the entire portion of the third conductor being covered by the first conductor. | 09-30-2010 |
| 20100244275 | CONTACT STRUCTURE FOR AN ELECTRONIC CIRCUIT SUBSTRATE AND ELECTRONIC CIRCUIT COMPRISING SAID CONTACT STRUCTURE - A substrate for an electronic circuit is provided wherein the substrate comprises a plurality of contact areas ( | 09-30-2010 |
| 20100252934 | Three-Dimensional Semiconductor Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate. | 10-07-2010 |
| 20100252935 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same according to an embodiment. In the method, a portion of a substrate comprising a pad is removed to form a via hole. An insulating layer is formed on the substrate. A portion of the insulating layer is removed to form an opening part comprising a plurality of openings exposing portions of the pad. A through electrode is formed to fill the via hole and to be electrically connected to the pad through one of the plurality of openings. A portion of the pad is exposed by another opening among the plurality of openings. | 10-07-2010 |
| 20100258946 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode. | 10-14-2010 |
| 20100258947 | Nonvolatile memory devices - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays. | 10-14-2010 |
| 20100258948 | Semiconductor Wafer and Method of Manufacturing the Same and Method of Manufacturing Semiconductor Device - A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes. | 10-14-2010 |
| 20100264548 | THROUGH SUBSTRATE VIAS - Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region ( | 10-21-2010 |
| 20100264549 | Trench Substrate and Method Of Manufacturing The Same - Disclosed herein are a trench substrate and a method of manufacturing the same. The trench substrate includes a base substrate, an insulating layer formed on one side or both sides of the base substrate and including trenches formed in a circuit region and a dummy region positioned at a peripheral edge of the trench substrate, and a circuit layer formed in the trenches of the circuit region through a plating process and including a circuit pattern and vias. Thanks to formation of the trenches in the dummy region and the cutting region, deviation in thickness of a plating layer formed on the insulating layer in a plating process is improved upon. | 10-21-2010 |
| 20100264550 | SELF-ALIGNED CONTACT - A self-aligned contact includes a lower contact disposed in a dielectric layer of a substrate and an upper contact disposed in the dielectric layer and directly on the lower contact, and electrically connected to the lower contact. The profile of the upper contact and the lower contact is zigzag. | 10-21-2010 |
| 20100270682 | Implementing Vertical Airgap Structures Between Chip Metal Layers - A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first layer of silicon dioxide dielectric above the first metal layer. A second layer of silicon dioxide dielectric is deposited and the vertical air gap is sealed. A next trace layer is etched from the second layer of silicon dioxide dielectric and a via opening is etched from the second and first layers of silicon dioxide dielectric. Then metal is deposited into the next trace layer and metal is deposited into the via opening. | 10-28-2010 |
| 20100270683 | Semiconductor device and method of manufacturing semiconductor device - An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating layer, the air gap, and the interconnect. A second insulating layer is formed over the etching stopper film. A via is provided in the second insulating layer and is connected to the interconnect. A portion of the etching stopper film that is disposed over the air gap is thicker than another portion that is disposed over the interconnect. | 10-28-2010 |
| 20100270684 | CHIP IDENTIFICATION USING TOP METAL LAYER - An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin. | 10-28-2010 |
| 20100270685 | DIE BONDING UTILIZING A PATTERNED ADHESION LAYER - An electronic package and method and system for forming the electronic package. The electronic package has a first substrate including a first electronic device and including through-holes extending through an entire thickness of the first substrate. The electronic package has a second substrate bonded to the first substrate, metallizations formed in the through-holes of the first substrate to connect to components of the first electronic device, and a patternable substance disposed between the first substrate and the second substrate and adhering the first substrate and the second substrate together in regions apart from the metallizations. The method and system form through-holes extending through an entire thickness of the first substrate, deposit and pattern an adherable substance on the second substrate in a pattern having openings which expose connections for a second electronic device of the second substrate, align and attach the first substrate and the second substrate together, and form metallizations in the through-holes to connect to the connections for the second electronic device. | 10-28-2010 |
| 20100270686 | Semiconductor device - The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer. | 10-28-2010 |
| 20100276814 | METHODS FOR PACKAGING MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED USING SUCH METHODS - Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed toward a method for packaging a microelectronic device that includes coupling an active side of a microelectronic die to a surface of a support member. The microelectronic die can have a backside opposite the active side, a peripheral side extending at least part way between the active side and the backside, and at least one through-wafer interconnect. The method can further include applying an encapsulant to cover a portion of the surface of the support member so that a portion of the encapsulant is laterally adjacent to the peripheral side, removing material from a backside of the microelectronic die to expose a portion of at least one through-wafer interconnect, and applying a redistribution structure to the backside of the microelectronic die. | 11-04-2010 |
| 20100283159 | Circuit Substrate and Method for Utilizing Packaging of the Circuit Substrate - A circuit substrate and the method for fabricating a packaging of the circuit substrate are provided. A plurality of electrodes are formed on the surface of the circuit substrate, the electrodes are formed with fork structures over an connection section of the circuit substrate, so that when the circuit substrate expands/contracts due to thermal processes, the probability of alignment with electrodes of an external circuit board is increased by easily detaching the fork structure overlapping an electrode of the external circuit board which is not corresponding to the fork structure of the electrode of the circuit substrate, so as to avoid short circuit. Thus, electrode misalignment due to electrode pitch variation of the traditional circuit substrate as a result of thermal deformation can be effectively eliminated. | 11-11-2010 |
| 20100289154 | METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING - A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element. | 11-18-2010 |
| 20100289155 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. The semiconductor device includes a semiconductor substrate and a penetration electrode penetrating the semiconductor substrate. A cavity part is formed in the semiconductor substrate to isolate the penetration electrode from the semiconductor substrate. A connection terminal is provided at a position where the connection terminal does not overlap the penetration electrode in a plan view. The connection terminal electrically connects the semiconductor device to the wiring board. | 11-18-2010 |
| 20100295188 | SEMICONDUCTOR DEVICE HAVING DEEP CONTACT STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a deep contact structure having an improved contact resistance is presented. The semiconductor device includes a semiconductor substrate, a first interlayer insulating layer, a contact plug, a second interlayer insulating layer, and a copper contact pad. The contact plug is formed in the first interlayer insulating layer and has a bulbous shaped upper side wall and an inwardly tapered lower side wall that extends downward towards the semiconductor substrate. The second interlayer insulating layer is formed over first interlayer insulating layer such that the second interlayer insulating layer includes a hole that exposes a top surface and a peripheral portion of the bulbous shaped upper side wall of the contact plug. The copper contact pad is buried within the hole so that the exposed parts of the bulbous shaped upper side wall of the contact plug protrude into the copper contact pad. | 11-25-2010 |
| 20100301493 | PACKAGED ELECTRONIC DEVICES HAVNG DIE ATTACH REGIONS WITH SELECTIVE THIN DIELECTRIC LAYER - A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is>a thickness of the first dielectric layer by at least 5 μm. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region. | 12-02-2010 |
| 20100301494 | RE-ESTABLISHING A HYDROPHOBIC SURFACE OF SENSITIVE LOW-K DIELECTRICS IN MICROSTRUCTURE DEVICES - Silicon oxide based low-k dielectric materials may be provided with a hydrophobic low-k surface area, even after exposure to a reactive process ambient, by performing a surface treatment on the basis of hexamethylcyclotrisilazane and/or octamethylcyclotetrasilazane. In addition to the surface treatment, a polymerization may be initiated on the basis of a hydrophobic surface nature of the silicon-based dielectric material, thereby increasing the chemical stability during the further processing. | 12-02-2010 |
| 20100301495 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Provided is the method for manufacturing the semiconductor device including: providing a film (organic silicon polymer film) containing a silane compound and a porogen on a substrate; providing a hole (interconnect trench) in the organic silicon polymer film using a selective etching process and providing a metallic film (barrier film and copper interconnect) in the inside of the interconnect trench; and conducting a radiation with ultraviolet over the organic silicon polymer film within an atmosphere of a reducing gas while the film is heated at a temperature of not lower than a boiling point or a decomposition temperature of the porogen to obtain a microporous film. | 12-02-2010 |
| 20100308469 | METHOD AND APPARATUS OF FORMING A VIA - The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line. | 12-09-2010 |
| 20100308470 | SEMICONDUCTOR DEVICE AND INDUCTOR - A semiconductor device and an inductor are provided. The semiconductor device includes a top level interconnect metal layer (M | 12-09-2010 |
| 20100308471 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electronic device includes: a first substrate; and a second substrate on which the first substrate is mounted and which is electrically connected to the first substrate in at least one predetermined area. The predetermined area includes at least two through vias running through the first substrate, and an interconnect provided in the second substrate. The at least two through vias are electrically connected together via the interconnect. | 12-09-2010 |
| 20100314775 | EXPLOSION-PROOF MODULE STRUCTURE FOR POWER COMPONENTS, PARTICULARLY POWER SEMICONDUCTOR COMPONENTS, AND PRODUCTION THEREOF - A power module having at least one electric power component, such as a power electronic semiconductor component. An electrical contact for a load current is formed on a lower surface and also on an upper surface of the power semiconductor component. To reduce an explosion pressure and accept power when the power electronic semiconductor component is overloaded, a hollow space filled with at least one electrically conducting particle is formed on an electrical contact surface of the electrical contact. In case of a short circuit, an arc is initially generated above the semiconductor element thickness of the power semiconductor component, whereupon the filling in the hollow space takes over current conduction. Preferably, the filling in the hollow space is a plurality of spherical electrically conducting particles. The explosion pressure can escape into interstices in the filling if there is a short circuit. Furthermore, metal vapors are cooled and are condensed. A duct extending from and out of the hollow space can additionally be provided to reduce the explosion pressure, thus preventing power components from demolishing the surroundings during an electrical overload. The foregoing power module may be an improved thyristor. | 12-16-2010 |
| 20100314776 | CONNECTION PAD STRUCTURE FOR AN IMAGE SENSOR ON A THINNED SUBSTRATE - The invention relates to the fabrication of electronic circuits on a thinned semiconductor substrate. To produce a connection pad on the back side of the thinned substrate, the procedure is as follows: an integrated circuit is produced on an unthinned substrate, in which a portion of a polycrystalline silicon layer ( | 12-16-2010 |
| 20100314777 | Semiconductor device and method for manufacturing same - A semiconductor device includes: a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; an interconnect (second interconnect trench) composed of a metallic film provided in an interconnect trench (second copper interconnect) and a plug composed of a metallic film provided in a connection hole (via hole) coupled to the second interconnect trench, both of which are provided in the interlayer insulating film; a first sidewall provided on a side surface of the via hole; and a second sidewall provided on a side surface of the second interconnect trench, and a thickness of the first sidewall in vicinity of a bottom of the side surface of the via hole is larger than a thickness of the second sidewall in vicinity of a bottom of the second interconnect trench. | 12-16-2010 |
| 20100314778 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In forming a semiconductor device, an insulation layer is formed on top of a semiconductor chip having a plurality of external terminals. A plurality of interconnections is formed on the insulating layer. External terminals are electrically connected to coordinated interconnections through a plurality of vias formed in the insulation layer. The interconnections are each formed integral with a via conduction part which covers the entire surfaces of the bottom and the sidewall sections of the via. The interconnection is formed so as to be narrower in its region overlying the via than the upper via diameter. | 12-16-2010 |
| 20100320616 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device comprises forming an insulating layer on a semiconductor substrate, etching the insulating layer to form contact regions, forming a conductive layer on an entire surface including the contact regions, and spiking the conductive layer in the semiconductor substrate. | 12-23-2010 |
| 20100320617 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER - Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure. | 12-23-2010 |
| 20100320618 | INTERCONNECTION SUBSTRATE, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD OF SEMICONDUCTOR DEVICE - An interconnection substrate including: a first insulating film made of a silicon compound, an adhesion enhancing layer formed on the first insulating film, and a second insulting film made of a silicon compound and formed on the adhesion enhancing layer, wherein the first insulating film and the second insulating film are combined together with a component having a structure represented by General Formula (1) described below: | 12-23-2010 |
| 20110001247 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method comprises bonding a semiconductor element onto one surface of a first protective film via an adhesive layer, an electrode being formed in the semiconductor element, the first protective film being disposed on a first base material and including a first via hole, removing the first base material from the first protective film, applying first laser light to the adhesive layer through the first via hole to form a second via hole in the adhesive layer so that the electrode is exposed through the adhesive layer, and forming a metal layer in the second via hole to connect the metal layer to the electrode. | 01-06-2011 |
| 20110001248 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 01-06-2011 |
| 20110006436 | Conductive Via Plug Formation - Various embodiments of the present invention are generally directed to a method of forming a conductive via plug in a semiconductor device. A first and second metal layer are electrically connected by a via plug that is formed by depositing a tungsten seed layer on a plurality of metal barrier layers within a recess using atomic layer deposition. The recess is then filled with tungsten using chemical vapor deposition. | 01-13-2011 |
| 20110006437 | OPENING STRUCTURE - An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings. | 01-13-2011 |
| 20110006438 | SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE FORMED THEREFROM - A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has other interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film. | 01-13-2011 |
| 20110006439 | SEMICONDUCTOR DEVICE, BASIC CELL, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A first wiring ( | 01-13-2011 |
| 20110012268 | SEMICONDUCTOR DEVICE - After opening a via hole, the bottom portion and the top portion are rounded by etching performed twice. As a result, resistance of the via hole can be reduced and its quality and life can be enhanced. | 01-20-2011 |
| 20110012269 | ELECTRONIC COMPONENT USED FOR WIRING AND METHOD FOR MANUFACTURING THE SAME - A wiring electronic component of the present invention is incorporated into an electronic device package in which a circuit element including a semiconductor chip is disposed and in which the circuit element is connected to a wiring pattern on the back face and also connected, via vertical wiring, to external electrodes located on the front face opposite the wiring pattern. The wiring electronic component is composed of an electrically conductive support portion, which serves as an electroforming mother die, and a plurality of vertical wiring portions formed through electroforming such that they are integrally connected to the support portion. | 01-20-2011 |
| 20110018138 | NANO-INTERCONNECTS FOR ATOMIC AND MOLECULAR SCALE CIRCUITS - A method for forming interconnects in a substrate, the substrate comprising a semiconductor layer on an oxide layer forming a silicon-on-oxide substrate, the method comprising forming a plurality of holes into the substrate to the semiconductor layer, and metalizing the plurality of holes to form the interconnects. | 01-27-2011 |
| 20110018139 | SCALLOPED TUBULAR ELECTRIC VIA - A via connecting the front surface of a substrate to its rear surface and having, in cross-section in a plane parallel to the surfaces, the shape of a scalloped ring. | 01-27-2011 |
| 20110018140 | ELECTRIC VIA COMPRISING LATERAL OUTGROWTHS - A via connecting the front surface of a substrate to its rear surface, this substrate including a porous region extending from at least a portion of the periphery of the via, the via including outgrowths extending in pores of the porous region. | 01-27-2011 |
| 20110018141 | WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE - A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the second plug is adjacent to the first plug. A second insulation layer is located on the first insulation layer, the first plug and the second plug. A bit line structure is located on the second insulation layer and is electrically connected to the first plug. A protection spacer is located on the recess of the first plug and a sidewall of an opening in the second insulation layer. The opening exposes the recess of the first plug, the second plug and the sidewall of the bit line structure. A pad is located in the opening and contacts the second plug. | 01-27-2011 |
| 20110024914 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE COMPRISING AN INTER-DIE CONNECTION ON THE BASIS OF FUNCTIONAL MOLECULES - In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips. | 02-03-2011 |
| 20110024915 | SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole. | 02-03-2011 |
| 20110024916 | Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias - A semiconductor device has a carrier for supporting the semiconductor device. A first semiconductor die is mounted over the carrier. A first dummy die having a first through-silicon via (TSV) is mounted over the carrier. The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. The carrier is removed. A first redistribution layer (RDL) is formed over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die. An insulation layer is formed over the first RDL. A second RDL is formed over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV. A semiconductor package is connected to the second RDL. | 02-03-2011 |
| 20110031630 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes: stacking a plurality of electrode layers containing a semiconductor alternately with insulating layers; processing part of a multilayer body of the electrode layers and the insulating layers into a staircase shape and exposing a surface of the staircase-shaped electrode layers; forming a metal film in contact with the exposed electrode layers; reacting the semiconductor of the electrode layers with the metal film to form a metal compound in at least a portion of the electrode layers in contact with the metal film; removing an unreacted portion of the metal film; forming an interlayer insulating layer covering the staircase-shaped electrode layers after removing the unreacted portion of the metal film; forming a plurality of contact holes piercing the interlayer insulating layer, each of the contact holes reaching the metal compound of the electrode layer at a corresponding stage; and providing a plurality of contact electrodes inside the contact holes. | 02-10-2011 |
| 20110031631 | PHOTOSENSITIVE ADHESIVE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device | 02-10-2011 |
| 20110031632 | DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET - A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die. | 02-10-2011 |
| 20110042820 | 3D SILICON-SILICON DIE STACK STRUCTURE AND METHOD FOR FINE PITCH INTERCONNECTION AND VERTICAL HEAT TRANSPORT - A method of fabricating a thin wafer die includes creating circuits and front-end-of-line wiring on a silicon wafer, drilling holes in a topside of the wafer, depositing an insulator on the drilled holes surface to provide a dielectric insulator, removing any excess surface deposition from the surface, putting a metal fill into the holes to form through-silicon-vias (TSV), creating back-end-of-line wiring and pads on the top surface for interconnection, thinning down the wafer to expose the insulator in from the TSVs to adapt the TSVs to be contacted from a backside of the wafer, depositing an insulating layer which contacts the TSV dielectric, thinning down the backside of the wafer, opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon, and depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer to form an integrated circuit. | 02-24-2011 |
| 20110042821 | VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES - Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions. | 02-24-2011 |
| 20110042822 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a GaAs substrate having a first major surface and a second major surface opposite to each other; a first metal layer composed of at least one of Pd, Ta, and Mo on the first major surface of the GaAs substrate; and a second metal layer composed of a Ni alloy or Ni on the first metal layer. | 02-24-2011 |
| 20110042823 | INTERPOSER CHIP AND MANUFACTURING METHOD THEREOF - The interposer chip includes a chip mounting region on which a semiconductor chip is mounted via a fixing material made of resin. The interposer chip has an insulator film, and wiring layers formed on the insulator film. At a position corresponding to a rim of the chip mounting region, a reinforcing region in which an adhesive force between the insulator film and the wiring layers are increased is provided. | 02-24-2011 |
| 20110042824 | MULTI-CHIP MODULE AND METHOD OF MANUFACTURING THE SAME - A multi-chip module includes a package board, a plurality of chips, and a wiring board. The plurality of chips are horizontally disposed on the package board. The plurality of chips are electrically connected with the package board, and respectively provided with via holes which penetrate through the plurality of chips. The plurality of chips are respectively provided with circuits at surfaces facing the package board. The wiring board is disposed on an opposite side to the package board across the plurality of chips. The wiring board includes a wiring pattern which is electrically connecting adjacent chips one another. The circuit is electrically connected to the wiring pattern through the via holes. | 02-24-2011 |
| 20110042825 | SEMICONDUCTOR DEVICE - In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI | 02-24-2011 |
| 20110042826 | SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER - The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO | 02-24-2011 |
| 20110042827 | BONDING STRUCTURES AND METHODS OF FORMING BONDING STRUCTURES - A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening. | 02-24-2011 |
| 20110042828 | WIRING BOARD, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A wiring board ( | 02-24-2011 |
| 20110057321 | 3-D MULTI-WAFER STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A 3-D multi-wafer stacked semiconductor structure and method for manufacturing the same. The method comprises steps of: providing a first wafer, a first circuit layer being formed on a surface thereof; bonding the first circuit layer with a carrier; performing a first thinning process on the first wafer; forming a first mask on the other surface of the thinned first wafer; providing a second wafer, a second circuit layer being formed on a surface thereof; bonding the second circuit layer with the first mask; and forming at least a through via filled with a conductor to electrically connect a first connecting pad on the first circuit layer and a second connecting pad on the second circuit layer. | 03-10-2011 |
| 20110057322 | CARBON NANOTUBE INTERCONNECT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a carbon nanotube interconnect includes a first interconnection layer, an interlayer dielectric film, a second interconnection layer, a contact hole, a plurality of carbon nanotubes and a film. The interlayer dielectric film is formed on the first interconnection layer. The second interconnection layer is formed on the interlayer dielectric film. The contact hole is formed in the interlayer dielectric film between the first interconnection layer and the second interconnection layer. The carbon nanotubes are formed in the contact hole. The carbon nanotubes have a first end connected to the first interconnection layer and a second end connected to the second interconnection layer. The film is formed between the interlayer dielectric film and the second interconnection layer. The film has a portion filled between the second ends of the carbon nanotubes. | 03-10-2011 |
| 20110057323 | PACKAGING STRUCTURE HAVING EMBEDDED SEMICONDUCTOR ELEMENT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening region predefined on the first surface; forming a first metallic frame around the periphery of the predefined opening region on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. The invention can precisely control the shape of the opening through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate. | 03-10-2011 |
| 20110057324 | Structure And Method Of Making Interconnect Element Having Metal Traces Embedded In Surface Of Dielectric - An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns. | 03-10-2011 |
| 20110057325 | CHIP-SIZE DOUBLE SIDE CONNECTION PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection. | 03-10-2011 |
| 20110057326 | METHOD FOR FORMING THROUGH ELECTRODE AND SEMICONDUCTOR DEVICE - An electrode on a first surface of a semiconductor substrate and a second surface of the semiconductor substrate are connected with each other by a through electrode. A through hole is formed through the semiconductor substrate from the second surface of the semiconductor substrate to an interlayer insulating film on the first surface, and an insulating film is formed on a side surface and a bottom surface of the through hole as well as on the second surface of the semiconductor substrate, so that by simultaneously etching the insulating film on the bottom surface of the through hole and the interlayer insulating film, thus formed, the through hole is formed so as to reach the electrode on the first surface of the semiconductor substrate. | 03-10-2011 |
| 20110062592 | Delamination Resistance of Stacked Dies in Die Saw - An integrated circuit structure includes a first die including TSVs; a second die over and bonded to the first die, with the first die having a surface facing the second die; and a molding compound including a portion over the first die and the second die. The molding compound contacts the surface of the second die. Further, the molding compound includes a portion extending below the surface of the second die. | 03-17-2011 |
| 20110062593 | SEMICONDUCTOR PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE - A semiconductor packaging substrate with a plurality of pads arranged in a square grid pattern thereon, in which among the pads, two pads obliquely adjacent to each other are connected with through-holes respectively and another through-hole is provided between the through-holes connected with the two pads obliquely adjacent to each other. | 03-17-2011 |
| 20110062594 | THROUGH HOLE ELECTRODE SUBSTRATE, METHOD FOR MANUFACTURING THE THROUGH HOLE ELECTRODE SUBSTRATE, AND SEMICONDUCTOR DEVICE USING THE THROUGH HOLE ELECTRODE SUBSTRATE - To provide a through hole electrode substrate and a semiconductor device which uses the through hole electrode substrate which have improved electrical properties in a conductive part which passes through the front and back of a substrate, a through hole electrode substrate | 03-17-2011 |
| 20110068475 | SEMICONDUCTOR DEVICE WITH LOW RESISTANCE BACK-SIDE COUPLING - Electronic elements ( | 03-24-2011 |
| 20110068476 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad. | 03-24-2011 |
| 20110068477 | THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE - A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture. | 03-24-2011 |
| 20110068478 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate. | 03-24-2011 |
| 20110074039 | RELIABLE INTERCONNECT FOR SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material. | 03-31-2011 |
| 20110074040 | Semiconductor Device And Method For Making Same - One or more embodiments may relate to a method for making a semiconductor structure, the method including: forming an opening at least partially through a workpiece; and forming an enclosed cavity within the opening, the forming the cavity comprising forming a paste within the opening. | 03-31-2011 |
| 20110074041 | Circuit Board with Oval Micro Via - Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor structure. A first via is formed in the first interconnect layer and in electrical contact with the first conductor structure. The first via has a first oval footprint. | 03-31-2011 |
| 20110074042 | ELECTRONIC DEVICE - The electronic device includes the substrate, the electronic component mounted on a main surface of the substrate, a plurality of external terminals formed on a back surface of the substrate, and a plurality of interconnects formed on the back surface of the substrate, wherein the plurality of interconnects includes a first interconnect disposed so as to overlap with an outer edge of the electronic component in a plan view. A pitch between a first external terminal and a second external terminal, adjacent to each other in one direction with the first interconnect located therebetween, is wider than a pitch between a third external terminal and a fourth external terminal, adjacent to each other in the same direction without the first interconnect located therebetween. | 03-31-2011 |
| 20110074043 | METHOD OF FORMING VIAS IN SEMICONDUCTOR SUBSTRATES AND RESULTING STRUCTURES - Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via. | 03-31-2011 |
| 20110079916 | ELECTRONIC ASSEMBLIES INCLUDING MECHANICALLY SECURED PROTRUDING BONDING CONDUCTOR JOINTS - An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces. | 04-07-2011 |
| 20110079917 | Interposer structure with passive component and method for fabricating same - According to an exemplary embodiment, an interposer structure for electrically coupling a semiconductor die to a support substrate in a semiconductor package includes at least one through-wafer via extending through a semiconductor substrate, where the at least one through-wafer via provides an electrical connection between the semiconductor die and the support substrate. The interposer structure further includes a passive component including a trench conductor, where the trench conductor extends through the semiconductor substrate. The passive component further includes a dielectric liner situated between the trench conductor and the semiconductor substrate. The passive component can further include at least one conductive pad for electrically coupling the trench conductor to the semiconductor die. The passive component can be, for example, an inductor or an antenna. | 04-07-2011 |
| 20110079918 | PLASMA-BASED ORGANIC MASK REMOVAL WITH SILICON FLUORIDE - Removal of organic mask material from an etched dielectric film with an etchant gas mixture including silicon fluoride (SiF | 04-07-2011 |
| 20110079919 | ELECTRICAL CONNECTION VIA FOR THE SUBSTRATE OF A SEMICONDUCTOR DEVICE - An electrical connection via passing through a substrate for a semiconductor device is made of at least one conducting ring formed in an annular hole passing through the substrate. | 04-07-2011 |
| 20110079920 | ELECTRICAL CONNECTION VIA FOR THE SUBSTRATE OF A SEMICONDUCTOR DEVICE - An electrical connection via is formed through a substrate to make an electrical connection from one face of the substrate to the other. The via includes a ring made of an electrically conductive material. The ring is formed in a hole in the substrate so as to at least partly form the via. | 04-07-2011 |
| 20110079921 | GENERATION OF METAL HOLES BY VIA MUTATION - A semiconductor interconnect architecture provides a reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) without degradation of the product yield or robustness, or increases copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs. | 04-07-2011 |
| 20110084397 | 3D INTEGRATED CIRCUIT LAYER INTERCONNECT - A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided. | 04-14-2011 |
| 20110084398 | SEMICONDUCTOR DEVICE COMPRISING AN ELECTROMAGNETIC WAVEGUIDE - A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates. | 04-14-2011 |
| 20110084399 | SEMICONDUCTOR DEVICE - A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern. | 04-14-2011 |
| 20110084400 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a substrate, at least one via hole provided on the substrate, a through silicon via provided in the at least one via hole, and an interface chip that is electrically connected to the core chips through the through silicon via. The via hole includes a bowing shaped portion in which a diameter of a center portion is larger than diameters of both edges. | 04-14-2011 |
| 20110084401 | PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates. | 04-14-2011 |
| 20110084402 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES - Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. | 04-14-2011 |
| 20110089570 | Multi-Layer Connection Cell - A semiconductor multi-layer connection cell is disclosed that includes configuration layers and “via” layers disposed between the configuration layers to allow configuration of signals at any layer in the connection cell. The layers include column structures extending through the layers. Each column structure includes a hole in a layer that can be filled to form an electrical connection between layers. | 04-21-2011 |
| 20110089571 | SEMICONDUCTOR DEVICE, CIRCUIT SUBSTRATE, AND ELECTRONIC DEVICE - A semiconductor device has a through electrode formed in a through hole which penetrates a Si substrate from one surface to the other surface of the Si substrate, wherein a rectangular electrode pad is provided on the other surface with an insulation film laid between the electrode pad and the other surface, an opening of the through hole on the one surface side is circular, an opening of the through hole on the other surface side is rectangular, and the area of the opening on the other surface side is made smaller than the area of the opening on the one surface side. | 04-21-2011 |
| 20110089572 | METHOD FOR FABRICATING THROUGH SUBSTRATE VIAS - A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips. | 04-21-2011 |
| 20110089573 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first interposer provided with a first chip first interconnection; a first chip arranged to contact the first interposer in one surface of the first chip; a second interposer arranged to contact the other surface of the first chip and provided with a first chip second interconnection; and a second chip group mounted on the second interposer. The first chip has a circuit forming surface on which a circuit element is formed, as one of the surfaces of the first chip, and the first chip first interconnection and the first chip second interconnection are electrically connected with the circuit element. A through electrode is formed to pass from the one of the surfaces of the first chip to the other surface, and one of the first chip first interconnection and the first chip second interconnection is electrically connected with the circuit element through the through electrode. | 04-21-2011 |
| 20110089574 | SEMICONDUCTOR DEVICE - A semiconductor device having a multilayer interconnect structure allowing heat in an interconnect layer at an intermediate level to be effectively dissipated is provided. A lower-layer interconnect ( | 04-21-2011 |
| 20110095435 | COAXIAL THROUGH-SILICON VIA - A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described. | 04-28-2011 |
| 20110095436 | THROUGH SILICON VIA WITH DUMMY STRUCTURE AND METHOD FOR FORMING THE SAME - A through silicon via structure includes a top pad and a vertical conductive post that is connected to the top pad. The top pad covers a wider area than the cross section of the vertical conductive post. An interconnect pad is formed at least partially below the top pad. An under layer is also formed at least partially below the top pad. At least one dummy structure connects the top pad and the under layer to fasten the top pad and the interconnect pad. | 04-28-2011 |
| 20110095437 | INTERFACE PLATE BETWEEN INTEGRATED CIRCUITS - An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple. | 04-28-2011 |
| 20110095438 | METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING - The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed. | 04-28-2011 |
| 20110095439 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THROUGH SEMICONDUCTOR VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: providing a package substrate; mounting a first integrated circuit die, having through silicon vias, on the package substrate; coupling cylindrical studs to the package substrate adjacent to the first integrated circuit die; and mounting a second integrated circuit die, having through silicon vias, on the first integrated circuit die and the cylindrical studs for forming an electrical connection among the second integrated circuit die, the first integrated circuit die, the package substrate, or a combination thereof. | 04-28-2011 |
| 20110101537 | HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION - Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions. | 05-05-2011 |
| 20110101538 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 05-05-2011 |
| 20110101539 | Semiconductor device and manufacturing method of semiconductor device - Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal. | 05-05-2011 |
| 20110101540 | INTEGRATED CHIP CARRIER WITH COMPLIANT INTERCONNECTS - A silicon chip includes a silicon substrate, a plurality of pads, and a plurality of through vias to connect back-end-of-line wiring to the plurality of pads. The silicon substrate includes a layer of active devices and the back-end-of-line wiring connected to the active devices. | 05-05-2011 |
| 20110101541 | SEMICONDUCTOR DEVICE - A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device | 05-05-2011 |
| 20110108994 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer. | 05-12-2011 |
| 20110115094 | STRUCTURES AND METHODS FOR PHOTO-PATTERNABLE LOW-k (PPLK) INTEGRATION - A single damascene or dual damascene interconnect structure fabricated with a photo-patternable low-k dielectric (PPLK) which is cured after etching. This interconnect method prevents the PPLK damage and the tapering of the edges of the interconnect structure. In one embodiment, the method of the present invention includes depositing a photo-patternable low-k (PPLK) material atop an initial structure. The initial structure can include a dielectric cap, an antireflective coating (ARC), or a material stack including the same. The at least one PPLK material is patterned, creating a single damascene structure. For dual damascene structures, a second PPLK layer is coated and patterned. An etch process is performed to transfer the pattern for the PPLK material into at least a portion of the substrate, typically into the dielectric cap and/or ARC using processes known by those skilled in the art (typically fluorocarbon-based plasmas). A diffusion liner deposition can follow the etch process. An electrically conductive material can also be deposited. The diffusion liner and the electrically conductive material can be polished using chemical mechanical polishing. The resulting structure is cured anytime after etching order to transform the resist like PPLK into a permanent low-k material that remains within the structure. | 05-19-2011 |
| 20110115095 | METHOD FOR MANUFACTURING A PLURALITY OF THIN CHIPS AND CORRESPONDINGLY MANUFACTURED THIN CHIP - In a method is for producing through contacts in thin chips, whose functionality is implemented in a layer structure starting from the surface layer of a semiconductor substrate, to separate these chips, the surface layer is structured using the layer structure and at least one cavity is produced below the surface layer, so that the individual chips are defined by trenches opening into the cavity and the individual chips are connected via support elements in the area of the cavity to the substrate below the cavity. The chips are provided with through contacts, in that firstly a contact hole, which extends through the entire layer structure of the chip and opens into a support element, is produced for each through contact. At least one dielectric layer is applied to the thus structured layer structure and in particular to the wall of the contact holes and structured in accordance with the electrical connections to be created between areas of the chip surface and at least one through contact. A metal plating, which extends in particular to the wall of the contact holes and the surface areas of the layer structure which adjoin the contact holes, is applied thereon and structured. Finally, the contact holes which are thus metal-plated are also filled using a solder. | 05-19-2011 |
| 20110115096 | ELECTRODEPOSITING A METAL IN INTEGRATED CIRCUIT APPLICATIONS - A method is described in which a contact hole to an interconnect in an insulating layer is fabricated. A barrier layer is subsequently applied. Afterward, a photoresist layer is applied, irradiated and developed. With the aid of a galvanic method, a copper contact is then produced in the contact hole. Either the barrier layer or an additional boundary electrode layer serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production. | 05-19-2011 |
| 20110115097 | AREA EFFICIENT THROUGH-HOLE CONNECTIONS - Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection. | 05-19-2011 |
| 20110121462 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor chip includes a semiconductor chip body, a through-silicon via and a silicon pattern. The semiconductor chip body has a first surface and a second surface facing away from the first surface. The through-silicon via is formed to pass through the semiconductor chip body and has a metal layer and an insulation layer which protrude from the second surface. The silicon pattern is formed on a sidewall of the protruding through-silicon via. | 05-26-2011 |
| 20110121463 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE AND METHODS OF THE SAME - According to one embodiment, a semiconductor package is disclosed. The semiconductor package can include an insulative substrate having a first surface and a second surface opposed to the first surface, a first through hole formed in the insulative substrate from the first surface to the second surface, and a second through hole formed near the first through hole in the insulative substrate from the first surface to the second surface, a conductive body formed in the vicinity of the second through hole and penetrating into the insulative substrate, a first outer electrode formed on the first surface and connected to an one end of the conductive body, and a second outer electrode formed on the second surface and connected to the other end of the conductive body. | 05-26-2011 |
| 20110127679 | Stacked Structure of Semiconductor Packages Including Through-Silicon Via and Inter-Package Connector, and Method of Fabricating the Same - A stacked structure of semiconductor packages includes an upper semiconductor package, a lower semiconductor package and inter-package connectors. The upper semiconductor package includes an upper package substrate, a plurality of upper semiconductor chips stacked on the upper package substrate, and conductive upper connection lands formed on a bottom surface of the upper package substrate. The lower semiconductor package includes a lower package substrate, a plurality of lower semiconductor chips stacked on the lower package substrate, and lower through-silicon vias vertically penetrating the lower semiconductor chips. The inter-package connectors may electrically connect the through-silicon vias to the upper connection lands. | 06-02-2011 |
| 20110133342 | WIRING BOARD, MANUFACTURING METHOD OF THE WIRING BOARD, AND SEMICONDUCTOR PACKAGE - A wiring board includes a ceramic substrate including a plurality of stacked ceramic layers, an internal wiring, and an electrode, the internal wiring being electrically connected to the electrode, the electrode being exposed from a first surface of the ceramic substrate; and a silicon substrate including a wiring layer, the wiring layer including a wiring pattern and a via-fill, the wiring pattern being formed on a main surface of the silicon substrate, an end of the via-fill being electrically connected to the wiring pattern, another end of the via-fill being exposed from a rear surface of the silicon substrate positioned opposite to the main surface, wherein the rear surface of the silicon substrate is anodically bonded to the first surface of the ceramic substrate; and the via-fill of the silicon substrate is directly connected to the electrode of the ceramic substrate. | 06-09-2011 |
| 20110133343 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: a semiconductor substrate having a through hole formed towards one surface side from the other surface side; an electrode pad arranged on the one surface side of the semiconductor substrate and partially exposed to the through hole; and a through electrode arranged at an inner side of the through hole and electrically connected to the electrode pad, wherein a connection portion between the electrode pad and the through electrode is arranged in a region within a plane of the electrode pad which is close to the center of the semiconductor substrate rather than to a center of the electrode pad. | 06-09-2011 |
| 20110140279 | SEMICONDUCTOR STRUCTURE INCORPORATING MULTIPLE NITRIDE LAYERS TO IMPROVE THERMAL DISSIPATION AWAY FROM A DEVICE AND A METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are embodiments of a method of forming such a semiconductor structure in conjunction with the formation of any of the following nitride layers during standard processing of other devices: a nitride hardmask layer (OP layer), a “sacrificial” nitride layer (SMT layer), a tensile nitride layer (WN layer) and/or a compressive nitride layer (WP layer). Optionally, the embodiments also incorporate incomplete contacts that extend through the blanket oxide layer into one or more of the nitride layers without contacting the device in order to further improve heat dissipation | 06-16-2011 |
| 20110140280 | Semiconductor apparatus capable of error revision using pin extension technique and design method therefor - A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension. | 06-16-2011 |
| 20110140281 | SUBSTRATE FOR ELECTRONIC DEVICE, STACK FOR ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an electronic device, including a step of aligning and stacking a plurality of substrates, each of the plurality of substrates having a plurality of vertical conductors and magnetic films, the vertical conductors being directed along a thickness direction of the substrate and distributed in a row with respect to a substrate surface, the magnetic films being disposed in place on the substrate surface in a predetermined positional relationship with the vertical conductors, upon aligning the plurality of substrates, the electronic device manufacturing method including a step of applying an external magnetic field to produce a magnetic attractive force between the magnetic films of adjacent stacked substrates and align the vertical conductors by the magnetic attractive force. | 06-16-2011 |
| 20110140282 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes: a semiconductor substrate, first and second internal electrodes provided on a surface of the semiconductor substrate; a first through electrode which penetrates through the semiconductor substrate in a thickness direction and is electrically connected to the first internal electrode; and a second through electrode connected to the second internal electrode, and the second internal electrode is thinner than the first internal electrode. The second through electrode may penetrate through the second internal electrode. | 06-16-2011 |
| 20110147944 | PLANARISING DAMASCENE STRUCTURES - Manufacturing a damascene structure involves: forming a sacrificial layer ( | 06-23-2011 |
| 20110147945 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING GENERATION OF CRACKS IN SEMICONDUCTOR CHIP DURING MANUFACTURING PROCESS - A semiconductor device includes a chip stacked body where a plurality of semiconductor chips are stacked, and penetration electrodes respectively formed in the semiconductor chips are electrically interconnected in stacking order of the semiconductor chips, a first support member that is disposed to face a first semiconductor chip formed in one end of the chip stacked body, and including electrodes electrically connected to the penetration electrodes of the first semiconductor chip, and a wiring board that is disposed to face a second semiconductor chip formed in an end opposed to the one end of the chip stacked body, and including external electrodes on a surface opposed to a surface facing the second semiconductor chip that is to be electrically connected to the penetration electrodes of the second semiconductor chip. | 06-23-2011 |
| 20110147946 | WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME - A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern. | 06-23-2011 |
| 20110147947 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an ELK film formed on a semiconductor substrate, a SiN film formed on the ELK film, and a plurality of interconnects formed in the ELK film and the SiN film to be located substantially at an equal height. The plurality of interconnects are provided in a non-dense interconnect region having a first interconnect area ratio which indicates a ratio of an area occupied by the interconnects per unit area, and a dense interconnect region having a second interconnect area ratio which is higher than the first interconnect area ratio. A height of an upper surface of a part of the SiN film located in the dense interconnect region is lower than a height of an upper surface of a part of the SiN film located in the non-dense interconnect region. | 06-23-2011 |
| 20110147948 | FORMING METHOD AND STRUCTURE OF POROUS LOW-K LAYER, INTERCONNECT PROCESS AND INTERCONNECT STRUCTURE - A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer. | 06-23-2011 |
| 20110156267 | Semiconductor Process, Semiconductor Element and Package Having Semiconductor Element - The present invention relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one through via structure. The base material has a first surface, a second surface, at least one groove and at least one foundation. The groove opens at the first surface, and the foundation is disposed on the first surface. The through via structure is disposed in the groove of the base material, and protrudes from the first surface of the base material. The foundation surrounds the through via structure. Whereby, the foundation increases the strength of the through via structure, and prevents the through via structure from cracking. | 06-30-2011 |
| 20110156268 | Semiconductor Process, Semiconductor Element and Package Having Semiconductor Element - The present invention relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor process includes the following steps: (a) providing a semiconductor element including a silicon base material and at least one conductive via structure disposed in the silicon base material; (b) removing part of the silicon base material to form a first surface, wherein the conductive via structure protrudes from the first surface of the silicon base material so as to form a through via structure; (c) forming a protective layer on the first surface of the silicon base material to cover the through via structure, wherein the protective layer is made of photo-sensitive material; (d) removing part of the protective layer to form a first surface, so as to expose the through via structure on the first surface of the protective layer. Whereby, the protective layer disposed on the through via structure is totally removed, so that the yield rate of electrically connecting the through via structure and external elements is ensured. | 06-30-2011 |
| 20110156269 | SEMICONDUCTOR PACKAGE AND STACK SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a semiconductor chip having a first region defined at a center portion of a first surface of the semiconductor chip, and having second and third regions defined on both sides of the first region, respectively. Bonding pads are disposed in the first region and a substrate having a substrate body is disposed in the second region of the semiconductor chip. The substrate includes an extension portion projecting away from the semiconductor chip. The substrate also includes circuit patterns disposed on the substrate body having a first ends placed adjacent to the bonding pads and second ends placed on the extension portion. Connection members electrically connect the first ends of the circuit patterns and the bonding pads. | 06-30-2011 |
| 20110156270 | CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES FORMED ON THE BASIS OF A PARTIALLY APPLIED ACTIVATION LAYER - When forming contact levels of sophisticated semiconductor devices, a superior bottom to top fill behavior may be accomplished by applying an activation material selectively in the lower part of the contact openings and using a selective deposition technique. Consequently, deposition-related irregularities, such as voids, may be efficiently suppressed even for high aspect ratio contact openings. | 06-30-2011 |
| 20110156271 | SEMICONDUCTOR MODULE - A semiconductor module having a second semiconductor package | 06-30-2011 |
| 20110156272 | Multilayered Wiring Substrate - A multilayered wiring substrate, comprising: a plurality of first main surface side connecting terminals arranged in a first main surface of a stack structure; and a plurality of second main surface side connecting terminals being arranged in a second main surface of the stack structure; wherein a plurality of conductor layers are alternately formed in a plurality of stacked resin insulation layers and are operably connected to each other through via conductors tapered such that diameters thereof are widened toward the first or the second main surface, wherein a plurality of openings are formed in an exposed outermost resin insulation layer in the second main surface, and terminal outer surfaces of the second main surface side connecting terminals arranged to match with the plurality of the openings are positioned inwardly from an outer main surface of the exposed outermost resin insulation layer, and edges of terminal inner surfaces are rounded. | 06-30-2011 |
| 20110156273 | CIRCUIT SUBSTRATE AND METHOD - Embodiments of the invention are concerned with semiconductor circuit substrates for use in a radiation detection device, said radiation detection device comprising a detector substrate having a plurality of detector cells arranged to generate charge in response to incident radiation, each of said detector cells including at least one detector cell contact for coupling charge from said detector cell to said semiconductor circuit substrate. More particularly, in embodiments of the invention the semiconductor circuit substrate comprises: a plurality of cell circuit contacts, each of which is configured to receive charge from a corresponding detector cell contact, cell circuitry associated with said plurality of cell circuit contacts; one or more conductive pathways arranged to carry at least one of control, readout and power supply signals to and/or from said cell circuitry; and one or more signal pathways extending through said semiconductor circuit substrate, said one or more signal pathways being electrically coupled to said conductive pathways so as to provide an external signal interface for said cell circuitry. Embodiments in accordance with the present invention thus provide a means of routing signals through the semiconductor circuit substrate to an electrical contact on a surface of the semiconductor circuit substrate. The electrical contact on the surface of the circuit substrate can then be directly coupled to a corresponding electrical contact on a mount. | 06-30-2011 |
| 20110163457 | INTEGRATED CIRCUIT MICRO-MODULE - One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna. | 07-07-2011 |
| 20110169170 | SEMICONDUCTOR DEVICE - This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate. | 07-14-2011 |
| 20110169171 | Dual Interconnection in Stacked Memory and Controller Module - A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package. | 07-14-2011 |
| 20110169172 | Semiconductor Device having dual damascene structure - A semiconductor device, includes a semiconductor substrate, a first wiring layer formed on the semiconductor substrate, the first wiring layer containing a first via having a first aspect ratio and a first wire having a second aspect ratio, the first aspect ratio being equal to or larger than the second aspect ratio, and a second wiring layer overlying the first wiring layer, the second wiring layer containing a second via having a third aspect ratio and a second wire having a fourth aspect ratio, the third aspect ratio being smaller than the fourth aspect ratio. | 07-14-2011 |
| 20110175232 | SEMICONDUCTOR DEVICE - A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body. | 07-21-2011 |
| 20110175233 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of: forming a mask material film on an insulating film that is formed over a semiconductor substrate and then forming a mask pattern having a first trench formation opening and a second trench formation opening from the mask material film; forming, on the mask material film, a resist pattern having a third trench formation opening that exposes the first trench formation opening and covering the second trench formation opening; forming a first trench in the insulating film using the resist pattern and the mask pattern; and forming a second trench in the insulating film using the mask pattern after removing the resist pattern. | 07-21-2011 |
| 20110175234 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit free from increase in chip area or significant reversion in designing is provided. The semiconductor integrated circuit includes: IO buffers arrayed in line; pad coupling wirings respectively arrayed in correspondence with the IO buffers; and IO buffer switching wirings respectively arrayed in line in correspondence with the IO buffers, set in a layer different from those of the IO buffers and the pad coupling wirings so that they overlap with part of the corresponding pad coupling wirings, and extended to other pad coupling wirings adjacent to the corresponding pad coupling wirings. Each of the IO buffer switching wirings is formed in an identical shape so that it is not short-circuited to adjacent other IO buffer switching wirings. The IO buffers are electrically coupled with the corresponding IO buffer switching wirings in the same positions. | 07-21-2011 |
| 20110175235 | WIRING SUBSTRATE AND SEMICONDUCTOR APPARATUS INCLUDING THE WIRING SUBSTRATE - A wiring substrate includes a core substrate including an inorganic dielectric insulating base material having first and second surfaces, and linear conductors penetrating the insulating base; a first wiring layer on the first surface electrically connected to a portion of linear conductors; a second wiring layer on the second surface electrically connected to the portion of the linear conductors; a first insulating layer on the first surface covering the first wiring layer and including a first through-hole; a third wiring layer on the first insulating layer electrically connected to the first wiring layer via the first through-hole; a second insulating layer on the second surface covering the second wiring layer and including a second through-hole; and a fourth wiring layer on the second insulating layer electrically connected to the second wiring layer via the second through-hole. | 07-21-2011 |
| 20110175236 | CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME - An embodiment of the invention provides a chip package, which includes a substrate having an upper surface and a lower surface, a chip disposed in or on the substrate, a pad disposed in or on the substrate and electrically connected to the chip, a hole extending from the lower surface toward the upper surface, exposing the pad, wherein a lower opening of the hole near the lower surface has a width that is shorter than that of an upper opening of the hole near the upper surface, an insulating layer located overlying a sidewall of the hole, and a conducting layer located overlying the insulating layer and electrically connected to the pad. | 07-21-2011 |
| 20110180932 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed. | 07-28-2011 |
| 20110180933 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE MANUFACTURING METHOD - A wiring layer is formed on a substrate, and a semiconductor device is mounted on the substrate. The wiring layer and the semiconductor device are sealed by a sealing resin. A conductive member is used to fill a through hole formed in the sealing resin in a predetermined position of the wiring layer and is provided so as to cover over the sealing resin. The metal foil is provided on the upper surface of the conductive member, and the metal foil and the wiring layer are electrically connected via the conductive member. | 07-28-2011 |
| 20110180934 | SEMICONDUCTOR DEVICE - A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively. | 07-28-2011 |
| 20110180935 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside a conductive pillar location; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond. | 07-28-2011 |
| 20110180936 | SEMICONDUCTOR DEVICE STRUCTURES AND ELECTRONIC DEVICES INCLUDING SAME HYBRID CONDUCTIVE VIAS - A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed. | 07-28-2011 |
| 20110187004 | SEMICONDUCTOR DEVICES INCLUDING AN INTERCONNECTION PATTERN AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a first insulating layer having a plurality of via plugs therein, a second insulating layer on the first insulating layer, and a conducting interconnection pattern disposed in the second insulating layer and having at least one interconnection landing arranged over and electrically connected to the via plugs. | 08-04-2011 |
| 20110193240 | BONDED STRUCTURE WITH ENHANCED ADHESION STRENGTH - A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates. | 08-11-2011 |
| 20110193241 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface. | 08-11-2011 |
| 20110193242 | Chip-stacked semiconductor and manufacturing method thereof - A semiconductor device includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a first silicon film in contact with an inner surface of the isolation trench, a second silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the first and second silicon films. | 08-11-2011 |
| 20110198758 | SEMICONDUCTOR DEVICE INCLUDING CONTACT PLUG AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole. | 08-18-2011 |
| 20110198759 | METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT HAVING REDISTRIBUTION LAYER WITH RECESSED CONNECTORS - A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud. | 08-18-2011 |
| 20110204524 | STRUCTURES AND METHODS OF FORMING PRE FABRICATED DEEP TRENCH CAPACITORS FOR SOI SUBSTRATES - Structures and methods are provided for forming pre-fabricated deep trench capacitors for SOI substrates. The method includes forming a trench in a substrate and forming a dielectric material in the trench. The method further includes depositing a conductive material over the dielectric material in the trench and forming an insulator layer over the conductive material and the substrate. | 08-25-2011 |
| 20110204525 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - An interlayer insulating film containing a pore-forming agent is formed on a semiconductor substrate, and then the interlayer insulating film is irradiated with ultraviolet (UV). This ultraviolet irradiation is performed in at least two separate times. | 08-25-2011 |
| 20110204526 | Methods of Determining X-Y Spatial Orientation of a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Positioning a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Processing a Semiconductor Substrate, and Semiconductor Devices - The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated. | 08-25-2011 |
| 20110210447 | CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES COMPRISING A CONTINUOUS TRANSITION TO METAL LINES OF A METALLIZATION LAYER - In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer. | 09-01-2011 |
| 20110210448 | Interconnect Structures Incorporating Air-Gap Spacers - A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. | 09-01-2011 |
| 20110210449 | INTERCONNECT STRUCTURES INCORPORATING AIR-GAP SPACERS - A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. | 09-01-2011 |
| 20110210450 | SEMICONDUCTOR DEVICE WITH HOLLOW STRUCTURE - A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed. | 09-01-2011 |
| 20110210451 | METHODS OF FORMING A METAL PATTERN AND SEMICONDUCTOR DEVICE STRUCTURE - A method of forming a metal pattern on a dielectric material that comprises forming at least one trench in a photosensitive, insulative material is disclosed. The at least one trench may be positioned over at least one bond pad. A metal is formed over the photosensitive, insulative material and into the at least one trench and a photoresist material is formed over the metal. A portion of the photoresist material may be removed to expose elevated areas of the metal such that a remaining portion of the photoresist material does not extend beyond sidewalls of the at least one trench and onto the elevated areas of the metal. The metal may be exposed laterally beyond the remaining portion of the photoresist material. | 09-01-2011 |
| 20110210452 | THROUGH-SUBSTRATE VIA AND REDISTRIBUTION LAYER WITH METAL PASTE - The invention relates to a semiconductor device for use in a stacked configuration of the semiconductor device and a further semiconductor device. The semiconductor device comprises: a substrate ( | 09-01-2011 |
| 20110215480 | STRESS RESISTANT MICRO-VIA STRUCTURE FOR FLEXIBLE CIRCUITS - A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer. | 09-08-2011 |
| 20110215481 | Semiconductor device - In a semiconductor device, a pad metal has at least a portion located immediately under a probe region, and the portion is divided into a plurality of narrow metal layers each arranged in parallel with a traveling direction of a probe. Thus, it is possible to enhance surface flatness of the pad metal and to prevent a characteristic of a semiconductor device from deteriorating without complication in processing and increase in chip size. | 09-08-2011 |
| 20110215482 | Semiconductor device - The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof. | 09-08-2011 |
| 20110221068 | INTERCONNECT STRUCTURE COMPRISING BLIND VIAS INTENDED TO BE METALIZED - An interconnect structure including:
| 09-15-2011 |
| 20110221069 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor element having a first surface on which an electrode terminal is formed, and a second surface located opposite to the first surface. The semiconductor device further includes a first insulating layer in which the semiconductor element is buried, and second insulating layers and wiring layers formed in such a manner that at least one insulating layer and at least one wiring layer are formed on each of both surfaces of the first insulating layer. The electrode terminal of the semiconductor element is connected to a first wiring layer located on the first surface side through a first via formed in the first insulating layer, and the first wiring layer is connected to a second wiring layer located on the second surface side through a second via formed in the first insulating layer. | 09-15-2011 |
| 20110221070 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads. | 09-15-2011 |
| 20110221071 | ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - In an electronic device having multilayer resin interconnection layers, it is desired to reduce the warp of its support substrate. It is manufactured by: forming a lower layer including a via and a first insulating part on the support substrate; and forming an intermediate layer including a first interconnection and a second insulating part covering the first interconnection on the lower layer. The lower layer is formed by: forming the first insulating part on a first circuit region and a first region surrounding it; and forming the via on the first circuit region. The intermediate layer is formed by: forming the first interconnection on the first circuit region; forming a film of the second insulation part to cover the lower layer; and removing the second insulating part on the first region such that an outer circumferential part of an upper surface of the lower layer part is exposed. | 09-15-2011 |
| 20110241217 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 10-06-2011 |
| 20110241218 | Electronic Device and Manufacturing Method - A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is the pitch of the second contact pads in micrometers. | 10-06-2011 |
| 20110241219 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first contact hole that passes through a planarizing film layered on a first interlayer insulating film, a second interlayer insulating film that covers the surface of the planarizing film and the inner surface of the first contact hole, a third interlayer insulating film layered on the second interlayer insulating film, and a second contact hole formed with a small inner diameter inside the first contact hole and passing through the first to the third interlayer insulating films are formed. Over the third interlayer insulating film and inside the second contact hole, a second conductive film electrically connected to a first conductive film is formed. | 10-06-2011 |
| 20110248408 | Package substrate and fabricating method thereof - There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided. | 10-13-2011 |
| 20110248409 | Method for Stacking Semiconductor Dies - A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer. | 10-13-2011 |
| 20110254168 | INTEGRATED CIRCUIT INTERCONNECT STRUCTURE - An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line. | 10-20-2011 |
| 20110254169 | SEMICONDUCTOR DEVICE WITH THROUGH SUBSTRATE VIA - A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube. | 10-20-2011 |
| 20110254170 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a base layer on which a revision signal transmission circuit is formed, three or more interconnect layers laminated on the base layer, a power source interconnect or a ground interconnect on an uppermost interconnect layer, and a revision signal line which connects the revision control circuit only to the power source interconnect or the ground interconnect of the uppermost interconnect layer. | 10-20-2011 |
| 20110254171 | Integrated Method for High-Density Interconnection of Electronic Components through Stretchable Interconnects - Stretchable multi-chip modules (SMCMs) are capable of withstanding large mechanical deformations and conforming to curved surfaces. These SMCMs may find their utilities in elastic consumer electronics such as elastic displays, skin-like electronic sensors, etc. In particular, stretchable neural implants provide improved performances as to cause less mechanical stress and thus fewer traumas to surrounding soft tissues. Such SMCMs usually comprise of various electronic components attached to or embedded in a polydimethylsiloxane (PDMS) substrate and wired through stretchable interconnects. However, reliably and compactly connecting the electronic components to PDMS-based stretchable interconnects is very challenging. This invention describes an integrated method for high-density interconnection of electronic components through stretchable interconnects in an SMCM. This invention has applications in high-density SMCMs, as well as high-density stretchable/conformable neural interfaces. | 10-20-2011 |
| 20110254172 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant. | 10-20-2011 |
| 20110254173 | Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street - A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed on the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be stacked and electrically interconnected through the TSVs. | 10-20-2011 |
| 20110260329 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a through-chip via passing through a semiconductor chip, and an insulator arranged inside the through-chip via to electrically divide the through-chip via. Here, the divided through-chip vias may transmit different signals. | 10-27-2011 |
| 20110260330 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a semiconductor chip. The semiconductor chip includes a well arranged to receive a first well bias voltage from a well biasing region, a through-chip-via arranged to penetrate the well, and a guard region disposed around the through-chip-via with space in-between and arranged to apply a second well bias voltage to the well. | 10-27-2011 |
| 20110260331 | STACKED SEMICONDUCTOR DEVICE - Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip. | 10-27-2011 |
| 20110260332 | MULTILEVEL INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME - A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via. | 10-27-2011 |
| 20110260333 | INTERCONNECT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced. | 10-27-2011 |
| 20110260334 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer. | 10-27-2011 |
| 20110260335 | POWER SUPPLY INTERCONNECT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT - A power supply interconnect structure of a semiconductor integrated circuit includes a single borderless stack via electrically connecting power supply interconnects of two different interconnect layers to form a connecting portion of the interconnects, and a multi-stack via functioning as another connecting portion of the interconnects, which electrically connect the power supply interconnects, and having a wide pad portion. The single borderless stack via is located in an interconnect region with high signal interconnect density. The multi-stack via is located in an interconnect region with low signal interconnect density. This increases interconnection efficiency in the region with the high signal interconnect density to improve interconnection characteristics. This enables reduction in an area of a chip and increases compatibility to an EDA tool, thereby improving IR-DROP characteristics. | 10-27-2011 |
| 20110266691 | Through-Substrate Vias with Improved Connections - A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via. | 11-03-2011 |
| 20110266692 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole. | 11-03-2011 |
| 20110266693 | TCE COMPENSATION FOR PACKAGE SUBSTRATES FOR REDUCED DIE WARPAGE ASSEMBLY - A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages. | 11-03-2011 |
| 20110266694 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING NANOTUBES, AND SEMICONDUCTOR STRUCTURES, DEVICES, AND SYSTEMS FABRICATED USING SUCH METHODS - A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed. | 11-03-2011 |
| 20110266695 | SEMICONDUCTOR DEVICE LAYOUT METHOD, A COMPUTER PROGRAM, AND A SEMICONDUCTOR DEVICE MANUFACTURE METHOD - A semiconductor device layout method is disclosed, wherein vias carrying the same signal are arranged at intervals equal to the minimum value defined by a design rule, and vias carrying different signals are arranged at second intervals that are greater than the minimum value. | 11-03-2011 |
| 20110266696 | SEMICONDUCTOR DEVICE PACKAGES INCLUDING A SEMICONDUCTOR DEVICE AND A REDISTRIBUTION ELEMENT - A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane. Redistribution elements including these features, as well as semiconductor device assemblies including the redistribution elements and assembly methods, are also disclosed. | 11-03-2011 |
| 20110266697 | ELECTRONIC PART PACKAGE - A peeling off layer | 11-03-2011 |
| 20110272818 | SEMICONDUCTOR DEVICE FOR PREVENTING CRACK IN PAD REGION AND FABRICATING METHOD THEREOF - A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net. | 11-10-2011 |
| 20110272819 | WAFER LEVEL PACKAGE AND METHODS OF FABRICATING THE SAME - In one embodiment, a wafer level package includes a rerouting pattern formed on a semiconductor substrate and a first encapsulant pattern overlying the rerouting pattern. The first encapsulant pattern has a via hole to expose a portion of the rerouting pattern. The package additionally includes an external connection terminal formed on the exposed portion of the rerouting pattern. An upper section of the sidewall and a sidewall of the external connection terminal may be separated by a gap distance. The gap distance may increase toward an upper surface of the encapsulant pattern. | 11-10-2011 |
| 20110272820 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads. | 11-10-2011 |
| 20110272821 | Wiring Substrate Manufacturing Method and Wiring Substrate - A wiring substrate manufactured by thinning a silicon substrate, which is coated by an insulation film, from a lower surface to an upper surface to form a substrate body. The substrate body is etched using a resist, which includes an opening, as a mask and the insulation film as an etching stopper layer to form a through hole and a cover, which covers an opening of the through hole at the upper surface of the substrate body. In a state in which the cover is formed, a functional element is formed on the upper surface of a further insulation film at the upper side of the substrate body. Then, a through electrode is formed in at least the through hole. | 11-10-2011 |
| 20110272822 | Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors - A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another. | 11-10-2011 |
| 20110272823 | THROUGH SUBSTRATE VIAS - Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5. | 11-10-2011 |
| 20110278731 | METHOD FOR INTEGRATED CIRCUIT DESIGN AND MANUFACTURE USING DIAGONAL MINIMUM-WIDTH PATTERNS - Methods for designing and manufacturing an integrated circuit are disclosed, in which the physical design process for a standard cell or cells utilizes a preferred diagonal direction for minimum-width patterns on at least one layer, where the standard cell or cells are used in the layout of an integrated circuit. The methods also include forming the patterns on a photomask using model-based fracturing techniques with charged particle beam simulation, and forming the patterns on a substrate such a silicon wafer using the photomask and an optical lithographic process with directional illumination which is optimized for the preferred diagonal direction. | 11-17-2011 |
| 20110278732 | Interconnect Structures for Substrate - A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like. | 11-17-2011 |
| 20110278733 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR DEVICE COMPRISING A CHIP WITH THROUGH-VIAS - A semiconductor device includes a first wafer having at least one first integrated-circuit chip and a first support layer surrounding the first integrated circuit chip. A first electrical-connection layer is placed on a frontside of the first wafer and includes a first electrical-connection network. A second wafer is placed on a frontside of the first electrical-connection layer. The second wafer includes at least one second integrated-circuit chip and a second support layer surrounding the second integrate circuit chip. The second integrated circuit chip has an active side facing the first electrical-connection layer, and one or more through-holes filled with a conductor forming electrical-connection vias. A second electrical-connection layer is placed on the backside of the second wafer and includes a second electrical-connection network. | 11-17-2011 |
| 20110278734 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads. | 11-17-2011 |
| 20110278735 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads. | 11-17-2011 |
| 20110278736 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure. | 11-17-2011 |
| 20110278737 | Stacking Integrated Circuits containing Serializer and Deserializer Blocks using Through Silicon Via - Methods and systems for stacking multiple chips with high speed serialiser/deserialiser blocks are presented. These methods make use of Through Silicon Via (TSV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serialiser/deserialiser blocks, using the TSVs. | 11-17-2011 |
| 20110278738 | SELF-ALIGNED, INTEGRATED CIRCUIT CONTACT - This document discusses, among other things, example systems including integrated circuit contacts configured to reduce the likelihood of shorting to unrelated portions of overlying conductive material due to contact misalignment. | 11-17-2011 |
| 20110285027 | SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME USING A CAPPING LAYER - A semiconductor structure includes an interconnect region, and a material transfer region coupled to the interconnect region through a bonding interface. The semiconductor structure includes a capping layer sidewall portion which extends annularly around the material transfer region and covers the bonding interface. The capping layer sidewall portion restricts the flow of debris from the bonding interface. | 11-24-2011 |
| 20110285028 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has an insulating film, serving as low-porosity regions low in porosity, formed on a substrate and high-porosity regions higher in porosity than the low-porosity regions, and also includes copper interconnects formed to fill interconnect grooves in the insulating film. The insulating film is present under the interconnect grooves, and present in portions neighboring the sidewalls of the interconnect grooves. | 11-24-2011 |
| 20110285029 | SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS - Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines. | 11-24-2011 |
| 20110285030 | METHOD FOR PRODUCING CHIP PACKAGES, AND CHIP PACKAGE PRODUCED IN THIS WAY - A method for producing chip packages is disclosed. In one embodiment, a plurality of chips is provided. The chips each have first pads. Second connection pads are applied on the wafer, wherein each second pad is electrically connected to a first pad. | 11-24-2011 |
| 20110285031 | Interconnect Structure to Reduce Stress Induced Voiding Effect - An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via. | 11-24-2011 |
| 20110285032 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads. | 11-24-2011 |
| 20110291287 | THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE - A device has a silicon substrate with a via extending from a first surface of the silicon substrate having a conductor portion. A first dielectric portion surrounds the conductor portion. A second dielectric portion is disposed between a first silicon portion and the silicon substrate. | 12-01-2011 |
| 20110291288 | PACKAGE SYSTEMS HAVING INTERPOSERS - A package system includes an integrated circuit disposed over an interposer. The interposer includes a first interconnect structure. A first substrate is disposed over the first interconnect structure. The first substrate includes at least one first through silicon via (TSV) structure therein. A molding compound material is disposed over the first interconnect structure and around the first substrate. The integrated circuit is electrically coupled with the at least one first TSV structure. | 12-01-2011 |
| 20110291289 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes first power supply through-chip vias formed through the semiconductor chip to be in a line in a first direction of the semiconductor chip, second power supply through-chip vias formed through the semiconductor chip to be in, first power lines arranged in a second direction, wherein each of the plurality of first power lines is coupled to each of the first power supply through-chip vias, and second power lines arranged in the second direction, wherein each of the plurality of second power lines is coupled to each of the second power supply through-chip vias. | 12-01-2011 |
| 20110291290 | SEMICONDUCTOR DEVICE - A semiconductor device includes a through-silicon-via arranged to couple a plurality of stacked semiconductor chips, an interconnection line coupled to the through-silicon-via at one side and arranged to couple the through-silicon-via to the semiconductor chip, an internal interconnection line disposed at the other side of the interconnection line and intersected with the interconnection line, and at least one first contact disposed to couple the internal interconnection line to the interconnection line. A region of the interconnection line in which the internal interconnection line is disposed is equally divided, and an area between the divided regions is removed. | 12-01-2011 |
| 20110291291 | Silicon Chip Having Penetrative Connection Holes - Two circuit layout areas on two surfaces of a chip are connected. Holes in the chip are coordinated with a conductive paste to connect the two surfaces. Thus, fabrication is made easy and cost is reduced. | 12-01-2011 |
| 20110291292 | Selective Shrinkage of Contact Elements in a Semiconductor Device - In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element. | 12-01-2011 |
| 20110291293 | METHOD FOR MANUFACTURING AN ELECTRONIC MODULE AND AN ELECTRONIC MODULE - This publication discloses an electronic module and a method for manufacturing an electronic module, in which a component ( | 12-01-2011 |
| 20110298139 | Semiconductor Package - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and a second chip. The substrate has a first surface, a second surface and at least one through hole. The first chip is disposed adjacent to the first surface of the substrate. The first chip includes a first active surface and a plurality of first signal pads. Part of the first active surface is exposed to the through hole. The position of the first signal pads corresponds to the through hole. The second chip is disposed adjacent to the second surface. The second chip includes a second active surface and a plurality of second signal pads. Part of the second active surface is exposed to the through hole. The position of the second signal pads corresponds to the through hole, and the second signal pads are capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the strength of the first chip and the second chip is increased after being mounted to the substrate, so the yield of the semiconductor package is increased. | 12-08-2011 |
| 20110298140 | Component having a through-contact - A method for manufacturing a component having a through-contact includes: providing a substrate; forming an insulating layer on the substrate; structuring the insulating layer, the insulating layer being removed at least in a predetermined trenching area surrounding a selected substrate area; performing an etching process in which the structured insulating layer functions as a mask to remove substrate material in the trenching area and to create a trench structure surrounding the selected substrate area; and forming a metallic layer on the insulating layer, the metallic layer sealing the trench structure. | 12-08-2011 |
| 20110304053 | INTERCONNECT STRUCTURE AND METHOD OF FABRICATING - An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material. | 12-15-2011 |
| 20110304054 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device including a conductive layer formed in a trench formed in a semiconductor substrate via an insulating film, an opening portion of the trench being formed with a plurality of interconnected concaves and with a curved surface as a folding fan so as to set to be the opening portion gradually wider from a sidewall of the trench towards a surface of the semiconductor substrate. | 12-15-2011 |
| 20110304055 | Semiconductor integrated circuit with multi-cut via and automated layout method for the same - A semiconductor integrated circuit includes a first wiring formed on a first wiring layer and prolonged in a first direction, a second wiring formed on a second wiring layer and prolonged in a second direction, a third wiring formed on the first wiring layer and prolonged in the first direction, a fourth wiring formed on the second wiring layer and prolonged in the second direction, a multi-cut via formed to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring. A first overhang is provided in a direction opposite to the first direction, the first overhang being larger than a second overhang, the second overhang being smaller than a third overhang. | 12-15-2011 |
| 20110304056 | STACK-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A stack-type semiconductor package includes: a substrate; a first through electrode module stacked on the substrate comprising a first chip and a second chip connected to the first chip by a first through electrode; a second through electrode module stacked on the first through electrode comprising a third chip and a fourth chip connected to the third chip by a second through electrode; and a signal transmission medium for electrically connecting the substrate to the first through electrode module and the second through electrode module. The stack-type semiconductor package may be highly integrated, reliability thereof is improved by increasing strength of the chips, stacking in high-steps is possible, the stack-type semiconductor package may be thin and simple, and productivity thereof may be significantly increased. | 12-15-2011 |
| 20110304057 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE DEVICE - A semiconductor device includes a semiconductor substrate including a first surface serving as an element formation surface, and a second surface opposite to the first surface; a through-via penetrating the semiconductor substrate; an insulating via coating film formed between a sidewall of the through-via and the semiconductor substrate; and an insulating protective film formed on the second surface of the semiconductor substrate. The via coating film and the protective film are different insulating films from each other. | 12-15-2011 |
| 20110309516 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance. The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap variation between the first signal coupling pads of the first chip and the third signal coupling pads of the second chip is under stringent control of the second distance and the fourth distance. Therefore, the mass-production yield of the semiconductor package is increased. | 12-22-2011 |
| 20110309517 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device including a substrate provided with a semiconductor element, and first and second interconnects provided above the substrate, each of the first and second interconnects having a line shape in a plan view, and the first and second interconnects being substantially parallel to each other. The device further includes a first via plug provided above the substrate, electrically connected to a lower surface of the first interconnect on a second interconnect side, and including a first recess part at an upper end of the first via plug under a first region between interconnects, the first region between interconnects being a region between the first interconnect and the second interconnect. The device further includes a via layer insulator provided above the substrate and including the first via plug, and a first trench under the first region between interconnects, the first trench including a region adjacent to the first via plug in a width direction of the first and second interconnects. Furthermore, an air gap is included in the first region between interconnects and in the first trench. | 12-22-2011 |
| 20110309518 | SEMICONDUCTOR DEVICE WITH CONFIGURABLE THROUGH-SILICON VIAS - Disclosed is a semiconductor device that comprises a plurality of through-silicon vias (TSVs), a signal line and a selective connector for causing the signal line to be either electrically connected to one of the TSVs or electrically isolated from all of the TSVs, based on a control signal. | 12-22-2011 |
| 20110309519 | SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIAS - Disclosed is a semiconductor device with through-silicon vias (TSVs) that comprises a primary TSV group, a plurality of signal lines connected to the primary TSV group, a redundant TSV group and connection circuitry responsive to a control signal having a predetermined value to electrically connect the signal lines to the redundant TSV group. | 12-22-2011 |
| 20110309520 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE DEVICE - A semiconductor device includes a semiconductor substrate including a first surface and a second surface opposite to the first surface, and a through-via penetrating the semiconductor substrate. The through-via has a stacked structure of a first conductive film formed in a portion of the semiconductor substrate closer to the first surface, and a second conductive film formed in a portion of the semiconductor substrate closer to the second surface. An insulating layer is buried inside the semiconductor substrate. The first conductive film is electrically connected to the second conductive film in the insulating layer. | 12-22-2011 |
| 20110309521 | CHIP STACK WITH CONDUCTIVE COLUMN THROUGH ELECTRICALLY INSULATED SEMICONDUCTOR REGION - A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas. | 12-22-2011 |
| 20110309522 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE COMPRISING DIFFERENT LEVEL INTERCONNECTION LAYERS CONNECTED BY CONDUCTOR LAYERS INCLUDING CONDUCTOR LAYER FOR REDUNDANCY - A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. | 12-22-2011 |
| 20110309523 | POP PRECURSOR WITH INTERPOSER FOR TOP PACKAGE BOND PAD PITCH COMPENSATION - An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap height and substrate contact pads lateral to the molded IC die. An interposer including an interposer substrate has bottom metal land pads and top metal land pads, interposer vias, and an open receptacle region formed through the interposer substrate. The substrate top surface is positioned relative to the interposer so that the molded IC die is within the open receptacle region to align the bottom metal land pads and substrate contact pads. An underfill layer is between the substrate top surface and the bottom side of the interposer substrate. A step height from the mold cap height minus a height of the top metal land pads is generally from 0 to 0.2 mm. | 12-22-2011 |
| 20110309524 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL LINE OF SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced. | 12-22-2011 |
| 20110316166 | INTEGRATED CIRCUIT SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer. | 12-29-2011 |
| 20110316167 | ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads. | 12-29-2011 |
| 20110316168 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure. | 12-29-2011 |
| 20110316169 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE WIRING SUBSTRATE - A wiring substrate includes a substrate body including a first substrate surface and a second substrate surface, a trench being open toward the first substrate surface, the trench having an inner bottom surface and an inner side surface, a through-hole having a first end communicating with the inner bottom surface of the trench and a second end being open toward the second substrate surface, a first conductive layer having a first surface toward the trench and being filled inside at least a portion of the through-hole from the second end, a second conductive layer covering the first surface and at least a part of the inner bottom surface of the trench, and a third conductive layer covering the second conductive layer and being filled inside the trench. | 12-29-2011 |
| 20110316170 | Wiring Substrate, Semiconductor Device, and Method for Manufacturing Wiring Substrate - A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion formed in a region corresponding to the recess, a portion formed outward from the recess, and a portion formed inward from the recess. The upper surface of the solder resist layer at the portion corresponding to the recess is higher than the upper surface of the pads but lower than the upper surfaces of the other portions of the solder resist layer. | 12-29-2011 |
| 20110316171 | Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer - A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. | 12-29-2011 |
| 20120001343 | Sophisticated Metallization Systems in Semiconductors Formed by Removing Damaged Dielectric Surface Layers After Forming the Metal Features - In sophisticated semiconductor devices, densely packed metal line layers may be formed on the basis of an ultra low-k dielectric material, wherein corresponding modified portions of increased dielectric constant may be removed in the presence of the metal lines, for instance, by means of a selective wet chemical etch process. Consequently, the metal lines may be provided with desired critical dimensions without having to take into consideration a change of the critical dimensions upon removing the modified material portion, as is the case in conventional strategies. | 01-05-2012 |
| 20120001344 | SEMICONDUCTOR DEVICE MANUFACTURE METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; etching the insulating film to form a dummy groove having a first depth, a wiring groove having a second depth deeper than the first depth, and a via hole to be disposed on a bottom of the wiring groove; depositing a conductive material in the dummy groove, wiring groove and via hole and above the insulating film; and polishing and removing the conductive material above the insulating film. | 01-05-2012 |
| 20120001345 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern. | 01-05-2012 |
| 20120001346 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a word line, a bit line crossing the word line, an active region arranged in an oblique direction at the word line and the bit line, and a contact pad contacting the active region, where the contact pad extends in the oblique direction. | 01-05-2012 |
| 20120007249 | SILICON BASED SUBSTRATE AND MANUFACTURING METHOD THEREOF - A silicon based substrate includes a silicon wafer, a first circuit substrate and a second circuit substrate. The silicon wafer includes a first surface and a second surface and at least a through silicon via. The first circuit substrate is disposed on the first surface and includes a plurality of first dielectric layers and a plurality of first conductive trace layers alternately stacked. The second circuit substrate is disposed on the second surface and includes a plurality of second dielectric layers and a plurality of second conductive trace layers alternately stacked. The trace density of the first conductive trace layers is higher than the trace density of the second conductive trace layers. Otherwise, the first dielectric layer includes an inorganic material and the second dielectric layer includes an organic material. A manufacturing method of the silicon based substrate is also provided. | 01-12-2012 |
| 20120007250 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes. | 01-12-2012 |
| 20120007251 | STACKED MULTI-CHIP - A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip. | 01-12-2012 |
| 20120007252 | SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATING METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity. | 01-12-2012 |
| 20120007253 | SEMICONDUCTOR CHIP AND STACK PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate with a top surface and a bottom surface. An active layer may be formed on the top surface of the semiconductor substrate and may comprise one or more signal pads and one or more chip selection pads on an upper surface of the active layer. First and second through electrodes may be formed to pass through the semiconductor substrate and the active layer, with the first through electrodes being electrically connected with the signal pads and the second through electrodes being electrically connected with the chip selection pads. A side electrode may be formed on a side surface of the semiconductor chip in such a way as to be connected with a second through electrode. | 01-12-2012 |
| 20120007254 | MULTI-LAYER VIA STRUCTURE - Disclosed is a multi-layer via structure, comprising a metal layer, a first via metal layer formed on a first open of a first dielectric layer and a second via metal layer formed on a second open of a second dielectric layer. The first and second via metal layers comprise first and second bottoms, first and second top portions, first and second inclined walls, respectively. The first and second inclined walls comprise first and second top edges, first and second bottom edges respectively. The second top edge has a point closest to a geometric center of the first bottom. A vertical projection of the point falls on the first inclined wall. Alternatively, a point of the second bottom edge, which is closest to the geometric center, has a vertical projection. The vertical projection is vertical to the metal layer and falls on the first inclined wall. | 01-12-2012 |
| 20120007255 | SEMICONDUCTOR DEVICE - A semiconductor device having a power supply wiring and a ground wiring is provided, which can suppress the occurrence of voltage drop in part of wiring and the occurrence of migration caused by voltage drop. The semiconductor device includes a semiconductor substrate having a main surface, a sheet-like power supply wiring spreading in a stratified form along the main surface of the semiconductor substrate, a sheet-like ground wiring spreading along the main surface of the semiconductor substrate in a stratified form and spacedly a predetermined certain distance from the sheet-like power supply wiring in a direction intersecting the main surface of the semiconductor substrate, a power supply wiring formed over the main surface of the semiconductor substrate and extending in one direction within the main surface of the semiconductor substrate, and a ground wiring formed over the main surface of the semiconductor substrate spacedly a predetermined certain distance from the power supply wiring and extending in the one direction. The sheet-like power supply wiring is electrically coupled with the power supply wiring and the sheet-like ground wiring is electrically coupled with the ground wiring. | 01-12-2012 |
| 20120007256 | REDISTRIBUTION LAYERS FOR MICROFEATURE WORKPIECES, AND ASSOCIATED SYSTEMS AND METHODS - Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device. | 01-12-2012 |
| 20120007257 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a first insulating film formed on a substrate and having a first interconnect; a second insulating film as a liner film formed on the first insulating film and the first interconnect so as to contact the first insulating film; and a third insulating film formed on the second insulating film so as to contact the second insulating film. The second insulating film includes pores. | 01-12-2012 |
| 20120013017 | INTEGRATED STRUCTURES OF HIGH PERFORMANCE ACTIVE DEVICES AND PASSIVE DEVICES - Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip. | 01-19-2012 |
| 20120013018 | DIE PACKAGE STRUCTURE AND RELATED DIE PACKAGE STRUCTURE MANUFACTURING METHOD - A die package structure, which comprises: a first die; a second die; a core material layer, provided between the first die and the second die; at least one via, penetrating through the first die, the second die and the core material layer; a metal material, stuffing into the via, such that the first die the second die, and the core material layer can be electrically contacted with each other; at least a signal contacting unit, contacting the metal material; and a dielectric layer, enclosing the first die, including at least one breach exposing the signal contacting unit. | 01-19-2012 |
| 20120013019 | SEMICONDUCTOR DEVICE - A signal line is formed in the a-th layer (a≧2) of a multi-layered interconnect layer and a redistribution layer. A plain line is formed in the b-th layer (b| 01-19-2012 | |
| 20120013020 | MEMS Device Comprising a Hermetically Sealed Cavity and Devices Obtained Thereof - A MEMS device is disclosed comprising a cavity containing a MEMS component, the cavity being formed in a dielectric layer stack having a thickness t | 01-19-2012 |
| 20120013021 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDCUTOR DEVICE - An electronic component incorporation substrate and a method for manufacturing the same that provide a high degree of freedom for selecting materials. An electronic component incorporation substrate includes a first structure, which has a substrate and an electronic component. The substrate includes a substrate body having first and second surfaces. A first wiring pattern is formed on the first surface and electrically connected to a second wiring pattern formed on the second surface through a through via. The electronic component is electrically connected to the first wiring pattern. The electronic component incorporation substrate includes a sealing resin, which seals the first structure, and a third wiring pattern, which is connected to the second wiring pattern through a second via. | 01-19-2012 |
| 20120013022 | METHOD FOR FORMING 3D-INTERCONNECT STRUCTURES WITH AIRGAPS - Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material. | 01-19-2012 |
| 20120013023 | SEMICONDUCTOR DEVICE - The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film. | 01-19-2012 |
| 20120018897 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor module, including: a substrate including wiring patterns formed on both sides thereof; a first device mounted on the substrate; a first molding layer made of a molding material, surrounding the first device and including via holes formed therein to interconnect with the wiring pattern formed on one side of the substrate; and a second device mounted on the first molding layer and electrically connected with the wiring pattern formed on one side of the substrate through the via holes formed in the first molding layer. | 01-26-2012 |
| 20120018898 | VIA STRUCTURE AND METHOD THEREOF - The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided. | 01-26-2012 |
| 20120018899 | Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets - A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias. | 01-26-2012 |
| 20120018900 | Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets - A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias. | 01-26-2012 |
| 20120025394 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link. | 02-02-2012 |
| 20120025395 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO | 02-02-2012 |
| 20120032339 | INTEGRATED CIRCUIT STRUCTURE WITH THROUGH VIA FOR HEAT EVACUATING - An integrated circuit structure includes a semiconductor substrate, an active device disposed on a first region of the semiconductor substrate, a layer stack disposed on a second region of the semiconductor substrate, a through via penetrating through the layer stack and the semiconductor substrate, and a third dielectric layer disposed between the through via and the semiconductor substrate. In one embodiment of the present invention, the layer stack includes a first dielectric layer disposed on the semiconductor substrate and a heat-conducting member disposed on the first dielectric layer. | 02-09-2012 |
| 20120032340 | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV - A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV. | 02-09-2012 |
| 20120032341 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole. | 02-09-2012 |
| 20120032342 | SEMICONDUCTOR PACKAGE FOR SELECTING SEMICONDUCTOR CHIP FROM A CHIP STACK - A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type. | 02-09-2012 |
| 20120032343 | PACKAGE SUBSTRATE FOR BUMP ON TRACE INTERCONNECTION - A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example. | 02-09-2012 |
| 20120032344 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A plurality of interconnects is, for example, a plurality of Cu interconnects, extending parallel to each other. Sidewall insulating films are formed at the sidewalls of each of a plurality of interconnects. An air gap is formed between each of a plurality of interconnects, and is located between a plurality of sidewall insulating films. The insulating film is formed on a plurality of interconnects, a plurality of sidewall insulating films, and the air gap. A via passes through the insulating film, and is connected to any of the interconnects. The sidewall insulating film is formed of a material having an etching rate lower than that of the insulating film in the conditions in which the insulating film is etched. | 02-09-2012 |
| 20120032345 | MULTILAYER CIRCUIT - A multilayer circuit ( | 02-09-2012 |
| 20120032346 | ENVIRONMENT-RESISTANT MODULE, MICROPACKAGE AND METHODS OF MANUFACTURING SAME - An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams. | 02-09-2012 |
| 20120038056 | INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN - The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask. | 02-16-2012 |
| 20120038057 | THERMAL ENHANCEMENT FOR MULTI-LAYER SEMICONDUCTOR STACKS - A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack. | 02-16-2012 |
| 20120038058 | VERTICALLY CONTACTED ELECTRONIC COMPONENT AND METHOD FOR PRODUCING SAME - An electronic component has at least one contact surface situated in a contact plane, at least one insulating layer disposed above the contact plane, at least one stabilizing layer disposed on the insulating layer for increasing a mechanical stability of the component, and at least one of a bonding contact and a soldering contact. The insulating layer and the stabilizing layer have at least one opening which opens in an upper side of the stabilizing layer. The upper side of the stabilizing layer is oriented away from the contact surface. The opening extends through the stabilizing layer and the insulating layer as far as the contact surface. The at least one of a bonding contact and a soldering contact extends over the stabilizing layer and touches the contact surface through the opening. | 02-16-2012 |
| 20120043664 | IMPLEMENTING MULTIPLE DIFFERENT TYPES OF DIES FOR MEMORY STACKING - A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer. | 02-23-2012 |
| 20120043665 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - A semiconductor device according to the present invention is a semiconductor device that includes: a semiconductor substrate having metal wiring formed on a bottom surface of the semiconductor substrate; and a plurality of wiring layers formed above the semiconductor substrate. The wiring layers include a first wiring layer and a second wiring layer that is formed above the first wiring layer. The semiconductor device further includes: a first through electrode which electrically connects the first wiring layer and the metal wiring; a second through electrode which electrically connects the second wiring layer and the metal wiring; and at least one layer difference adjustment film formed between the semiconductor substrate and the wiring layers. The at least one layer difference adjustment film includes a layer difference adjustment film formed on a region excluding a region corresponding to the second through electrode. | 02-23-2012 |
| 20120043666 | Semiconductor Device and Method of Fabricating the Same - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized. | 02-23-2012 |
| 20120043667 | COMPLIANT PRINTED CIRCUIT SEMICONDUCTOR PACKAGE - A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device. | 02-23-2012 |
| 20120056328 | Die Edge Contacts for Semiconductor Devices - A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. | 03-08-2012 |
| 20120056329 | Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect - A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame. | 03-08-2012 |
| 20120056330 | SEMICONDUCTOR DEVICE - A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug. | 03-08-2012 |
| 20120056331 | METHODS OF FORMING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FORMED BY THE SAME - Provided are a method of forming a semiconductor device including a via and a semiconductor device formed by the same. In the method, by forming an unseeded layer that covers a seed layer disposed on a substrate and at a side wall of a via hole, exposes the seed layer disposed at a bottom of the via hole, and cannot serve as a seed, a plated layer configuring the via is formed upward from the seed layer in a bottom-up growth process, and thus, a void is not formed. Also, an inlet of the via hole is not blocked by using the bottom-up growth process, and thus, an electroplating speed can increase, thereby shortening a time taken in filling the via hole with a metal. | 03-08-2012 |
| 20120056332 | COMPLIANT PRINTED CIRCUIT WAFER LEVEL SEMICONDUCTOR PACKAGE - A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices. | 03-08-2012 |
| 20120061848 | CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHESIVE LAYER - A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffner. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffner can be tailored so that the thermal coefficient of expansion of the stiffner provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon. | 03-15-2012 |
| 20120061849 | SEMICONDUCTOR COMPONENT AND DEVICE PROVIDED WITH HEAT DISSIPATION MEANS - A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components. | 03-15-2012 |
| 20120061850 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA). | 03-15-2012 |
| 20120061851 | SIMULATED WIREBOND SEMICONDUCTOR PACKAGE - A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds | 03-15-2012 |
| 20120068351 | CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING - An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element. | 03-22-2012 |
| 20120068352 | STACKED CHIP ASSEMBLY HAVING VERTICAL VIAS - An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region. | 03-22-2012 |
| 20120068353 | Semiconductor Device and Method of Forming Dam Material With Openings Around Semiconductor Die for Mold Underfill Using Dispenser and Vacuum Assist - A semiconductor wafer contains a plurality of semiconductor die separated by saw streets. A dam material is formed over the saw streets around each of the semiconductor die. A plurality of openings is formed in the dam material. The openings in the dam material can be formed on each side or corners of the first semiconductor die. The semiconductor wafer is singulated through the dam material to separate the semiconductor die. The semiconductor die is mounted to a substrate. A mold underfill is deposited through a first opening in the dam material. A vacuum is drawn on a second opening in the dam material to cause the underfill material to cover an area between the first semiconductor die and substrate without voids. The number of second openings can be greater than the number of first openings. The first opening can be larger than the second opening. | 03-22-2012 |
| 20120068354 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a multilayer body, a second electrode film provided on the multilayer body, a second insulating film provided on the second electrode film, a semiconductor film, a memory film and a gate insulating film. At boundary between the inner surface of the second through hole and the inner surface of the third through hole, or on the inner surface of the second through hole, a step difference is formed so that an upper side from the step difference is thicker than a lower side from the step difference. | 03-22-2012 |
| 20120068355 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including two silicon wafers stacked and bonded together with bumps of one wafer electrically coupled with those of the other wafer, in which generation of voids on the junction surface between the silicon wafers is suppressed. Due to a recess made in the surface of a buried conductive film, a cavity is formed in the junction surface between the silicon wafers. The ends of the cavity extend to the periphery of the junction surface between the silicon wafers. This allows the air trapped on the junction surface between the silicon wafers to get out through the cavity, thereby reducing the possibility of generation of voids on the junction surface. | 03-22-2012 |
| 20120068356 | Component having a VIA - A component having a via includes: (i) a first layer having a first via portion, a first trench structure, and a first surrounding layer portion, the first via portion being separated by the first trench structure from the first surrounding layer portion; (ii) a second layer having a second via portion, a second trench structure, and a second surrounding layer portion, the second via portion being separated by the second trench structure from the second surrounding layer portion; (iii) an insulation layer disposed between the first and the second layer, the insulation layer having an opening so that the first and the second via portions of the first and the second layers are directly connected to one another in the region of the opening. The first via portion and the second surrounding layer portion at least partially overlap. | 03-22-2012 |
| 20120068357 | SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a base, a semiconductor element, an electrode terminal, a connecting member and a joining material. The semiconductor element is mounted on the base. The electrode terminal is provided spaced from the base. The connecting member connects the semiconductor element to the electrode terminal and includes a plurality of through holes provided in one end portion of the connecting member. The one end portion is connected to the semiconductor element. The joining material intervenes between the semiconductor element and the connecting member and penetrates into the plurality of through holes. | 03-22-2012 |
| 20120068358 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring. | 03-22-2012 |
| 20120068359 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device comprises: a core substrate; at least one insulating layer and at least one wiring layer which are disposed on each of a first surface of the core substrate and a second surface opposite to the first surface; a via(s) which is disposed in each of the insulating layer and the core substrate, and connects the wiring layers to each other; a semiconductor element, mounted on the first surface of the core substrate, with a surface for forming an electrode terminal(s) facing up; and a connecting portion(s) which penetrates the insulating layer disposed on the first surface and directly connects the electrode terminal of the semiconductor element and the wiring layer disposed on the first surface. A minimum wiring pitch of the wiring layer directly connected to the connecting portion is smaller than that of any of the wiring layer(s) disposed on the second surface. | 03-22-2012 |
| 20120068360 | Stacked Semiconductor Device Assembly - The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices. In some embodiments, the first pad is associated with a first capacitance, while the second pad is associated with a second capacitance that is smaller than the first capacitance. | 03-22-2012 |
| 20120074579 | SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS - A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side. | 03-29-2012 |
| 20120074580 | METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C | 03-29-2012 |
| 20120074581 | DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate. | 03-29-2012 |
| 20120074582 | DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME - A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. | 03-29-2012 |
| 20120074583 | SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING - A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width. | 03-29-2012 |
| 20120074584 | MULTI-LAYER TSV INSULATION AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate. The stacked insulation layer can include at least one first insulation layer and at least one second insulation layer whose dielectric constant is different than that of the first insulation layer. One insulation layer may be a polymer and one insulation layer may be a silicon based insulation layer. The insulation layers may be uniform in thickness or may vary as a distance from the substrate changes. | 03-29-2012 |
| 20120074585 | Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer - A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die. | 03-29-2012 |
| 20120074586 | METHODS OF FABRICATING PACKAGE STACK STRUCTURE AND METHOD OF MOUNTING PACKAGE STACK STRUCTURE ON SYSTEM BOARD - A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate. | 03-29-2012 |
| 20120074587 | Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level - A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die. | 03-29-2012 |
| 20120080802 | THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. | 04-05-2012 |
| 20120080803 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE - A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke. | 04-05-2012 |
| 20120080804 | ELECTRONIC DEVICE INCLUDING INTERCONNECTS WITH A CAVITY THEREBETWEEN AND A PROCESS OF FORMING THE SAME - A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity. | 04-05-2012 |
| 20120080805 | Semiconductor device and method of manufacturing the same - A semiconductor device according to the invention includes a first Cu interconnect and a first barrier insulating film. a The first barrier insulating film is provided on the first Cu interconnect, and prevents Cu from being diffused from the first Cu interconnect. In addition, the semiconductor device includes a second Cu interconnect and a second barrier insulating film on the first barrier insulating film. The second barrier insulating film is provided on a first Cu interconnect, and prevents Cu from being diffused from the second Cu interconnect. The first and second barrier insulating films are made of a silicon-based insulating film having a branched alkyl group and a carbon-carbon double bond. | 04-05-2012 |
| 20120086128 | BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS - A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed. | 04-12-2012 |
| 20120086129 | Manufacturing of a Device Including a Semiconductor Chip - A method includes providing a semiconductor chip having a first main surface and a second main surface opposite to the first main surface. An electrically insulating material is deposited on the first main surface of the semiconductor chip using a plasma deposition method. A first electrically conductive material is deposited on the second main surface of the semiconductor chip using a plasma deposition method. | 04-12-2012 |
| 20120086130 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion. | 04-12-2012 |
| 20120086131 | SEMICONDUCTOR ELEMENT HAVING CONDUCTIVE VIAS AND SEMICONDUCTOR PACKAGE HAVING A SEMICONDUCTOR ELEMENT WITH CONDUCTIVE VIAS AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor element having conductive vias and a semiconductor package having a semiconductor element with conductive vias and a method for making the same. The semiconductor element having conductive vias includes a silicon substrate and at least one conductive via. The thickness of the silicon substrate is substantially in a range from 75 to 150 μm. The conductive via includes a first insulation layer and a conductive metal, and the thickness of the first insulation layer is substantially in a range from 5 to 19 μm. Using the semiconductor element and the semiconductor package of the present invention, the electrical connection between the conductive via and the other element can be ensured, and the electrical connection between the silicon substrate and the other semiconductor element can be ensured, so as to raise the yield rate of a product. Moreover, by employing the method of the present invention, warpage and shift of the silicon substrate can be avoided during the reflow process, so as to conduct the reflow process only a single time in the method of the present invention, thereby simplifying the subsequent process and reducing cost. | 04-12-2012 |
| 20120086132 | METHOD OF MANUFACTURING VIA ELECTRODE - Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles. | 04-12-2012 |
| 20120091593 | STRUCTURE AND METHOD FOR SIMULTANEOUSLY FORMING A THROUGH SILICON VIA AND A DEEP TRENCH STRUCTURE - A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned. | 04-19-2012 |
| 20120091594 | Method of Producing a Chip Package, and Chip Package - A method of producing a chip package includes providing a substrate comprising a first recess having a recess bottom and recess side walls. A chip comprising a chip backside is introduced into the recess such that the chip does not protrude from the recess and such that a gap remains between the recess side walls and the chip, the chip backside being attached to the recess bottom. The gap is filled with a filler material. | 04-19-2012 |
| 20120098140 | HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS - A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions. | 04-26-2012 |
| 20120098141 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a bit line contact plug that is coupled to the active region and that includes a first ion implantation region buried in a first inner void, and a storage node contact plug that is coupled to the active region and includes a second ion implantation region buried in a second inner void. Although the semiconductor device is highly integrated, a contact plug is buried to prevent formation of a void, so that increase in contact plug resistance is prevented, resulting in improved semiconductor device characteristics. | 04-26-2012 |
| 20120098142 | ELECTRICAL CONTACT FOR A DEEP BURIED LAYER IN A SEMI-CONDUCTOR DEVICE - A semi-conductor device includes at least one deep buried layer with an electrical connection made thereto by an electrical contact. The electrical contact to the deep buried layer is made by formed an opening through the use of a first chemical attack and a second chemical attack after the first chemical attack. By making an opening, the electrical contact can be made with the deep buried layer without at the same time occupying excessively wide portions of the device. For example, it is possible to make electrical contacts having a width of less than 1.5 μm with deep layers having a depth of more than 5 μm. | 04-26-2012 |
| 20120098143 | METHOD FOR PACKAGING A SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE - A method for packaging a semiconductor chip includes: providing a semiconductor wafer that has an upper surface and includes a plurality of chip regions, each of the chip regions having a semiconductor unit that includes at least one electrical-connecting pad; forming over the upper surface a photoresist layer, followed by forming a plurality of pad-exposing holes in the photoresist layer; filling a first conductive material in the pad-exposing holes, followed by reflowing; removing the photoresist layer, and forming over the upper surface a protective layer; grinding the protective layer; coating an insulated protective layer on the ground protective layer, and forming a plurality of via holes in the insulated protective layer; filling a second conductive material in the via holes, followed by reflowing; and removing the insulated protective layer. | 04-26-2012 |
| 20120098144 | VERTICAL ELECTRODE STRUCTURE USING TRENCH AND METHOD FOR FABRICATING THE VERTICAL ELECTRODE STRUCTURE - Provided is a vertical electrode structure using a trench and a method of manufacturing the vertical electrode structure. The method of forming a vertical electrode structure using a trench includes steps of: forming the trench on a predetermined region of a semiconductor substrate; and forming electrode layers in predetermined regions of inner and outer portions of the trench. In this manner, the electrode deposition in the vertical direction is established by using the trench, so that it is possible to form a deposited electrode having a size of several hundred nm or less by a short processing time and a low processing cost. | 04-26-2012 |
| 20120098145 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness. | 04-26-2012 |
| 20120104622 | Through Level Vias and Methods of Formation Thereof - In one embodiment, a semiconductor device includes a first metal line disposed in a first metal level above a substrate. A second metal line is disposed in a second metal level disposed over the first metal level. A third metal line is disposed in a third metal level disposed over the second metal level. A through level via contacts the first metal line and the third metal line. | 05-03-2012 |
| 20120104623 | Semiconductor Device and Method of Forming Stepped Interposer for Stacking and Electrically Connecting Semiconductor Die - A semiconductor substrate has a plurality of different size recesses formed in the substrate to provide a stepped interposer. A conductive via can be formed through the stepped interposer. An insulating layer follows a contour of the stepped interposer. A conductive layer is formed over the insulating layer following the contour of the stepped interposer. A first semiconductor die is partially disposed in a first recess and electrically connected to the conductive layer. A second semiconductor die is partially disposed in a second recess and electrically connected to the conductive layer. The first semiconductor die is electrically connected to the second semiconductor die through the conductive layer. The first and second semiconductor die can be flipchip type semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of the stepped interposer can be removed to reduce thickness. | 05-03-2012 |
| 20120104624 | Semiconductor Device and Method of Stacking Semiconductor Die in Mold Laser Package Interconnected by Bumps and Conductive Vias - A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via. | 05-03-2012 |
| 20120104625 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip having a bonding pad, a metal line electrically connected to the semiconductor chip and having a terminal contacting an external terminal, an insulation layer covering the metal line and having an opening that defines the terminal, and a molding layer molding the semiconductor chip, wherein the molding layer includes a recess pattern exposing the bonding pad and extending from the bonding pad to the terminal, and the metal line is embedded in the recess pattern to contact the bonding pad. | 05-03-2012 |
| 20120104626 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE - An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second substrate including a die location of the second die. The process can also include attaching the second substrate to a handling substrate and singulating the second die from the second substrate before removing the handling substrate. In another aspect, the handling substrate can include a rigid substrate. The process can include orienting the front side of the first die and a back side of the second substrate front-to-back with respect to each other. In yet another aspect, the first terminal is electrically connected to the through via and the second terminal. In one embodiment, the electronic device can include a third die. | 05-03-2012 |
| 20120104627 | SEMICONDUCTOR CHIPS HAVING REDISTRIBUTED POWER/GROUND LINES DIRECTLY CONNECTED TO POWER/GROUND LINES OF INTERNAL CIRCUITS AND METHODS OF FABRICATING THE SAME - Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided. | 05-03-2012 |
| 20120104628 | INTERPOSER FOR SEMICONDUCTOR PACKAGE - An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact. | 05-03-2012 |
| 20120104629 | REVERSIBLE TOP/BOTTOM MEMS PACKAGE - A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die. | 05-03-2012 |
| 20120112356 | SYSTEM AND METHOD FOR RELIEVING STRESS AND IMPROVING HEAT MANAGEMENT IN A 3D CHIP STACK - The present disclosure provides a system and method for relieving stress and providing improved heat management in a | 05-10-2012 |
| 20120112357 | SYSTEM AND METHOD FOR RELIEVING STRESS AND IMPROVING HEAT MANAGEMENT IN A 3D CHIP STACK HAVING AN ARRAY OF INTER-STACK CONNECTIONS - The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to the chip stack. Additionally, improved heat management is provided such that the chip stack adjusts in response to thermal energy generated within the chip stack to remove heat from between chips of the stack, thereby allowing the chips to operate as desired without compromising the performance of the chip stack. The chip stack also includes an array of flexible conductors disposed between two chips, thereby providing an electrical connection between the two chips. | 05-10-2012 |
| 20120112358 | STACK-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability. | 05-10-2012 |
| 20120112359 | Semiconductor Devices and Fabrication Methods thereof - A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures. | 05-10-2012 |
| 20120112360 | SEMICONDUCTOR CHIP, STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME, AND METHOD FOR MANUFACTURING STACKED SEMICONDUCTOR PACKAGE - A semiconductor chip includes a semiconductor chip body including a peripheral region, a first region and a second region, and having a plurality of memory banks formed in each of the first region and the second region; a plurality of first through electrodes formed in the peripheral region; and a plurality of second through electrodes formed in the first and second regions along a direction parallel to a minor axis of the semiconductor chip body. | 05-10-2012 |
| 20120112361 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate having a via hole comprised of a first region having a first width and a second region having a second width greater than the first width, wherein at least a portion of the substrate is exposed in the via hole, and an insulating region having an air gap spaced apart from and surrounding the first region of the via hole. | 05-10-2012 |
| 20120112362 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern. | 05-10-2012 |
| 20120112363 | CHIP STRUCTURE HAVING REDISTRIBUTION LAYER - A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer. | 05-10-2012 |
| 20120119373 | WAFER LEVEL SEMICONDUCTOR PACKAGE AND MANUFACTURING METHODS THEREOF - A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die. | 05-17-2012 |
| 20120119374 | THROUGH SILICON VIA WITH IMPROVED RELIABILITY - A semiconductor device includes a substrate having a top surface and a bottom surface, and a through-silicon via (TSV) extending from the top surface of the substrate to the bottom surface of the substrate, the TSV having a height and a side profile extending along a longitudinal axis, wherein the side profile has an upper segment forming a first angle relative to the longitudinal axis, and a lower segment forming a second angle relative to the longitudinal axis, the second angle being different from the first angle, and wherein the lower segment has a height that is less than 20% of the height of the TSV. | 05-17-2012 |
| 20120119375 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs. | 05-17-2012 |
| 20120119376 | SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME - Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate | 05-17-2012 |
| 20120119377 | WIRING SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING WIRING SUBSTRATE - A wiring substrate is provided with a first wiring layer including a first land, a first insulative layer formed on the first wiring layer, a second wiring layer formed on the first insulative layer, a second insulative layer formed on the second wiring layer, and a via formed extending through the first insulative layer and the second insulative layer in a thicknesswise direction. The via includes one end, which is electrically connected to the first land of the first wiring layer, and another end, which is located opposed to the one end and serves as a pad to which a mounted electronic component is electrically connected. The second wiring layer includes a coupling portion electrically connected to the via. The coupling portion of the second wiring has a width that is smaller than a diameter of the via. | 05-17-2012 |
| 20120119378 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A support carrier is provided and the at least one die is attached to the support carrier. The first surface of the at least one die is facing the support carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The second surface of the cap is disposed at a different plane than the second surface of the die. | 05-17-2012 |
| 20120119379 | ELECTRIC PART PACKAGE AND MANUFACTURING METHOD THEREOF - A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part. | 05-17-2012 |
| 20120119380 | MICROELECTRONIC PACKAGE WITH TERMINALS ON DIELECTRIC MASS - A package for a microelectronic element, such as a semiconductor chip, has a dielectric mass overlying the package substrate and microelectronic element and has top terminals exposed at the top surface of the dielectric mass. Traces extending along edge surfaces of the dielectric mass desirably connect the top terminals to bottom terminals on the package substrate. The dielectric mass can be formed, for example, by molding or by application of a conformal layer. | 05-17-2012 |
| 20120119381 | SEMICONDUCTOR DEVICE WITH VERTICAL CURRENT FLOW AND LOW SUBSTRATE RESISTANCE AND MANUFACTURING PROCESS THEREOF - A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate. | 05-17-2012 |
| 20120119382 | SEMICONDUCTOR DEVICE WITH VERTICAL CURRENT FLOW AND LOW SUBSTRATE RESISTANCE AND MANUFACTURING PROCESS THEREOF - A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate. | 05-17-2012 |
| 20120119383 | STACKED INTEGRATED CIRCUIT PACKAGE FABRICATION METHODS THAT USE VIAS FORMED AND FILLED AFTER STACKING, AND RELATED STACKED INTEGRATED CIRCUIT PACKAGE STRUCTURES - Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described. | 05-17-2012 |
| 20120119384 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device having a through-hole electrode and a manufacturing method thereof, a dummy groove hole portion for forming insulating portion insulating wirings from each other is provided, to surround a rewiring layer including a through-hole electrode on a back surface of a semiconductor substrate. This allows the wirings to be insulated from each other just by removing the metal layer existing at a bottom portion of the dummy groove hole portion. Thus, a reduction in the processing time can be realized. | 05-17-2012 |
| 20120126415 | Filling Cavities in Semiconductor Structures - High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom. | 05-24-2012 |
| 20120126416 | Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die - A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate. | 05-24-2012 |
| 20120126417 | Semiconductor Device And Semiconductor Package Having The Same - The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a semiconductor substrate, a backside dielectric layer, a plurality of first backside under ball metal (UBM) pads and a first backside UBM plane. The backside dielectric layer is disposed adjacent to a backside surface of the semiconductor substrate. The first backside UBM pads are disposed on the backside dielectric layer. The first backside UBM plane is disposed on the backside dielectric layer, and has a plurality of through holes. The first backside UBM pads are located within the through holes, and a gap is between the first backside UBM plane and the first backside UBM pads. Whereby, the cost for forming the first backside UBM pads and the first backside UBM plane is relatively low | 05-24-2012 |
| 20120126418 | INTEGRATED CIRCUIT DEVICE HAVING DIE BONDED TO THE POLYMER SIDE OF A POLYMER SUBSTRATE - An integrated circuit (IC) device includes a polymer substrate having a topside surface and a bottomside surface opposite the topside surface, a plurality of through-holes that extend from the topside surface to the bottomside surface, and a plurality of bottom metal pads on the bottomside surface positioned over the plurality of through-holes. At least one IC die having an active topside including a plurality of bond pads and a second side is affixed to the topside surface. Bonding features are coupled to the plurality of bond pads for coupling respective ones of the plurality of bond pads to the plurality bottom metal pads. The bonding features extend into the through-holes to contact the bottom metal pads. | 05-24-2012 |
| 20120126419 | Substrate Arrangement and a Method of Manufacturing a Substrate Arrangement - According to one embodiment of the present invention, a substrate arrangement is provided. The substrate arrangement includes a first substrate; a second substrate positioned above the first substrate, the second substrate comprising a first through hole; a third substrate positioned above the second substrate, the third substrate comprising a second through hole; a first electrically conductive interconnect pillar positioned on the first substrate and extending from the first substrate through the first through hole to electrically contact the third substrate; and a second electrically conductive interconnect pillar positioned on the second substrate and extending from the second substrate through the second through hole. A method of manufacturing a substrate arrangement is also provided. | 05-24-2012 |
| 20120126420 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS AND SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR DEVICE - The present invention relates to a package having a semiconductor device. The semiconductor device includes a substrate body, a plurality of conductive vias and a plurality of metal pads. The conductive vias are disposed in the through holes of the substrate body. The metal pads are electrically connected to the conductive vias. At least one of the metal pads has at least one curved side wall and at least one reference side wall. The curvature of the curved side wall is different from that of the reference side wall, so as to allow the metal pads to be closer to each other. This arrangement allows the conductive to be closer to each other. Therefore, more conductive vias can be arranged in a limited space. | 05-24-2012 |
| 20120126421 | Semiconductor Devices and Methods of Forming the Same - A method of forming a semiconductor device may include forming a contact mold layer on a substrate; forming an interconnection mold layer on the contact mold layer that includes a material having an etching selectivity with respect to the contact mold layer; forming grooves in the interconnection mold layer that extend in a first direction and expose the contact mold layer; forming holes in the contact mold layer connected to the grooves by etching a part of the contact mold layer exposed by the groove; and forming contact portions in the holes and interconnections in the groove. A diffusion coefficient of mobile atoms in the contact mold layer is greater than a diffusion coefficient of mobile atoms in a nitride. | 05-24-2012 |
| 20120126422 | SEMICONDUCTOR DEVICE HAVING PLURAL WIRING LAYERS - A semiconductor device includes a lower wiring layer, having signal lines and power supply lines extending in a Y-direction; an upper wiring layer having signal lines and power supply lines extending in an X-direction; via conductors provided in first overlap regions where corresponding signal lines overlap each other; and via conductors provided in second overlap regions where corresponding power supply lines overlap each other. The width in the X-direction of the first regions is wider than the widths in the X-direction of the second regions. Therefore, in the first regions, a plurality of via conductors can be provided. Moreover, the power supply lines are divided in the Y-direction to avoid interference with the first regions. On a plurality of lower-layer lines, two vias are placed at a minimum pitch containing one via. | 05-24-2012 |
| 20120126423 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device manufacturing method, including: preparing a support plate having a mounting portion on which a mounting terminal is mountable; preparing a circuit board having a mounting surface on which a semiconductor chip is mounted and a connection pad is formed; bringing the support plate to face the mounting surface of the circuit board, and connecting the support plate to the connection pad through the mounting terminal; forming a resin layer between the support plate and the mounting surface of the circuit board to cover the mounting terminal; and removing the support plate, thereby faulting a via in the resin layer along a shape of the mounting portion so as to expose the mounting terminal therethrough. | 05-24-2012 |
| 20120126424 | SEMICONDUCTOR CHIP INCLUDING A CHIP VIA PLUG PENETRATING A SUBSTRATE, A SEMICONDUCTOR STACK, A SEMICONDUCTOR DEVICE PACKAGE AND AN ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure. | 05-24-2012 |
| 20120126425 | 3D INTEGRATED CIRCUITS STRUCTURE - A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit. | 05-24-2012 |
| 20120133046 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure and a process thereof are provided. The semiconductor structure includes a semiconductor wafer having a first surface and a second surface opposite to the first surface, through silicon vias and a crack stopping slot. The through silicon vias are embedded in the semiconductor wafer and connected between the first surface and the second surface. The crack stopping slot is located in the periphery of the second surface of the semiconductor wafer. The depth of the crack stopping slot is less than or equal to the thickness of the semiconductor wafer. The process firstly provides a semiconductor wafer having through silicon vias. Then, the aforementioned crack stopping slot is formed at a back side of the semiconductor wafer opposite to the first surface. Next, the semiconductor wafer is thinned from the back side to expose a second end of each through silicon via. | 05-31-2012 |
| 20120133047 | Method of Plating Through Wafer Vias in a Wafer for 3D Packaging - Therefore, a method of plating wafer via holes in a wafer is provided. A substrate ( | 05-31-2012 |
| 20120133048 | SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector. | 05-31-2012 |
| 20120133049 | Process of Fabricating Semiconductor Device and Through Substrate via, and Through Substrate via Structure Therefrom - A method of fabricating a semiconductor device, a process of fabricating a through substrate via and a substrate with through vias are provided. The substrate with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers. | 05-31-2012 |
| 20120133050 | TUNNEL JUNCTION VIA - A memory device comprising a plurality of tunnel junctions (TJs) includes a bottom wiring layer; a top wiring layer; a plurality of TJs contacting the bottom wiring layer and the top wiring layer; and a plurality of tunnel junction vias (TJVs) contacting the bottom wiring layer and the top wiring layer, wherein the plurality of TJVs each have a lower resistance the each of the plurality of TJs, wherein the plurality of TJVs comprise at least one concave surface, and wherein the at least one concave surface of the plurality of TJVs is configured to trap etched material during formation of the TJVs so as to reduce the resistance of the plurality of TJVs. | 05-31-2012 |
| 20120133051 | SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE - A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks. | 05-31-2012 |
| 20120133052 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism). | 05-31-2012 |
| 20120139123 | OFFSET SOLDER VIAS, METHODS OF MANUFACTURING AND DESIGN STRUCTURES - Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer. | 06-07-2012 |
| 20120139124 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES WITH PLURAL ACTIVE CHIPS - A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle. | 06-07-2012 |
| 20120139125 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THEREOF - Provided are a multi-chip package and a method of manufacturing the same, which can facilitate wire bonding even when an upper chip is larger than a lower chip or overhangs a lower chip. A multi-chip package includes a substrate having first and second bonding pads on a top surface thereof, a first chip connected to the first bonding pads on the substrate, an insulating layer formed on the substrate so as to surround lateral surfaces of the first chip, a set of openings formed in the insulating layer so as to expose the second bonding pads, and a second chip formed on the insulating layer and the first chip, the second chip having a larger area than the first chip and connected to the second bonding pads using wires that pass through the second openings. | 06-07-2012 |
| 20120139126 | BONDING STRUCTURE OF SEMICONDUCTOR PACKAGE, METHOD FOR FABRICATING THE SAME, AND STACK-TYPE SEMICONDUCTOR PACKAGE - A bonding structure of a semiconductor package includes: a first conductive member configured to transmit an electrical signal; and a bonding pad configured to be electrically coupled to a surface of the first conductive member and comprising a plurality of sub bonding pads. | 06-07-2012 |
| 20120139127 | METHOD FOR FORMING ISOLATION TRENCHES - A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided. | 06-07-2012 |
| 20120139128 | SEMICONDUCTOR PACKAGE AND A METHOD FOR SELECTING A CHIP IN THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip formed with a first through-silicon via; a second semiconductor chip stacked over the first semiconductor chip and formed with a second through-silicon via; and a cantilever formed over the first semiconductor chip and electrically connected to the first through-silicon via or the second through-silicon via according to an electrical signal. | 06-07-2012 |
| 20120146234 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads. | 06-14-2012 |
| 20120146235 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an outer contact pad having an outer pad top side; mounting an integrated circuit above the outer pad top side; forming an encapsulation having an encapsulation top side and an encapsulation bottom side, the encapsulation over the integrated circuit with the encapsulation bottom side coplanar with the outer pad top side; and forming a vertical interconnect through the encapsulation, the vertical interconnect having an interconnect bottom side directly on the outer pad top side and an interconnect top side exposed from the encapsulation. | 06-14-2012 |
| 20120146236 | Semiconductor Device and Method of Forming Openings Through Insulating Layer Over Encapsulant for Enhanced Adhesion of Interconnect Structure - A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site. | 06-14-2012 |
| 20120146237 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. When forming a profile of the lower electrode, a second lower electrode hole (i.e., a bunker region) located at the lowermost part of the lower electrode is buried with an Ultra Low Temperature Oxide (ULTO) material without damaging the lower electrode material. As a result, when a dielectric film is deposited in a subsequent process, the above-mentioned semiconductor device prevents the occurrence of a capacitor leakage current caused by defective gapfilling of the dielectric film located at the lowermost part of the lower electrode. | 06-14-2012 |
| 20120146238 | Method for Packaging Semiconductor Dies Having Through-Silicon Vias - Integrated circuit structures and methods are provided. According to an embodiment, a circuit structure includes a die and an anisotropic conducting film (ACF). The die comprises a through via, and the through via protrudes from a surface of the die. A cross-sectional area of the through via in the surface of the die is equal to a cross-sectional area of a protruding portion of the through via in a plane parallel to the surface of the die. The ACF adjoins the surface of the die, and the protruding portion of the through via penetrates the ACF. | 06-14-2012 |
| 20120146239 | PACKAGED MICROELECTRONIC DEVICES RECESSED IN SUPPORT MEMBER CAVITIES, AND ASSOCIATED METHODS - Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device. | 06-14-2012 |
| 20120153492 | METHOD OF FABRICATION OF THROUGH-SUBSTRATE VIAS - A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material. | 06-21-2012 |
| 20120153493 | EMBEDDED COMPONENT DEVICE AND MANUFACTURING METHODS THEREOF - An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening. | 06-21-2012 |
| 20120153494 | FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a patterned die backside film (DBF) on a backside of a die, wherein the patterned DBF comprises an opening surrounding at least one through silicon via (TSV) pad disposed on the backside of the die. | 06-21-2012 |
| 20120153495 | REDUCED PTH PAD FOR ENABLING CORE ROUTING AND SUBSTRATE LAYER COUNT REDUCTION - Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate. | 06-21-2012 |
| 20120153496 | TSV FOR 3D PACKAGING OF SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same. | 06-21-2012 |
| 20120153497 | INTEGRATED CIRCUIT HAVING A THREE DIMENSIONAL STACK PACKAGE STRUCTURE - An integrated circuit includes a first semiconductor chip including a plurality of first through chip vias for a first voltage and a plurality of second through chip vias for a second voltage inserted in vertical direction. A second semiconductor chip is stacked over the first semiconductor chip, and includes the plurality of first through chip vias and the plurality of second through chip vias. The plurality of first connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding first through chip vias. The plurality of second connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding second through chip vias. A first conductive line is configured to couple the plurality of first connection pads to each other, and a second conductive line is configured to couple the plurality of second connection pads to each other. An isolation layer is inserted between the first conductive line and the second conductive line. | 06-21-2012 |
| 20120153498 | Semiconductor Device and Method of Forming the Same - In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented. | 06-21-2012 |
| 20120153499 | SEMICONDUCTOR PACKAGE AND PACKAGE ON PACKAGE HAVING THE SAME - A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform. | 06-21-2012 |
| 20120153500 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact. | 06-21-2012 |
| 20120153501 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device in which the semiconductor chip including the external terminal(s) is embedded in an insulating layer and interconnect conductor(s) is (are) formed on the insulating layer, base hole(s) is (are) formed at position(s) of the insulating layer corresponding to the external terminal(s) in a state where the semiconductor chip has shrunk after having been embedded in the insulating layer. The interconnect conductor(s) is (are) electrically connected to the external terminal(s) through the base hole(s). | 06-21-2012 |
| 20120153502 | STRUCTURES COMPRISING PLANAR ELECTRONIC DEVICES - A method of manufacturing a structure comprising substantially planar electronic devices comprises providing an active material layer having a plurality of insulative features formed therein. The features at least partly inhibit electrical current flow and define at least a first substantially planar electronic device in the layer having at least first and second terminals comprising an area of the active material layer. A patterned dielectric layer having an exposed surface patterned with at least a first depression arranged over the first terminal is formed over the active material layer. Dielectric material is removed from at least a base of the first depression to expose a first terminal surface and form a hole through the dielectric material to the first terminal. The hole is at least partly filled with electrically conductive material to form an electrical connection to the first terminal. Corresponding structures and electrical circuits are also described and claimed. | 06-21-2012 |
| 20120153503 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 06-21-2012 |
| 20120161330 | DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS - Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. | 06-28-2012 |
| 20120161331 | MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALLY EMBEDDED DIE AND A PROCESS OF FORMING THE SAME - An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate. | 06-28-2012 |
| 20120161332 | METHOD FOR PRODUCING VIAS IN FAN-OUT WAFERS USING DRY FILM AND CONDUCTIVE PASTE, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures. | 06-28-2012 |
| 20120161333 | DEVICE FOR CONNECTING NANO-OBJECTS TO EXTERNAL ELECTRICAL SYSTEMS, AND METHOD FOR PRODUCING SAID DEVICE - Device for connecting nano-objects to external electrical systems, and method for producing the device. | 06-28-2012 |
| 20120161334 | REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE - An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires. | 06-28-2012 |
| 20120161335 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and an insulating layer that is provided on the semiconductor substrate, wherein, in an internal circuit formation region of the insulating layer, a via hole and an interconnect trench that is formed on the via hole and communicates with the via hole are provided, in the via hole and the interconnect trench, a conductor is provided so as to integrally bury the via hole and said interconnect trench, in a dicing region of the insulating layer, a groove portion and an opening that communicates with the groove portion and is formed to cover the groove portion when the semiconductor substrate is seen in plane view from the side of the substrate surface are formed, and in the groove portion and the opening, a conductor is provided so as to integrally bury the groove portion and the opening. | 06-28-2012 |
| 20120168957 | METHOD TO REDUCE DEPTH DELTA BETWEEN DENSE AND WIDE FEATURES IN DUAL DAMASCENE STRUCTURES - A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region. | 07-05-2012 |
| 20120168958 | METHOD AND SYSTEM FOR FORMING DUMMY STRUCTURES IN ACCORDANCE WITH THE GOLDEN RATIO - The present disclosure is directed to method of forming dummy structures in accordance with the golden ratio to reduce dishing and erosion during a chemical mechanical polish. The method includes determining at least one unfilled portion of a die prior to a chemical mechanical planarization and filling the at least one unfilled portion with a plurality of dummy structures, a ratio of the dummy structures to a total area of the unfilled portion being in the range of 36 percent and 39 percent. A die formed in accordance with the method may include a plurality of metal levels and a plurality of regions at each metal level, each region having a plurality of dummy structures formed as golden rectangles. | 07-05-2012 |
| 20120168959 | PACKAGE SUBSTRATE HAVING A THROUGH HOLE AND METHOD OF FABRICATING THE SAME - A package substrate includes a core board having a through hole; a circuit layer formed on the core board; a metallic ring disposed on the core board surrounding a contour of the through hole, the metallic ring having opening portions positioned opposite to each other, making the metallic ring having a disconnected manner; and an embedded component installed in the through hole. When the embedded component is deviated in the through hole to allow the electrodes to be in contact with the metallic ring, the electrodes are prevented from coming into contact with the same section of the metallic ring to thereby avoid short circuit. | 07-05-2012 |
| 20120168960 | MULTI CHIP PACKAGE - The preferred embodiment of the present invention can prevent signal distortions such as stress, or the like, occurring at the time of power delivery due to the difference in the lengths of the metal wires for electrically connecting each of the plurality of semiconductor chips formed on the dual die package substrate. | 07-05-2012 |
| 20120168961 | SEMICONDUCTOR DEVICE - An externally connecting electrode is formed above a semiconductor substrate with interlayer insulation films and disposed in the externally connecting electrode. The externally connecting electrode has a pad metal layer whose upper surface is exposed, a first metal layer formed between the pad metal layer and the semiconductor substrate, and at least two first vias which penetrate the interlayer insulation film and electrically connect the pad metal layer to the first metal layer and are formed in the interlayer insulation film. The maximum interval b between the first vias is larger than the width a of the pad metal layer. | 07-05-2012 |
| 20120168962 | THIN WAFER PROTECTION DEVICE - A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer. | 07-05-2012 |
| 20120168963 | Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors - A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant. | 07-05-2012 |
| 20120175781 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor substrate includes a via-hole that extends from a first surface to a second surface. An electrode pad layer that serves as the bottom of the via-hole is disposed on the second surface. An insulating layer is formed on the first surface of the semiconductor substrate and the sidewall of the via-hole. A metal layer is formed on the first surface of the semiconductor substrate and the sidewall of the via-hole with the insulating layer interposed therebetween and is directly formed on the bottom of the via-hole. An inclined surface is formed on the sidewall of the via-hole such that the bottom of the via-hole has a smaller opening size than the open end of the via-hole. The inclined surface has asperities. | 07-12-2012 |
| 20120175782 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor package and a method of manufacturing the same. a substrate including a first face and a second face, wherein the first and second faces face each other; a first ground pattern disposed on the first face; a second ground pattern disposed on the second face; a plurality of ground via plugs which connect the first ground pattern and the second ground pattern, wherein the plurality of ground via plugs penetrate the substrate; and a first aluminum oxide film interposed between the plurality of ground via plugs, wherein a ground voltage is applied to the plurality of ground via plugs. The semiconductor package may be manufactured using an anodic oxidation process. | 07-12-2012 |
| 20120175783 | SEMICONDUCTOR PACKAGE HAVING AN INTERNAL COOLING SYSTEM - A semiconductor package having an internal cooling system is presented which includes a semiconductor chip and a through-electrode. The semiconductor chip has a circuit section. The through-electrode passes through an upper surface and a lower surface the semiconductor chip. The through-electrode is electrically connected with the circuit section of the semiconductor chip. The through-electrode also has a through-hole for allowing cooling fluid to flow therethrough. | 07-12-2012 |
| 20120175784 | Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound - A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via. | 07-12-2012 |
| 20120175785 | SEMICONDUCTOR DEVICE - In one embodiment, there is provided a semiconductor device that includes: a substrate; a dielectric layer on the substrate; a first ground metal layer embedded in the dielectric layer and having a first DC potential, the first ground metal layer having a first hole therethrough; a first ground patch disposed in the first hole; a second ground metal layer embedded in the dielectric layer such that the dielectric layer is interposed between the first and second ground metal layers in a thickness direction of the dielectric layer, the second ground metal layer having a second DC potential and having a second hole therethrough; a second ground patch disposed in the second hole; a first via which electrically connects the first ground metal layer and the second ground patch; and a second via which electrically connects the second ground metal layer and the first ground patch. | 07-12-2012 |
| 20120181700 | INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS - Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate. | 07-19-2012 |
| 20120181701 | Multilayer Connection Structure and Making Method - A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2 | 07-19-2012 |
| 20120181702 | PHOTOSENSITIVE ADHESIVE COMPOSITION HAVING ALKALI SOLUBLE EPOXY RESIN, AND PATTERNABLE ADHESIVE FILM USING THE SAME - Provided are a photosensitive adhesive composition having an alkali soluble epoxy resin and a patternable adhesive film using the same. The photosensitive adhesive composition has good pattern formability and adhesiveness since the photosensitive adhesive composition includes the alkali soluble epoxy resin. | 07-19-2012 |
| 20120181703 | PATTERNABLE ADHESIVE COMPOSITION, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A patternable adhesive composition including at least one alkali soluble resin including an alkali soluble group and an acryloyl group, at least one radically polymerizable compound, at least one thermosettable compound, and at least one photo-radical initiator. | 07-19-2012 |
| 20120181704 | SEMICONDUCTOR MODULE WITH MICRO-BUFFERS - The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die. | 07-19-2012 |
| 20120181705 | PITCH DIVISION PATTERNING TECHNIQUES - Embodiments of the invention comprise pitch division techniques to extend the capabilities of lithographic techniques beyond their minimum pitch. The pitch division techniques described herein employ additional processing to ensure pitch divided lines have the spatial isolation necessary to prevent shorting problems. The pitch division techniques described herein further employ processing acts to increase the structural robustness of high aspect ratio features. | 07-19-2012 |
| 20120187565 | Device Including Two Semiconductor Chips and Manufacturing Thereof - A device includes a first semiconductor chip with a first contact pad on a first face and a second semiconductor chip with a first contact pad on a first face. The second semiconductor chip is placed over the first semiconductor chip, wherein the first face of the first semiconductor chip faces the first face of the second semiconductor chip. Exactly one layer of an electrically conductive material is arranged between the first semiconductor chip and the second semiconductor chip. The exactly one layer of an electrically conductive material electrically couples the first contact pad of the first semiconductor chip to the first contact pad of the second semiconductor chip. | 07-26-2012 |
| 20120187566 | AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION - A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via. | 07-26-2012 |
| 20120187567 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die. | 07-26-2012 |
| 20120187568 | Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants - A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die. | 07-26-2012 |
| 20120187569 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first insulating film formed on a substrate and including a first area and a second area; a groove formed in the first area of the first insulating film; a plurality of first wiring lines formed in the groove and on the first insulating film, and a second insulating film covering a top surface of the first insulating film and top surfaces of the first wiring lines, the plurality of first wiring lines are parallel to a sidewall of the groove and apart from each other with a first predetermined distance, and the first wiring line closest to the sidewall is apart from the sidewall with a second predetermined distance. | 07-26-2012 |
| 20120187570 | HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS - A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions. | 07-26-2012 |
| 20120187571 | METHOD OF MANUFACTURING PHOTOMASK AND METHOD OF REPAIRING OPTICAL PROXIMITY CORRECTION - A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data. | 07-26-2012 |
| 20120187572 | Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component - A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer. | 07-26-2012 |
| 20120187573 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, AND SEMICONDUCTOR WAFER - A semiconductor wafer having a plurality of interconnect layers, includes a plurality of chip-composing portions, a dicing region separating the chip-composing portions from each other, and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions. | 07-26-2012 |
| 20120193806 | 3D SEMICONDUCTOR DEVICE - A three dimensional semiconductor device includes a first die; and a second die overlaying the first die, wherein said first die comprises signals are selectively coupleable to the second die using Through Silicon Vias. | 08-02-2012 |
| 20120193807 | DRAM CELL BASED ON CONDUCTIVE NANOCHANNEL PLATE - A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask. | 08-02-2012 |
| 20120193808 | BONDED STACKED WAFERS AND METHODS OF ELECTROPLATING BONDED STACKED WAFERS - A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs. | 08-02-2012 |
| 20120193809 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer having a first dielectric block and a first conductive block on the first dielectric block; at least one stacking wafer having a second dielectric block and at least one second conductive block on the second dielectric block, wherein the stacking wafers are bonded to the bottom wafer by an adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer; and a conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the conductive via is positioned within the first conductive block and the second conductive block. | 08-02-2012 |
| 20120193810 | WIRELESS APPARATUS AND WIRELESS SYSTEM - According to one embodiment, a wireless apparatus includes an integrated circuit package, a board having a first layer. The integrated circuit package includes an integrated circuit and at least one antenna. The board has a first surface and a second surface opposite to the first surface, the integrated circuit package is mounted on the board and is electrically connected to the board. The first layer is formed on the second surface, a part of the first layer in a first region is formed of a conductor, the first region is a region on which the antenna is projected in a thickness direction of the board, the part of the first layer in the first region is electrically connected to a particular region included in a third region, the third region is formed of a second region included in the board and the first surface. | 08-02-2012 |
| 20120193811 | INTERPOSER AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole. | 08-02-2012 |
| 20120193812 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. | 08-02-2012 |
| 20120193813 | WIRING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE WIRING STRUCTURE - A wiring structure of a semiconductor device, includes: an insulating layer formed on a base member; a first metal layer covered with the insulating layer; a second metal layer having a plurality of electrode parts which are arranged on the insulating layer to be spaced from each other and which have a thickness larger than the first metal layer, the insulating layer having a plurality of via holes which connect the first metal layer and the plurality of electrode parts; and a plurality of through wiring lines which are located within the plurality of via holes and which electrically connect the plurality of electrode parts to the first metal layer. | 08-02-2012 |
| 20120193814 | IC Device Having Low Resistance TSV Comprising Ground Connection - A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs. | 08-02-2012 |
| 20120193815 | STACKED STRUCTURE OF CHIPS - A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function. | 08-02-2012 |
| 20120199980 | INTEGRATED CIRCUITS HAVING INTERCONNECT STRUCTURES AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING INTERCONNECT STRUCTURES - Integrated circuits and methods for fabricating an integrated circuit are provided. A conductive feature is formed in a semiconductor substrate. A layer of ULK or LK dielectric material is formed overlying the conductive feature. An opening having a sidewall surface is etched through the layer of ULK or LK dielectric material. Damage on the sidewall surface resulting from the etching is removed. An ULK or LK dielectric liner is formed overlying the sidewall surface. The ULK or LK dielectric liner along the bottom of the opening is removed to expose the conductive feature. The opening is filled with a metal fill material contacting the conductive feature. | 08-09-2012 |
| 20120199981 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal. | 08-09-2012 |
| 20120199982 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate; a plurality of interconnect layers disposed at different heights from the semiconductor substrate, each interconnect layer including an interconnection formed therein; and a via formed in a columnar shape extending in the stack direction of the interconnect layers, the via electrically connecting the interconnections of the different interconnect layers, the interconnections including a plurality of intermediate interconnections in contact with the via in the intermediate portion thereof, the intermediate interconnections including a plurality of first type intermediate interconnections passing through the via in a direction perpendicular to the stack direction, and the first type intermediate interconnection of a first one of the interconnect layer and the first type intermediate interconnection of a second one of the interconnect layer are intersecting each other in the via. | 08-09-2012 |
| 20120199983 | ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN - The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage. | 08-09-2012 |
| 20120199984 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING DEVICE - A semiconductor device comprises a material layer including a first surface and a trench with an opening in the first surface. The trench is formed in the material layer. The trench comprises a tapered portion and a vertical portion. The tapered portion is in contact with the opening and comprises a scalloping-forming trench. The vertical portion has a substantially vertical sidewall. A width of the scalloping-forming trench is larger than a width of the vertical portion. | 08-09-2012 |
| 20120199985 | COMPLIANT CORE PERIPHERAL LEAD SEMICONDUCTOR TEST SOCKET - An electrical interconnect for providing a temporary interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the conductive traces into the openings. Conductive structures are electrically coupled to the conductive traces over the openings. The conductive structures are adapted to enhance electrical coupling with the terminals on the IC device. Vias electrically extending through the substrate couple the conductive traces to PCB terminals located proximate a second surface of the substrate. | 08-09-2012 |
| 20120199986 | Semiconductor Device and Manufacturing Method Thereof - A wiring line is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively without increasing the number of manufacturing steps. | 08-09-2012 |
| 20120205814 | DIELECTRIC PROTECTION LAYER AS A CHEMICAL-MECHANICAL POLISHING STOP LAYER - The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry. | 08-16-2012 |
| 20120205815 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a body having a first surface and a second surface facing away from the first surface, and formed with a groove in the first surface. First connection parts may electrically connect a portion of the first surface to a portion of the second surface of the body. Second connection parts may electrically connect a portion of a bottom portion of the groove to a portion of the second surface of the body. A lower device may be disposed in the groove of the body, and have third connection parts that are electrically connected with the second connection parts. An upper device may be disposed on the body and the lower device, and have fourth connection parts that are electrically connected with the first connection parts and the third connection parts. | 08-16-2012 |
| 20120205816 | SEMICONDUCTOR CHIP AND FABRICATING METHOD THEREOF - A semiconductor chip includes a substrate having a front surface and a back surface opposite the front surface, a conductive column part passing through the substrate from the front surface to the back surface, a cavity formed by removing a part of the back surface around an end portion of the conductive column part such that the end portion of the conductive column part protrudes from the cavity, a first insulation layer formed in the cavity such that a portion of the end portion of the conductive column part is exposed, and a back electrode electrically connected to the exposed end portion of the conductive column part. | 08-16-2012 |
| 20120205817 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device including a component substrate of a semiconductor device; electrode pads provided on one surface of the component substrate; a support plate material reinforcing the component substrate; via holes made in the support plate material; a conducting material filled in the via holes; and a joining member interposed between the electrode pads and the conducting material and joining the component substrate and the support plate material. | 08-16-2012 |
| 20120205818 | SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURE FORMED BY PITCH SPLITTING - A hybrid photo-patternable dielectric material is provided that has dual-tone properties with a parabola like dissolution response to radiation. In one embodiment, the hybrid photo-patternable dielectric material includes a composition of at least one positive-tone component including a positive-tone polymer, positive-tone copolymer, or blends of positive-tone polymers and/or positive-tone copolymers having one or more acid sensitive positive-tone functional groups; at least one negative-tone component including a negative-tone polymer, negative-tone copolymer, or blends of negative-tone polymers and/or negative-tone copolymers having one or more acid sensitive negative-tone functional groups; at least one photoacid generator; and at least one solvent that is compatible with the positive-tone and negative-tone components. | 08-16-2012 |
| 20120205819 | DEVICE WITH GAPS FOR CAPACITANCE REDUCTION - A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps. | 08-16-2012 |
| 20120211892 | Semiconductor Device and Method of Forming WLCSP Structure Using Protruded MLP - A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars. | 08-23-2012 |
| 20120211893 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method can include dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole. | 08-23-2012 |
| 20120211894 | JOINING ELECTRODE, METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a joining electrode including: an insulating layer; a recessed portion formed in the insulating layer; a covering layer formed on a side surface and a bottom surface of the recessed portion; and a joining metallic layer formed on the covering layer and having an upper surface protruding from a surface of the insulating layer. | 08-23-2012 |
| 20120211895 | CHIP MODULE AND METHOD FOR PROVIDING A CHIP MODULE - A semiconductor device comprising a semiconductor die that is embedded in a package, wherein the die has a front side comprising a plurality of pads to be bonded to terminals of the package, and wherein a backside of the die is coupled to a backside surface of the package by a thermal bridge. | 08-23-2012 |
| 20120211896 | INTERCONNECTS FOR PACKAGED SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING SUCH DEVICES - Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects. | 08-23-2012 |
| 20120211897 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a multilayer interposer substrate including a power layer as an inner layer; a plurality of connection terminals provided on one surface of the interposer substrate; and a semiconductor chip mounted on the other surface of the interposer substrate. Among power terminals, ground terminals, and signal terminals provided in the semiconductor apparatus, all the power terminals are arranged in one power area and the power area includes only the power terminals. | 08-23-2012 |
| 20120217643 | Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die - A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV. | 08-30-2012 |
| 20120217644 | Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding - A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers. | 08-30-2012 |
| 20120217645 | Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP - A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure. | 08-30-2012 |
| 20120217646 | VIAS BETWEEN CONDUCTIVE LAYERS TO IMPROVE RELIABILITY - Another semiconductor device includes a first layer including a plurality of electrically conductive wires, a second layer, a plurality of non-functional via pads are included in the second layer or between the first layer and the second layer. A dangling via is included within a specified area of the first layer. The dangling vias connect one or more of the wires in the first layer to a respective one of the via pads. | 08-30-2012 |
| 20120217647 | Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer - A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. | 08-30-2012 |
| 20120217648 | THROUGH SUBSTRATE STRUCTURE, DEVICE PACKAGE HAVING THE SAME, AND METHODS FOR MANUFACTURING THE SAME - A through substrate structure, an electronic device package using the same, and methods for manufacturing the same are disclosed. First, a via hole pattern is formed by etching an upper surface of a first substrate. A pattern layer of a second substrate is formed on the first substrate by filling the via hole pattern with a material for the second substrate by reflow. A via hole pattern is formed in the pattern layer of the second substrate by patterning the upper surface of the first substrate. Moreover, a via plug filling the via hole pattern is formed by a plating process, for example, thereby forming a through substrate structure, which can be used in an electronic device package. | 08-30-2012 |
| 20120217649 | DIGITAL INTEGRATED CIRCUIT - An array of functional cells includes a subset of cells powered by at least one supply rail. That supply rail is formed of first segments located on a first metallization level and second segments located on a second metallization level with at least one conductor element extending between the first and second segments to electrically connect successive segments of the supply rail. | 08-30-2012 |
| 20120217650 | SEMICONDUCTOR DEVICE, SENSOR AND ELECTRONIC DEVICE - A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion. | 08-30-2012 |
| 20120217651 | THROUGH SUBSTRATE VIAS - Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal. | 08-30-2012 |
| 20120217652 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed. | 08-30-2012 |
| 20120217653 | SEMICONDUCTOR DEVICE AND NOISE SUPPRESSING METHOD - A first semiconductor chip ( | 08-30-2012 |
| 20120223437 | Semiconductor Device Comprising Metallization Layers of Reduced Interlayer Capacitance by Reducing the Amount of Etch Stop Materials - Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines. | 09-06-2012 |
| 20120223438 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate; a plurality of interconnect layers disposed at different heights from the semiconductor substrate, each interconnect layer including an interconnection formed therein; and a via formed in a columnar shape extending in the stack direction of the interconnect layers, the via electrically connecting the interconnections of the different interconnect layers, the interconnections including an intermediate interconnection in contact with the via in the intermediate portion thereof, and the intermediate interconnection including a first type intermediate interconnection passing through the via in a direction perpendicular to the stack direction and in contact with the via on the top surface, bottom surface, and both side surfaces thereof. | 09-06-2012 |
| 20120223439 | TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA - An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements. | 09-06-2012 |
| 20120223440 | METHOD OF MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT AND THREE-DIMENSIONAL INTEGRATED CIRCUIT APPARATUS - In a three-dimensional integrated circuit apparatus | 09-06-2012 |
| 20120228777 | THROUGH SILICON VIA GUARD RING - The present disclosure relates to forming a plurality of through silicon vias guard rings proximate the scribes streets of a microelectronic device wafer. The microelectronic device wafer includes a substrate wherein the through silicon via guard ring is fabricated by forming vias extending completely through the substrate. The through silicon via guard rings act as crack arresters, such that defects caused by cracks resulting from the dicing of the microelectronic wafer are substantially reduced or eliminated. | 09-13-2012 |
| 20120228778 | SUBSTRATES WITH THROUGH VIAS WITH CONDUCTIVE FEATURES FOR CONNECTION TO INTEGRATED CIRCUIT ELEMENTS, AND METHODS FOR FORMING THROUGH VIAS IN SUBSTRATES - A through via ( | 09-13-2012 |
| 20120228779 | AIR-GAP C4 FLUIDIC I/O INTERCONNECTS AND METHODS OF FABRICATING SAME - An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect. | 09-13-2012 |
| 20120228780 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device including a through via plug and a method of manufacturing the same. In the semiconductor device, since a redistributed interconnection pattern is disposed on a protection film of a convex-concave structure having a protrusion and a recessed portion, the semiconductor device may have improved reliability while preventing a leakage current. In the method of manufacturing the semiconductor device, since an end surface of through via structure is exposed by removing a protection film and an insulating film liner using a selective etching process, damage to the through via structure is minimized, thereby preventing copper contamination in a substrate. | 09-13-2012 |
| 20120228781 | STACKED SEMICONDUCTOR COMPONENT HAVING THROUGH WIRE INTERCONNECT (TWI) WITH COMPRESSED WIRE - A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a compressed wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. | 09-13-2012 |
| 20120235305 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate. | 09-20-2012 |
| 20120235306 | Virtually Substrate-less Composite Power Semiconductor Device - A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness T | 09-20-2012 |
| 20120241972 | LAYOUT SCHEME FOR AN INPUT OUTPUT CELL - An integrated circuit layout for an Input Output (IO) cell includes at least three metal layers. An IO pad is disposed directly over a top metal layer of the at least three metal layers. At least top two metal layers of the at least three metal layers provide a power bus and a ground bus. | 09-27-2012 |
| 20120241973 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a via hole in the substrate, the via hole having a top end and a bottom end with the bottom end is larger than the top end; forming a pad on the substrate, the pad encloses the top end of the via hole; and reflowing a conductive filler having higher volume than the via hole over the via hole, the conductive filler having a protrusion extending from the bottom end and the bottom end entirely overlaps at least one surface of the protrusion. | 09-27-2012 |
| 20120241974 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a lower wiring on the substrate; an inter-layer insulating film covering the lower wiring; first and second upper wirings on the inter-layer insulating film and separated from each other; and a semi-insulating protective film covering the first and second upper wirings, wherein the protective film is not provided in a region right above the lower wiring and between the first upper wiring and the second upper wiring. | 09-27-2012 |
| 20120241975 | METHOD FOR DECOMPOSING LINES OF AN ELECTRONIC CIRCUIT - A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines are interconnected, a space having a width at least equal to the minimum space between two lines separated by one line being left free, in a second direction perpendicular to the first direction, on either side of a minimum rectangle containing the first and the second lines. | 09-27-2012 |
| 20120241976 | SEMICONDUCTOR PACKAGING PROCESS USING THROUGH SILICON VIAS - A microelectronic unit can include a semiconductor element having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts at the front surface and a rear surface remote from the front surface. The semiconductor element can have through holes extending from the rear surface through the semiconductor element and through the contacts. A dielectric layer can line the through holes. A conductive layer may overlie the dielectric layer within the through holes. The conductive layer can conductively interconnect the contacts with unit contacts. | 09-27-2012 |
| 20120241977 | CONFIGURABLE INTERPOSER - A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers. | 09-27-2012 |
| 20120248621 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods. | 10-04-2012 |
| 20120248622 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are formed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods. | 10-04-2012 |
| 20120248623 | VIA NETWORK STRUCTURES AND METHOD THEREFOR - A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact. | 10-04-2012 |
| 20120248624 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer. | 10-04-2012 |
| 20120248625 | SEMICONDUCTOR PACKAGE COMPRISING AN OPTICAL SEMICONDUCTOR DEVICE - A semiconductor package includes a transmissive support plate and includes at least one elongate hole. An integrated circuit semiconductor device is mounted on a rear face of the support plate. The semiconductor device includes first and second optical elements oriented towards the rear face of the support plate, where the first and second optical elements are placed on either side of the elongate hole. An encapsulation material made of an opaque material encapsulates the semiconductor device and fills the elongate hole so as to form an optical insulation partition between the first and second optical elements. A cavity is left, however, between each optical element and a rear face of the support plate. | 10-04-2012 |
| 20120248626 | METHODS FOR PACKAGING MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED USING SUCH METHODS - Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed toward a method for packaging a microelectronic device that includes coupling an active side of a microelectronic die to a surface of a support member. The microelectronic die can have a backside opposite the active side, a peripheral side extending at least part way between the active side and the backside, and at least one through-wafer interconnect. The method can further include applying an encapsulant to cover a portion of the surface of the support member so that a portion of the encapsulant is laterally adjacent to the peripheral side, removing material from a backside of the microelectronic die to expose a portion of at least one through-wafer interconnect, and applying a redistribution structure to the backside of the microelectronic die. | 10-04-2012 |
| 20120248627 | HEAT CONDUCTION FOR CHIP STACKS AND 3-D CIRCUITS - A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities. | 10-04-2012 |
| 20120256319 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A method of manufacturing a semiconductor device, includes: forming a first circuit substrate having a first interconnection; forming a second circuit substrate having a second interconnection; bonding the first circuit substrate to the top surface of the second circuit substrate so as to be stacked facing each other; and performing an etching process of simultaneously removing parts formed on the first interconnection and the second interconnection in a stacked body of the first circuit substrate and the second circuit substrate so as to form a first opening in the top surface of the first interconnection and to form a second opening in the top surface of the second interconnection. The forming of the first circuit substrate includes forming an etching stopper layer on the surface of the first interconnection out of a material having an etching rate lower than that of the first interconnection in the etching process. | 10-11-2012 |
| 20120256320 | WIRING BOARD MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WIRING BOARD - A semiconductor device | 10-11-2012 |
| 20120261826 | TSV STRUCTURE AND METHOD FOR FORMING THE SAME - A TSV structure includes a through via connecting a first side and a second side of a wafer, a conductive layer which fills up the through via, a through via dielectric ring surrounding and directly contacting the conductive layer, a first conductive ring surrounding and directly contacting the through via dielectric ring as well as a first dielectric ring surrounding and directly contacting the first conductive ring and surrounded by the wafer. | 10-18-2012 |
| 20120261827 | THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. | 10-18-2012 |
| 20120261828 | INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL - An interconnect structure includes a patterned and cured dielectric layer located directly on a surface of a patterned permanent antireflective coating. The patterned and cured dielectric layer and the permanent antireflective coating form shaped openings. The shaped openings include an inverse profile which narrows towards a top of the shaped openings. A conductive structure fills the shaped openings wherein the patterned and cured dielectric layer and the permanent antireflective coating each have a conductively filled region. | 10-18-2012 |
| 20120261829 | MIDDLE OF LINE STRUCTURES AND METHODS FOR FABRICATION - A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned dielectric layer and the permanent antireflective coating form openings. The openings correspond with locations of the contact pads. Contact structures are formed in the openings to make electrical contact with the contacts pads such that the patterned dielectric layer and the permanent antireflective coating each have a conductively filled region forming the contact structures. | 10-18-2012 |
| 20120261830 | MEMS DEVICE ETCH STOP - The present disclosure provides a micro-electro-mechanical systems (MEMS) device and a method for fabricating such a device. In an embodiment, a MEMS device includes a substrate, a dielectric layer above the substrate, an etch stop layer above the dielectric layer, and two anchor plugs above the dielectric layer, the two anchor plugs each contacting the etch stop layer or a top metal layer disposed above the dielectric layer. The device further comprises a MEMS structure layer disposed above a cavity formed between the two anchor plugs and above the etch stop layer from release of a sacrificial layer. | 10-18-2012 |
| 20120261831 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to the each of the interconnects. A protrusion is formed at a portion of each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. The portion having the recess is separated from portions on two sides thereof and is separated also from the portion having the protrusion. | 10-18-2012 |
| 20120261832 | Wiring Board, Semiconductor Device, and Method for Manufacturing Wiring Board - A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part. | 10-18-2012 |
| 20120261833 | SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE - A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure. | 10-18-2012 |
| 20120261834 | SEMICONDUCTOR DEVICE - A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed on the substrate, and the TSV penetrates through the substrate. The shelter is disposed on the substrate and at least one part thereof is between the circuit area and the TSV in order to shelter EMI between the TSV and the circuit area. The novel structure prevents the circuits in the circuit area being affected by noise caused by TSV when TSV acts as a power pin. | 10-18-2012 |
| 20120261835 | SEMICONDUCTOR DEVICE - The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented. | 10-18-2012 |
| 20120261836 | ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES - A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer. | 10-18-2012 |
| 20120267788 | Hybrid TSV and Method for Forming the Same - Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion. | 10-25-2012 |
| 20120267789 | VIAS IN POROUS SUBSTRATES - A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction. | 10-25-2012 |
| 20120267790 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction. | 10-25-2012 |
| 20120267791 | MULTI CHIP PACKAGE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE MULTI CHIP PACKAGE - A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes. | 10-25-2012 |
| 20120267792 | SEMICONDUCTOR DEVICE - A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal. | 10-25-2012 |
| 20120267793 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region. | 10-25-2012 |
| 20120267794 | STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME - Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical. | 10-25-2012 |
| 20120273958 | MULTILAYER INTERCONNECT STRUCTURE AND METHOD FOR INTEGRATED CIRCUITS - A multilayer interconnect structure is formed by, providing a substrate ( | 11-01-2012 |
| 20120273959 | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP - A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer. | 11-01-2012 |
| 20120273960 | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Encapsulant with TMV for Vertical Interconnect in POP - A semiconductor device has a carrier or first conductive layer with a plurality of TSV semiconductor die mounted over the carrier or first conductive layer. An encapsulant is deposited around the first semiconductor die and over the carrier or first conductive layer to embed the first semiconductor die. A conductive TMV is formed through the encapsulant. A second conductive layer is formed over a first surface of the encapsulant. A first insulating layer is formed over the first surface of the encapsulant while exposing portions of the second conductive layer. A second insulating layer is formed over the second surface of the encapsulant while exposing portions of the first conductive layer. Alternatively, a first interconnect structure is formed over the first surface of the encapsulant. The carrier is removed and a second interconnect structure is formed over a second surface of the encapsulant. | 11-01-2012 |
| 20120273961 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a plurality of semiconductor chips which are stacked; and an auxiliary semiconductor chip configured to recover and transmit signals of the plurality of semiconductor chips through a plurality of through vias which extend vertically, at a predetermined time interval. | 11-01-2012 |
| 20120273962 | SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device having an air gap, includes: providing a substrate having a first dielectric layer and a second dielectric layer formed thereon successively; forming a mask layer on the second dielectric layer; patterning the first and the second dielectric layer by using the mask layer as a mask so as to form a plurality of grooves; filling a conducting material into the grooves; removing redundant conducting material on the second dielectric layer utill the second dielectric layer is exposed so as to form a plurality of conductive trenches; forming a molecular sieve on the second dielectric layer and the conductive trenches; and removing the second dielectric layer partly or completely by flowing a reactant gas towards the second dielectric layer through the molecular sieve, so as to form an air gap. It is novel and simple to form an air gap through molecular sieve. | 11-01-2012 |
| 20120273963 | MICROELECTRONIC INTERCONNECT SUBSTRATE AND PACKAGING TECHNIQUES - There is provided herein an electrical cross-over comprising: a substrate having an upper surface and a lower surface; an electrically-conductive valve metal area extending from said upper surface to said lower surface; an electrical isolation structure extending from said upper surface to said lower surface and encompassing said electrically conductive area; a first electrically-conductive trace formed on a first electrical isolation area and at least traversing said electrically-conductive crossing area, and at least two second electrically-conductive traces each one of said at least two electrically-conductive traces is at least partially formed on a corresponding second electrical isolation area, wherein said each one of said at least second electrically-conductive traces at least partially extends into said crossing area thereby generating electrical conductivity between said at least two second electrically-conductive traces and said first electrically-conductive trace is electrically isolated from said at least two second electrically-conductive traces. | 11-01-2012 |
| 20120273964 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes: forming an insulating layer above a substrate; forming a recessed section in the insulating layer; forming, on the insulating layer, a mask pattern having a first opening which exposes the recessed section, and a second opening which is arranged outside the first opening and does not expose the recessed section; forming a first conductive member and a second conductive member by respectively depositing a conductive material in the first opening and the second opening; and polishing and removing the first conductive member and the second conductive member on the upper side of the insulating layer so as to leave the first conductive member in the recessed section. | 11-01-2012 |
| 20120273965 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a plurality of memory blocks formed over a substrate including source regions and separated from each other by a slit, a plurality of bit lines coupled to the strings of the memory blocks and disposed over the memory blocks, and source contact lines formed within the slits, coupled to the source regions, respectively, and disposed in a direction to cross the plurality of bit lines. | 11-01-2012 |
| 20120273966 | INTEGRATED CIRCUIT INTERCONNECT STRUCTURE - An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line. | 11-01-2012 |
| 20120273967 | Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and through-hole vias (THV) provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die. | 11-01-2012 |
| 20120273968 | Printed Circuit Board With Coextensive Electrical Connectors And Contact Pad Areas - A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads. | 11-01-2012 |
| 20120273969 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-01-2012 |
| 20120280399 | BUFFER PAD IN SOLDER BUMP CONNECTIONS AND METHODS OF MANUFACTURE - Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer. | 11-08-2012 |
| 20120280400 | ELECTRONIC CIRCUITS INCLUDING PLANAR ELECTRONIC DEVICES - A method for use in the manufacture of an electronic circuit comprising at least one substantially planar electronic device is disclosed. The method comprises:
| 11-08-2012 |
| 20120280401 | SEMICONDUCTOR DEVICE - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. | 11-08-2012 |
| 20120280402 | Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 11-08-2012 |
| 20120280403 | Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 11-08-2012 |
| 20120286428 | FORMATION OF THROUGH-SILICON VIA (TSV) IN SILICON SUBSTRATE - To form a through-silicon via (TSV) in a silicon substrate without using plating equipment or using sputtering equipment or small metal particles, and form an interlayer connection by stacking a plurality of such silicon substrates, a through hole of a silicon substrate is filled using molten solder itself. In detail, solid solder placed above the through hole of the silicon substrate is molten and the molten solder is guided to and filled in the internal space. A metal layer can be deposited on an internal surface of the through hole beforehand, and also an intermetallic compound (IMC) can be formed in a portion other than the metal layer. | 11-15-2012 |
| 20120286429 | Semiconductor Device and Method of Singulating Thin Semiconductor Wafer on Carrier Along Modified Region Within Non-Active Region Formed by Irradiating Energy - A semiconductor device comprises a carrier including an adhesive disposed over the carrier. The semiconductor device further comprises a semiconductor wafer including a plurality of semiconductor die separated by a non-active region. A plurality of bumps is formed over the semiconductor die. The semiconductor wafer is mounted to the carrier with the adhesive disposed around the plurality of bumps. Irradiated energy is applied to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die. The semiconductor wafer is singulated along the modified region by applying stress to the semiconductor wafer. The adhesive is removed from around the plurality of bumps after singulating the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die comprising through silicon vias. The modified region optionally includes a plurality of vertically stacked modified regions. | 11-15-2012 |
| 20120286430 | Method of Producing a Semiconductor Device and Semiconductor Device Having a Through-Wafer Interconnect - A substrate ( | 11-15-2012 |
| 20120286431 | Integrated Circuit Die Stacks Having Initially Identical Dies Personalized With Switches - Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die. | 11-15-2012 |
| 20120292777 | Backside Power Delivery Using Die Stacking - In a stacked die device having an active circuit die bonded on top of a power delivery die using, circuit components formed on the active circuit die are connected to receive power from a coarse network of low resistance, high capacitance power and ground conductors in the power delivery die through conductive via structures or through silicon vias (TSVs) formed in the active circuit die so that primary power is provided from the backside of the active circuit die, leaving more resources and space in the metal interconnect structure for input/output signal routing. | 11-22-2012 |
| 20120292778 | EMBEDDED SEMICONDUCTOR POWER MODULES AND PACKAGES - Disclosed are semiconductor die packages constructed from modules of embedded semiconductor dice and electrical components. In one embodiment, a semiconductor die package comprises a first module and a second module attached to the first module. One or more semiconductor dice are embedded in the first module, and one or more electrical components, such as surface-mounted components, are embedded in the second module. The first module may be formed by a lamination process, and the second module may be formed by a lamination process or a molding process. Patterned metal layers and vias provide electrical interconnections to the package and among the die and components of the package. The second module may be attached to the first module by coupling interconnect lands of separately manufactured modules to one another, or may be directly attached by lamination or molding. | 11-22-2012 |
| 20120292779 | SEMICONDUCTOR STRUCTURE HAVING OFFSET PASSIVATION TO REDUCE ELECTROMIGRATION - A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad. | 11-22-2012 |
| 20120292780 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a package structure is provided. A seed layer is formed on a upper surface of a metal substrate. A patterned dry film layer is formed on a lower surface of the metal substrate and the seed layer. A portion of the seed layer is exposed by the patterned dry film layer. The patterned dry film layer is used as an electroplating mask to electroplate a circuit layer on the portion of the seed layer exposed by the patterned dry film layer. A chip is bonded to and electrically connected to the circuit layer. A molding compound is formed on the metal substrate. The molding compound encapsulates the chip, the circuit layer and the portion of the seed layer. A portion of the metal substrate and a portion of the seed layer are removed so as to expose a portion of the molding compound. | 11-22-2012 |
| 20120292781 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive back side. Conductive vias extend through the integrated circuit between the front and back sides. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive vias and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side. | 11-22-2012 |
| 20120292782 | MICROELECTRONIC DEVICES HAVING CONDUCTIVE THROUGH VIA ELECTRODES INSULATED BY GAP REGIONS - A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed. | 11-22-2012 |
| 20120292783 | PROTECTION LAYER FOR ADHESIVE MATERIAL AT WAFER EDGE - This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies. | 11-22-2012 |
| 20120292784 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a first surface being an element formation surface, and a second surface opposite to the first surface; a through-hole formed to penetrate the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through-hole; a barrier film formed on the inner wall of the through-hole with the insulating film interposed therebetween; and a conductive portion formed to fill the through-hole provided with the insulating film and the barrier film. A gettering site is formed in a portion of the semiconductor substrate around the through-hole at least near a side of the first surface. | 11-22-2012 |
| 20120292785 | Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP - A semiconductor device has a substrate with a cavity formed through first and second surfaces of the substrate. A conductive TSV is formed through a first semiconductor die, which is mounted in the cavity. The first semiconductor die may extend above the cavity. An encapsulant is deposited over the substrate and a first surface of the first semiconductor die. A portion of the encapsulant is removed from the first surface of the first semiconductor die to expose the conductive TSV. A second semiconductor die is mounted to the first surface of the first semiconductor die. The second semiconductor die is electrically connected to the conductive TSV. An interposer is disposed between the first semiconductor die and second semiconductor die. A third semiconductor die is mounted over a second surface of the first semiconductor die. A heat sink is formed over a surface of the third semiconductor die. | 11-22-2012 |
| 20120292786 | INTEGRATED VOID FILL FOR THROUGH SILICON VIA - A microelectronic assembly having a through hole extending through a first wafer (or chip) and a second wafer (or chip) are provided. The first and second wafers (or chips) have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers (or chips) leaving a gap between the confronting faces. A hole is etched in the first wafer (or chip), then material is sputtered to form a wall of material in the gap between wafers (or chips). Etching continues to extend the hole into or through the second wafer (or chip). The hole is filled to form a substantially vertical through silicon conductive via. | 11-22-2012 |
| 20120299190 | METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS - A method for tiling selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and adding tiling features on a metal layer above the selected isolated vias and within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias. | 11-29-2012 |
| 20120299191 | Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected Through Conductive Vias Formed in Encapsulant Around Die - A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers. | 11-29-2012 |
| 20120299192 | PAD STRUCTURE, CIRCUIT CARRIER AND INTEGRATED CIRCUIT CHIP - A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad. | 11-29-2012 |
| 20120299193 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, INTERPOSER, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND INTERPOSER MANUFACTURING METHOD - A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area. | 11-29-2012 |
| 20120299194 | SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES - A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another. | 11-29-2012 |
| 20120299195 | CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD - A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface. | 11-29-2012 |
| 20120306093 | CONVERTING METAL MASK TO METAL-OXIDE ETCH STOP LAYER AND RELATED SEMICONDUCTOR STRUCTURE - A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices. | 12-06-2012 |
| 20120306094 | SIGNAL ROUTING USING THROUGH-SUBSTRATE VIAS - The present description relates to the field of microelectronic devices and the fabrication thereof, wherein through-substrate vias are utilized to route signals between microelectronic integrated circuit components, such as transistors, resistors, capacitors, inductors, and the like, within the microelectronic devices. The through-substrate vias may be used for routing critical signals, which may include, but are not limited to, timing sensitive signal, such as clock signals and the like. | 12-06-2012 |
| 20120306095 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD OF THE SAME - A semiconductor package and a fabrication method are provided. The semiconductor package includes a first substrate including opposite first and second surfaces, a first through electrode penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a second through electrode penetrating the second substrate, an insulating pattern interposed between the second surface of the first substrate and the third surface of the second substrate to at least partially expose the second surface of the first substrate and the third surface of the second substrate, and a connecting pattern disposed in a space defined by the insulating pattern and the first and second substrates to electrically connect the first through electrode with the second through electrode. | 12-06-2012 |
| 20120306096 | METHOD AND MODEL OF CARBON NANOTUBE BASED THROUGH SILICON VIAS (TSV) FOR RF APPLICATIONS - A carbon nanotube (CNT) through silicon via (TSV) for three-dimensional (3D) substrate interconnects is described. TSV technologies provide for high performance and high density 3D packages. The CNT-based TSVs provide for integration of analog, RF and mixed-signal integrated circuits. CNT-based TSV provides superior electrical characteristics as compared to conventional TVs filled with conductive metals. | 12-06-2012 |
| 20120306097 | Semiconductor Device and Method of Forming WLCSP Structure using Protruded MLP - A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars. | 12-06-2012 |
| 20120306098 | Curing Low-k Dielectrics for Improving Mechanical Strength - An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer. | 12-06-2012 |
| 20120306099 | MULTILAYERED BOARD SEMICONDUCTOR DEVICE WITH BGA PACKAGE - In a lamination type semiconductor device, in the case where a power source plane is wrapped by a closed area to prevent the needless radiation from being leaked to the outside of the semiconductor package, a planar conductor for shield having an area intersecting with the respective layers is required. However, in a device for manufacturing the lamination type semiconductor device, a process for manufacturing the above-mentioned conductor cannot be realized ordinarily. In order to make the process possible, it is required to modify or replace a manufacturing apparatus of the semiconductor device, and accordingly a manufacturing cost will be considerably increased. In the present invention, a guard ring is arranged in an surrounding area of a power source plane. The guard ring is connected to a GND plane of another layer through a via. Consequently, the RF radiation occurs between the power source plane and the guard ring. | 12-06-2012 |
| 20120306100 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip. | 12-06-2012 |
| 20120306101 | SEMICONDUCTOR DEVICE - A power line structure is implemented which is capable of securing large interconnection resources for signal lines while suppressing a power supply voltage drop. Power supply potential lines and substrate potential lines are formed in a first wiring layer, and power supply strap lines are formed in a wiring layer that is located below the center of the overall height of the wiring layers. Upper via portions are arranged at a lower density in the direction in which the power supply strap lines extend than lower via portions. | 12-06-2012 |
| 20120313253 | FAN-OUT WLP WITH PACKAGE - A microelectronic package includes a microelectronic unit and a substrate. The microelectronic unit includes a microelectronic element having contacts on a front face. A dielectric material has a first surface substantially flush with the front face of the microelectronic element. Conductive traces have at least portions extending along the front face away from the contacts, at least some of which also extend along the first surface of the dielectric material. Contacts are connected with the traces, at least some of which are disposed at the first surface of the dielectric material. The substrate has first and second opposed surfaces and an edge extending therebetween, the first surface facing the front face of the microelectronic unit, and the second surface having a plurality of terminals thereon configured for electrical connection with at least one external component. Masses of conductive matrix material join the terminals with the redistribution contacts. | 12-13-2012 |
| 20120313254 | COMPACT METAL CONNECT AND/OR DISCONNECT STRUCTURES - Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes. | 12-13-2012 |
| 20120313255 | 3D Integration Microelectronic Assembly For Integrated Circuit Devices And Method Of Making Same - A 3D interposer (and method of making same) that includes a crystalline substrate handler having opposing first and second surfaces, with a cavity formed into the first surface. A layer of insulation material is formed on the surface of the handler that defines the cavity. The cavity is filled with a compliant dielectric material. A plurality of electrical interconnects is formed through the interposer. Each electrical interconnect includes a first hole formed through the crystalline substrate handler extending from the second surface to the cavity, a second hole formed through the compliant dielectric material so as to extend from and be aligned with the first hole, a layer of insulation material formed along a sidewall of the first hole, and conductive material extending through the first and second holes. | 12-13-2012 |
| 20120313256 | Non-Hierarchical Metal Layers for Integrated Circuits - An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch. | 12-13-2012 |
| 20120313257 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - Certain embodiments provide a semiconductor device including a first substrate, a circuit element, a second substrate, a metal layer, and a radiation plate. The circuit element is formed on a front surface of the first substrate and has an electrode. The second substrate has a first face, and is laminated on the first substrate so that the first face of the second substrate faces a front surface of the first substrate. The second substrate has a via hole arranged on the electrode. The metal layer is formed inside of the via hole. The radiation plate is formed on a second face of the second substrate, and is connected to the metal layer. | 12-13-2012 |
| 20120313258 | SEMICONDUCTOR DEVICE HAVING THROUGH SILICON VIAS AND MANUFACTURING METHOD THEREOF - In The semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer. | 12-13-2012 |
| 20120319291 | SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A semiconductor structure includes a dielectric layer disposed over a substrate. A metallic line is disposed in the dielectric layer. A through-silicon-via (TSV) structure continuously extends through the dielectric layer and the substrate. A surface of the metallic line is substantially leveled with a surface of the TSV structure. | 12-20-2012 |
| 20120319292 | STRUCTURE OF A WAFER LEVEL SUBSTRATE FOR CARRYING LIGHT EMITTING DEVICES - Structure and fabricating method of a wafer level substrate for carrying light emitting devices are provided in present invention. The wafer level silicon substrate structure includes a first substrate and a second substrate. A metal line is constructed on a surface of the first substrate according to a predetermined pattern. The predetermined pattern is divided into a plurality of first portions and a plurality of second portions. The second substrate is adhered to the surface of the first substrate. The second substrate has a plurality of through holes. Each of the through holes is respectively corresponding to the first portions. Each of the first portions is adapted to electrically connect with a light emitting device. The provided wafer level substrate structure configured with light emitting devices is capable of providing uniform light output, having better light extraction property, improving process yield, higher production yield and achieving product uniformity. | 12-20-2012 |
| 20120319293 | MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CONTAINING SAME, METHOD OF MANUFACTURING A MULTI-CHANNEL COMMUNICATION PATHWAY IN SAME, AND METHOD OF ENABLING ELECTRICAL COMMUNICATION BETWEEN COMPONENTS OF A STACKED-DIE PACKAGE - A microelectronic device comprises a first surface ( | 12-20-2012 |
| 20120319294 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LASER HOLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; molding a first encapsulation above the substrate; forming a via through the first encapsulation; mounting an integrated circuit above the substrate and between sides of the first encapsulation; and forming a second encapsulation covering the integrated circuit and the first encapsulation. | 12-20-2012 |
| 20120319295 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a circuit structure having a circuit active side and a cavity from the circuit active side; mounting an integrated circuit device in the cavity; forming a base encapsulation, having a base first side facing away from the circuit active side, on the circuit active side, around the integrated circuit device, and in the cavity; forming a first conductive pin, having a first pin height, in the base encapsulation and traversing from the circuit active side to the base first side; forming a second conductive pin, having a second pin height equivalent to the first pin height, in the base encapsulation and traversing from the integrated circuit device to the base first side; and removing a portion of the circuit structure to form a circuit non-active side and expose the integrated circuit device and a base second side. | 12-20-2012 |
| 20120319296 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor chip includes a semiconductor substrate, a via and an insulating layer. The semiconductor substrate has a first major surface and a second major surface on opposite side from the first major surface. The semiconductor substrate is provided with a circuit section including an element and a wiring and a guard ring structure section surrounding the circuit section on the first major surface side. The via is provided in a via hole extending from the first major surface side to the second major surface side of the semiconductor substrate. The insulating layer is provided in a first trench extending from the first major surface side to the second major surface side of the semiconductor substrate. | 12-20-2012 |
| 20120319297 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions. | 12-20-2012 |
| 20120319298 | METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer. | 12-20-2012 |
| 20120319299 | Semiconductor Diode and Method for Producing a Semiconductor Diode - A semiconductor diode has a first semiconductor layer ( | 12-20-2012 |
| 20120326324 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting an organic chip assembly on the base substrate, the organic chip assembly includes providing an assembly integrated circuit embedded in an organic cover, the organic cover having a through via, and the organic chip assembly having a vertical assembly side; forming a molded underfill encapsulating the vertical assembly side, and between the organic chip assembly and the base substrate; and removing a portion of the organic chip assembly and the molded underfill for forming a planarized assembly surface. | 12-27-2012 |
| 20120326325 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate. | 12-27-2012 |
| 20120326326 | Systems and Methods for Producing Flat Surfaces in Interconnect Structures - Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. | 12-27-2012 |
| 20120326327 | VIA STRUCTURE FOR INTEGRATED CIRCUITS - An integrated circuit (IC) having a concentric arrangement of stacked vias is disclosed. The IC includes first and second pluralities of signal lines on first and second metal layers, respectively. The second metal layer is arranged between the first metal layer and a silicon layer. The IC also includes a via structure implemented in a predefined area, and connects each of the first and second pluralities of signal lines to circuitry in the silicon layer through respective first and second pluralities of vias. Each via of the first and second pluralities has a center point that extends along a vertical axis from its respective metal layer to the silicon layer. Centers of each of the second plurality of vias are closer to a perimeter of the predefined area than respective centers of any of the first plurality of vias. | 12-27-2012 |
| 20120326328 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A method for manufacturing a semiconductor device includes providing a substrate having a first surface and a second surface, the second surface is on the opposite side of the substrate facing away from the first surface. The method further includes forming a first portion of an opening by etching a portion of the substrate from the first surface, forming a buffer layer on an inner surface of the first portion, etching a bottom of the buffer layer to expose an area of the underlying substrate, and etching the exposed area of the substrate to form a second portion of the opening. The method also includes performing an isotropic etching on the second portion of the opening to obtain a flask-shaped opening and filling the opening with a filling material. The method also includes partially removing a portion of the second surface and the filling material from the second portion of the opening. | 12-27-2012 |
| 20120326329 | Semiconductor Device and Method of Forming a Conductive Via-in-Via Structure - A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area. | 12-27-2012 |
| 20120326330 | METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT HAVING REDISTRIBUTION LAYER WITH RECESSED CONNECTORS - A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud. | 12-27-2012 |
| 20130001793 | PACKAGE INTERCONNECTS - A method for forming a device is disclosed. A substrate having first and second major surfaces is provided. A stress buffer is formed in the substrate. A through silicon via (TSV) contact is formed between the stress buffer. The stress buffer has a depth less than a depth of the TSV contact. The stress buffer alleviates stress created by the difference in coefficient thermal expansion (CTE) between the TSV contact and the substrate. | 01-03-2013 |
| 20130001794 | IN SITU-BUILT PIN-GRID ARRAYS FOR CORELESS SUBSTRATES, AND METHODS OF MAKING SAME - A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins. | 01-03-2013 |
| 20130001795 | Wafer Level Package and a Method of Forming the Same - A wafer level package is provided. The wafer level package includes at least one chip with at least one electronic component, and at least one connecting chip with at least one through-silicon via, wherein the at least one through-silicon via is electrically coupled to the at least one chip. Further embodiments relate to a method of forming the wafer level package. | 01-03-2013 |
| 20130001796 | SEMICONDUCTOR DEVICE - A semiconductor device including a plug; a lower insulating film surrounding a lower sidewall of the plug; a spacer surrounding an upper sidewall of the plug; and a first interconnection line on the plug, the lower insulating film, and the spacer, the first interconnection line being in contact with an upper surface of the plug, wherein an upper portion of the spacer protrudes higher than the upper surface of the plug. | 01-03-2013 |
| 20130001797 | PACKAGE ON PACKAGE USING THROUGH SUBSTRATE VIAS - A package on package (PoP) employing a through substrate via (TSV) technique in order to reduce the size of a semiconductor chip, has vertically narrow pitches, and forms a higher number of connection terminals. The PoP include a first substrate with a recess disposed in a first surface of the substrate, and a semiconductor chip disposed at the recess. The PoP also includes a semiconductor package connected to the first semiconductor package. The first substrate includes TSVs for electronically connecting the semiconductor package and the semiconductor chip, and routing lines for re-distributing the signals/and or power transmitted via the TSVs. | 01-03-2013 |
| 20130001798 | SEMICONDUCTOR PACKAGE - A semiconductor package having a first semiconductor device including an active surface and a non-active surface opposite to the active surface, and a second semiconductor device having an active surface facing the active surface of the first semiconductor device is provided. Connection terminals are provided on the active surface of the second semiconductor device and first through vias are provided in the first semiconductor device. External terminals providing electrical connection with an external device are provided. The connection terminals comprise center terminals overlapping with the active surface of the first semiconductor device and outer terminals around the center terminals. The center terminals are electrically connected to the external terminals through the first through via. | 01-03-2013 |
| 20130001799 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 01-03-2013 |
| 20130001800 | METHOD OF FORMING PACKAGE-ON-PACKAGE AND DEVICE RELATED THERETO - Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs. | 01-03-2013 |
| 20130001801 | METHODS TO FORM SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURES - Interconnect structures are provided including at least one patterned dielectric layer located on a substrate, wherein said at least one patterned dielectric layer includes differently sized conductive features embedded therein. The differently sized conductive features are laterally adjacent to each other and are located at a same interconnect level. | 01-03-2013 |
| 20130009315 | INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY - A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described. | 01-10-2013 |
| 20130009316 | Apparatus and Methods for Dicing Interposer Assembly - Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods. | 01-10-2013 |
| 20130009317 | FORMING GROUNDED THROUGH-SILICON VIAS IN A SEMICONDUCTOR SUBSTRATE - A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILI) layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate. | 01-10-2013 |
| 20130009318 | STACKED MEMORY LAYERS HAVING MULTIPLE ORIENTATIONS AND THROUGH-LAYER INTERCONNECTS - In one embodiment, an apparatus includes a first memory layer oriented in a first planar orientation, a second memory layer oriented in a second planar orientation, a third memory layer oriented in the first planar orientation; and a connector that is connected to the first memory layer at an electrical contact of the first memory layer and to the third memory layer at an electrical contact of the third memory layer, where the connector is unconnected to the second memory layer. At least one of the electrical contact of the first memory layer and the electrical contact of the third memory layer comprises a through-layer via. The second planar orientation is angularly offset a predetermined number of degrees from the first planar orientation. | 01-10-2013 |
| 20130009319 | Apparatus and Methods for Forming Through Vias - Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed. | 01-10-2013 |
| 20130009320 | Semiconductor package and method of manufacturing the same - There are provided a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part or the substrate part and electrically connected to the semiconductor chip. | 01-10-2013 |
| 20130009321 | SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate. | 01-10-2013 |
| 20130009322 | Through-Substrate Via Having a Strip-Shaped Through-Hole Signal Conductor - A TSV structure suitable for high speed signal transmission includes a metal strip portion that extends through a long and small diameter hole in a substrate. In one example, the metal strip portion is formed by laser ablating away portions of a metal sheath that lines a cylindrical sidewall of the hole, thereby leaving a longitudinal section of metal that is the metal strip portion. A second metal strip portion, that extends in a direction perpendicular to the hole axis, is contiguous with the metal strip portion that extends through the hole such that the two metal strip portions together form a single metal strip. Throughout its length, the single metal strip has a uniform width and thickness and therefore can have a controlled and uniform impedance. In some embodiments, multiple metal strips pass through the same TSV hole. In some embodiments, the structure is a coaxial TSV. | 01-10-2013 |
| 20130009323 | INTERCONNECT STRUCTURE AND METHOD OF FABRICATING - An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material. | 01-10-2013 |
| 20130009324 | UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS - An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. | 01-10-2013 |
| 20130009325 | SEMICONDUCTOR ELEMENT-EMBEDDED SUBSTRATE, AND METHOD OF MANUFACTURING THE SUBSTRATE - A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; | 01-10-2013 |
| 20130015585 | STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERSAANM Kosenko; ValentinAACI Mountain ViewAAST CAAACO USAAGP Kosenko; Valentin Mountain View CA USAANM Savastiouk; SergeyAACI SaratogaAAST CAAACO USAAGP Savastiouk; Sergey Saratoga CA US - A through via contains a conductor ( | 01-17-2013 |
| 20130015586 | DE-SKEWED MULTI-DIE PACKAGES - A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto. | 01-17-2013 |
| 20130015587 | SEMICONDUCTOR DEVICE AND TEST METHODAANM Okutsu; AkihikoAACI YokohamaAACO JPAAGP Okutsu; Akihiko Yokohama JPAANM Saito; HitoshiAACI HachiojiAACO JPAAGP Saito; Hitoshi Hachioji JPAANM Okano; YoshiakiAACI ItabashiAACO JPAAGP Okano; Yoshiaki Itabashi JP - A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion. | 01-17-2013 |
| 20130015588 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region. | 01-17-2013 |
| 20130020716 | SYSTEM AND METHOD TO PROCESS HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN A THERMAL INTERFACE MATERIAL USED IN 3D CHIP STACKS - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. | 01-24-2013 |
| 20130020717 | INTEGRATED CIRCUIT HAVING A STRESSOR AND METHOD OF FORMING THE SAME - An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed. | 01-24-2013 |
| 20130020718 | MEMS Devices and Methods of Forming Same - The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack. | 01-24-2013 |
| 20130020719 | MICROELECTRONIC DEVICES INCLUDING THROUGH SILICON VIA STRUCTURES HAVING POROUS LAYERS - A microelectronic device includes a substrate including a via hole extending therethrough, a porous layer on sidewalls of the via hole, and a conductive via electrode extending through the via hole between the sidewalls thereof. The porous layer includes a plurality of pores therein that reduce a dielectric constant of the porous layer. Related fabrication methods are also discussed. | 01-24-2013 |
| 20130020720 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips. | 01-24-2013 |
| 20130020721 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a through silicon via that penetrates through the semiconductor substrate in a thickness direction thereof, a first insulating region, a second insulating region formed below the first principal surface of the semiconductor substrate, and an isolation region made of an insulating material buried in a second trench formed below the first principal surface of the semiconductor substrate. The first insulating region is made of an insulating material buried in a first groove that surrounds the through silicon via and penetrates through the semiconductor substrate from a first principal surface thereof to a second principal surface thereof. The second insulating region is deeper than the second trench and shallower than the first trench. | 01-24-2013 |
| 20130020722 | SEMICONDUCTOR DEVICE, CIRCUIT SUBSTRATE, AND ELECTRONIC DEVICE - A semiconductor device has a through electrode formed in a through hole which penetrates a Si substrate from one surface to the other surface of the Si substrate, wherein a rectangular electrode pad is provided on the other surface with an insulation film laid between the electrode pad and the other surface, an opening of the through hole on the one surface side is circular, an opening of the through hole on the other surface side is rectangular, and the area of the opening on the other surface side is made smaller than the area of the opening on the one surface side. | 01-24-2013 |
| 20130026641 | CONDUCTOR CONTACT STRUCTURE AND FORMING METHOD, AND PHOTOMASK PATTERN GENERATING METHOD FOR DEFINING SUCH CONDUCTOR CONTACT STRUCTURE - A conductor contact structure includes a conductor line, a dielectric layer and a contact hole. The conductor line includes a first zone and a second zone. The first zone extends along a symmetry axis and is symmetrical with respect to the symmetry axis. The second zone extends along the symmetry axis but is not symmetrical with respect to the symmetry axis. A distance between a first edge of the second zone and the symmetry axis is greater than a distance between a second edge of the second zone and the symmetry axis. A contact hole is formed in the dielectric layer and in communication with the second zone. A diameter of the contact hole is smaller than a distance between the first edge and the second edge of the second zone. | 01-31-2013 |
| 20130026642 | INTEGRATED CIRCUIT PACKAGE INCLUDING A DIRECT CONNECT PAD, A BLIND VIA, AND A BOND PAD ELECTRICALLY COUPLED TO THE DIRECT CONNECT PAD - An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other. | 01-31-2013 |
| 20130026643 | SEMICONDUCTOR DIE ASSEMBLIES, SEMICONDUCTOR DEVICES INCLUDING SAME, AND METHODS OF FABRICATION - Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation. | 01-31-2013 |
| 20130026644 | Photoactive Compound Gradient Photoresist - A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist. | 01-31-2013 |
| 20130026645 | LOW STRESS VIAS - A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region. | 01-31-2013 |
| 20130026646 | PASSIVATED THROUGH WAFER VIAS IN LOW-DOPED SEMICONDUCTOR SUBSTRATES - A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate. | 01-31-2013 |
| 20130026647 | VIA STRUCTURE - A via structure includes at least a first via set and a second via set electrically connected to the first via set. There is at least one via in the first via set and at least one via in the second via set. The via in the first via set has a cross-sectional area which is larger than that of the via in the second via set. | 01-31-2013 |
| 20130026648 | FILM FOR FORMING SEMICONDUCTOR PROTECTION FILM, AND SEMICONDUCTOR DEVICE - Disclosed is a film for forming a semiconductor protection film, which protects a surface of a semiconductor element that is mounted on a structure such as a substrate and is located on the outermost side, the surface being on the reverse side of the surface at which the semiconductor element is mounted on the structure, and the resin composition constituting the film for forming a semiconductor protection film contains (A) a thermosetting component and (B) an inorganic filler. | 01-31-2013 |
| 20130026649 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions. | 01-31-2013 |
| 20130026650 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE STRUCTURE CONFIGURED BY VERTICALLY STACKING SEMICONDUCTOR DEVICES, AND MANUFACTURING METHOD THEREOF - A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer. | 01-31-2013 |
| 20130026651 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 01-31-2013 |
| 20130026652 | SEMICONDUCTOR DEVICE - A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip | 01-31-2013 |
| 20130026653 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property. | 01-31-2013 |
| 20130026654 | Semiconductor Device and Method of Forming Vertical Interconnect in FO-WLCSP Using Leadframe Disposed Between Semiconductor Die - A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe. | 01-31-2013 |
| 20130032944 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC ELEMENTS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact. | 02-07-2013 |
| 20130032945 | SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION - An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures. | 02-07-2013 |
| 20130032946 | LASER-ASSISTED CLEAVING OF A RECONSTITUTED WAFER FOR STACKED DIE ASSEMBLIES - A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving. | 02-07-2013 |
| 20130032947 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package that stably protects an internal semiconductor chip from external shocks, and a method of manufacturing the semiconductor package is disclosed. The semiconductor package includes a first semiconductor chip including a first body layer having a first surface, a second surface, and a lateral surface between the first surface and the second surface, and a first protective layer that exposes an edge portion of the first surface and forms a step difference with the first surface; an encapsulation structure that covers a lateral surface of the first body layer and the edge portion of the first surface so as to encapsulate the first semiconductor chip to have a locking structure; and a first conductive terminal formed on the first body layer through the protective layer. | 02-07-2013 |
| 20130032948 | SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE HAVING GROOVES - A semiconductor device including a substrate having grooves is provided. The semiconductor device includes a substrate including a first surface, a second surface opposite to the first surface, an opening penetrating from the first surface to the second surface, and a first groove formed at a side of the opening, a semiconductor chip formed on the opening at the first surface of the substrate and flip-chip bonded to the first surface by a plurality of first external connection terminals, and a molding unit filling a region between the substrate and the semiconductor chip, filling the opening and filling at least a portion of the first groove, and covering the semiconductor chip. | 02-07-2013 |
| 20130032949 | SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION - An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures. | 02-07-2013 |
| 20130032950 | Techniques for Interconnecting Stacked Dies Using Connection Sites - An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites. | 02-07-2013 |
| 20130037959 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING INTERCONNECT LAYERS HAVING ONE OR MORE OF ELECTRICAL, OPTICAL, AND FLUIDIC INTERCONNECTS THEREIN, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS - Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thinner layer of material on a thicker substrate body, and forming a plurality of through wafer interconnects through the layer of material. A first semiconductor structure may be bonded over the thin layer of material, and at least one conductive feature of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect, an optical interconnect, and a fluidic interconnect may be formed in the transferred layer of material. A second semiconductor structure may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods. | 02-14-2013 |
| 20130037960 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES IN 3D INTEGRATION PROCESSES USING RECOVERABLE SUBSTRATES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods. | 02-14-2013 |
| 20130037961 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device that may prevent an unexposed substrate and generation of bowing profile during a process for forming an open region having a high aspect ratio, and a method for fabricating the semiconductor device. The semiconductor device includes a first material layer formed over a substrate, an open region formed in the first material layer that exposes the first material layer, a second material layer formed on sidewalls of the open region, wherein the second material layer is a compound material including an element of the first material layer, and a conductive layer formed inside the open region. | 02-14-2013 |
| 20130037962 | WAFER LEVEL PACKAGING STRUCTURE WITH LARGE CONTACT AREA AND PREPARATION METHOD THEREOF - A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. | 02-14-2013 |
| 20130037963 | CONDUCTIVE ROUTINGS IN INTEGRATED CIRCUITS USING UNDER BUMP METALLIZATION - An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion. | 02-14-2013 |
| 20130037964 | SEMICONDUCTOR PACKAGE - A semiconductor package substrate may include a first semiconductor chip, a second semiconductor chip, plugs and interconnection terminals. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The first and second semiconductor chips may have corresponding first regions and corresponding second regions. Conductive plugs may be built only in a first region of the first semiconductor chip. Circuitry of the second semiconductor chip may only be electrically connected to the first semiconductor chip through the conductive connectors corresponding to the first regions of the first and second semiconductor chips. | 02-14-2013 |
| 20130037965 | THREE-DIMENSIONAL INTEGRATED CIRCUIT, PROCESSOR, SEMICONDUCTOR CHIP, AND MANUFACTURING METHOD OF THREE-DIMENSIONAL INTEGRATED CIRCUIT - One aspect of the present invention is a three-dimensional integrated circuit | 02-14-2013 |
| 20130043597 | Semiconductor Constructions and Methods of Forming Interconnects - Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts. | 02-21-2013 |
| 20130043598 | BOND PAD STRUCTURE TO REDUCE BOND PAD CORROSION - Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced. | 02-21-2013 |
| 20130043599 | CHIP PACKAGE PROCESS AND CHIP PACKAGE STRUCTURE - Chip package processes and chip package structures are provided. The chip package structure includes a substrate, a chip, an insulating layer, a third patterned conductive layer and an electronic element. The substrate has a first patterned conductive layer. The chip is disposed on the substrate. A second patterned conductive layer of the chip is bonded to the first patterned conductive layer of the substrate. The chip has a first through hole. The insulating layer is disposed on the chip and filled into the first through hole. The insulating layer has a second through hole which passes through the first through hole. The third patterned conductive layer is disposed on the insulating layer and filled into the second through hole to electrically connect to the first patterned conductive layer. The electronic element is disposed on the third patterned conductive layer and electrically connects to the third patterned conductive layer. | 02-21-2013 |
| 20130043600 | BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE - Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods. | 02-21-2013 |
| 20130049217 | SEMICONDUCTOR DEVICE PACKAGING HAVING PRE-ENCAPSULATION THROUGH VIA FORMATION USING DROP-IN SIGNAL CONDUITS - A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications. | 02-28-2013 |
| 20130049218 | SEMICONDUCTOR DEVICE PACKAGING HAVING PRE-ENCAPSULATION THROUGH VIA FORMATION - A method for forming signal conduits before encapsulation for incorporation as through vias in a semiconductor device package is provided. One or more signal conduits are formed through photolithography and metal deposition on a metal film or substrate. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die and other parts of the package. The ends of the signal conduits are exposed and the signal conduits can then be used as through vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package, and electrical contacts of the semiconductor die. Using this method, signal conduits can be provided in a variety of geometric placings in the semiconductor device package. A semiconductor device package including the signal conduits made from the above method is also provided. | 02-28-2013 |
| 20130049219 | Semiconductor Device and Method for Forming the Same - A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate. | 02-28-2013 |
| 20130049220 | Through Silicon Via Keep Out Zone Formation Method and System - Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs. | 02-28-2013 |
| 20130049221 | SEMICONDUCTOR PACKAGE HAVING PLURAL SEMICONDUCTOR CHIPS AND METHOD OF FORMING THE SAME - A semiconductor package includes a first semiconductor chip mounted to a substrate, a first encapsulant covering the first semiconductor chip and have first to fourth sidewall surfaces, and a chip stack mounted to the substrate and disposed on the first encapsulant. The chip stack includes a plurality of second semiconductor chips. A second encapsulant covers the chip stack. The second encapsulant may cover the first sidewall surface of the first encapsulant and expose the third sidewall surface of the first encapsulant. | 02-28-2013 |
| 20130049222 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming select lines extending in a second direction crossing a first direction on a semiconductor substrate, wherein the semiconductor substrate has active regions separated by an isolation layer and extending in the first direction, forming junctions by implanting first impurities into the active regions, respectively, between the select lines and forming a plurality of oxide layers filled between the select lines, forming contact holes exposing the junctions by etching at least one of the plurality of oxide layers, forming junction extensions by implanting second impurities into the active regions of the semiconductor substrate exposed due to loss of the isolation layer while the contact holes are formed, and forming contact plugs for filling the contact holes. | 02-28-2013 |
| 20130056877 | CHIP-HOUSING MODULE AND A METHOD FOR FORMING A CHIP-HOUSING MODULE - A chip-housing module including a carrier configured to carry one or more chips; the carrier including: a first plurality of openings, wherein each opening of the first plurality of openings is separated by a first pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a first range of voltage values to a chip; a second plurality of openings, wherein each opening of the second plurality of openings is separated by a second pre-determined distance, and configured to receive a chip connection for providing a voltage lying within a second range of voltage values to a chip; and wherein a pair of openings consisting of one opening of the first plurality of openings and one opening of the second plurality of openings is separated by a distance different from at least one of the first pre-determined distance and the second pre-determined distance, is provided. | 03-07-2013 |
| 20130056878 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A substrate having a first region and second regions disposed on two sides of the first region; a first group of conductive lines extending from the first region to the second regions on the substrate; a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate; interlayer insulating layers formed over the substrate; insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; and contact plugs contacting second group of conductive line formed in second open regions of the interlayer insulating layer in the second region. | 03-07-2013 |
| 20130056879 | Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer. | 03-07-2013 |
| 20130062773 | CONTACT FOR A NON-VOLATILE MEMORY AND METHOD THEREFOR - A semiconductor device is disclosed that comprises a first non-volatile memory cell, a second non-volatile memory cell, an active region between the first and second memory cells, and an electrically conductive contact touching the active region, wherein the contact has a horizontal cross-section that is at least five percent smaller in a first dimension than in a second dimension. | 03-14-2013 |
| 20130062774 | Semiconductor Device and Method for Forming the Same - A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask. | 03-14-2013 |
| 20130062775 | Strain-Compensating Fill Patterns for Controlling Semiconductor Chip Package Interactions - Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density. | 03-14-2013 |
| 20130062776 | ELECTRICAL TEST STRUCTURE APPLYING 3D-ICS BONDING TECHNOLOGY FOR STACKING ERROR MEASUREMENT - A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern. | 03-14-2013 |
| 20130062777 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Also in a semiconductor integrated circuit device including a copper embedded wiring as a main wiring layer, generally, the uppermost-layer wiring layer is often an aluminum-based pad layer in order to ensure wire bonding characteristics. The aluminum-based pad layer is also generally used as a wiring layer (general intercoupling wiring such as power source wiring or signal wiring). However, such a general intercoupling wiring has a relatively large wiring length. This causes a demerit for the device to be susceptible to damages during a plasma treatment due to the antenna effect, and other demerits. With the present invention, in a semiconductor integrated circuit device including a metal multilayer wiring system having a lower-layer embedded type multilayer wiring layer and an upper-layer non-embedded type aluminum-based pad metal layer, the non-embedded type aluminum-based pad metal layer substantially does not have a power supply ring wiring. | 03-14-2013 |
| 20130062778 | WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE - A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a flat-plate shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a flat-plate shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a first signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode. | 03-14-2013 |
| 20130062779 | BONDING CONTACT AREA ON A SEMICONDUCTOR SUBSTRATE - A bonding contact area on a semiconductor substrate is provided that includes a reinforcing structure having at least one conductive material layer arranged on the semiconductor substrate to receive the patterned reinforcing structure, a metal layer formed as a bonding contact layer with a bonding surface and arranged on a conductive material layer. Whereby, below the bonding surface, an oxide layer having at least about a 2 μm thickness is arranged, which extends beyond the edge of the bonding surface. The reinforcing structure is arranged in the oxide layer, when viewed looking down onto the bonding surface, outside the bonding surface within the oxide layer. | 03-14-2013 |
| 20130069239 | Semiconductor Device and Method of Forming Stacked Semiconductor Die and Conductive Interconnect Structure Through an Encapsulant - A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die. | 03-21-2013 |
| 20130069240 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE MOLD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a top integrated circuit on a first side of the substrate; mounting a bottom integrated circuit on a second side of the substrate; forming a top encapsulation over the top integrated circuit and a bottom encapsulation over the bottom integrated circuit simultaneously; and forming a bottom via through the bottom encapsulation to the substrate. | 03-21-2013 |
| 20130069241 | Semiconductor Device and Method of Forming Semiconductor Package Using Panel Form Carrier - A semiconductor device has a first insulating layer formed over a carrier. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer. Vias are formed through the second insulating layer. A second conductive layer is formed over the second insulating layer and extends into the vias. A semiconductor die is mounted to the second conductive layer. A bond wire is formed between a contact pad on the semiconductor die and the second conductive layer. The second conductive layer extends to a mounting site of the semiconductor die to minimize the bond wire span. An encapsulant is deposited over the semiconductor die. A portion of the first insulating layer is removed to expose the second conductive layer. A portion of the first conductive layer is removed to electrically isolate remaining portions of the first conductive layer. | 03-21-2013 |
| 20130069242 | ARRANGEMENT OF THROUGH-SUBSTRATE VIAS FOR STRESS RELIEF AND IMPROVED DENSITY - A semiconductor device structure for a three-dimensional integrated circuit has a semiconductor substrate having a plurality of through-substrate vias provided in the substrate, wherein three or more of the plurality of through-substrate vias are arranged in a hexagonal packing array with respect to their design-rule circle. | 03-21-2013 |
| 20130069243 | Chip Module and Method for Fabricating a Chip Module - The chip module includes a semiconductor chip having a first contact element on a first main face and a second contact element on a second main face. The semiconductor chip is arranged on a corner in such a way that the first main face of the semiconductor chip faces the carrier. One or more electrical connectors are connected to the carrier and include end faces located in a plane above a plane of the second main face of the semiconductor chip. | 03-21-2013 |
| 20130069244 | RECTANGULAR VIA FOR ENSURING VIA YIELD IN THE ABSENCE OF VIA REDUNDANCY - A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication. | 03-21-2013 |
| 20130069245 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface, a wiring layer formed on the first surface of the first sealing insulating layer, an insulating layer formed on the wiring layer, a second semiconductor chip mounted on the second surface of the first sealing insulating layer, and a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip. | 03-21-2013 |
| 20130069246 | METHODS OF FORMING ELECTRONIC DEVICES - Methods of forming electronic devices are provided. The methods involve alkaline treatment of photoresist patterns and allow for the formation of high density resist patterns. The methods find particular applicability in semiconductor device manufacture. | 03-21-2013 |
| 20130075920 | Multilayer Connection Structure and Making Method - An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers. | 03-28-2013 |
| 20130075921 | Forming Packages Having Polymer-Based Substrates - A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via. | 03-28-2013 |
| 20130075922 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SUBSTRATE EMBEDDED DUMMY-DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle. | 03-28-2013 |
| 20130075923 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation. | 03-28-2013 |
| 20130075924 | Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP - A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant. | 03-28-2013 |
| 20130075925 | SEMICONDUCTOR DEVICE - A semiconductor device is free from degradation of characteristics attributable to a manufacturing process thereof and its characteristics are hardly affected by changes in electric potentials of bonding pads. The semiconductor device | 03-28-2013 |
| 20130075926 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector. | 03-28-2013 |
| 20130075927 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed. | 03-28-2013 |
| 20130075928 | INTEGRATED CIRCUIT AND METHOD OF MAKING - Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via. | 03-28-2013 |
| 20130075929 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film. | 03-28-2013 |
| 20130075930 | SEMICONDUCTOR SUBSTRATE, ELETRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor substrate includes a vertical conductor and an insulating layer. The vertical conductor includes a metal/alloy component of a nanocomposite crystal structure and is filled in a vertical hole formed in the semiconductor substrate along its thickness direction. The insulating layer is formed around the vertical conductor in a ring shape and includes nm-sized silica particles and a nanocrystal or nanoamorphous silica filling up a space between the silica particles to provide a nanocomposite structure along with the silica particles. | 03-28-2013 |
| 20130075931 | BOND PAD STRUCTURE - A bond pad structure for an integrated circuit chip package is disclosed. The bond pad structure includes a top metal layer, a patterned metal layer and an interconnection structure. The patterned metal layer is formed below the top metal layer and includes an annular metal layer and a plurality of metal blocks evenly arranged at a central area of the annular metal layer; the patterned metal layer is connected to the top metal layer through both the annular metal layer and the metal blocks. The interconnection structure is formed below the patterned metal layer and is connected to patterned metal layer only through the annular metal layer. By using the above structure, active or passive devices can be disposed under the bond pad structure and will not be damaged by package stress. An integrated circuit employing the above bond pad structure is also disclosed. | 03-28-2013 |
| 20130075932 | Power Semiconductor Module with Integrated Thick-Film Printed Circuit Board - A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 μm. | 03-28-2013 |
| 20130075933 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant. | 03-28-2013 |
| 20130082394 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package. | 04-04-2013 |
| 20130082395 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
| 20130082396 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
| 20130082397 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region. | 04-04-2013 |
| 20130082398 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region. | 04-04-2013 |
| 20130082399 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes. | 04-04-2013 |
| 20130082400 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A HEMT has a compound semiconductor layer, a protection film which has an opening and covers an upper side of the compound semiconductor layer, and a gate electrode which fills the opening and has a shape riding on the compound semiconductor layer, wherein the protection film has a stacked structure of a lower insulating film not containing oxygen and an upper insulating film containing oxygen, and the opening includes a first opening formed in the lower insulating film and a second opening formed in the upper insulating film and wider than the first opening, the first opening and the second opening communicating with each other. | 04-04-2013 |
| 20130082401 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers. | 04-04-2013 |
| 20130082402 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole. | 04-04-2013 |
| 20130087925 | Packaging Structures of Integrated Circuits - A chip includes a dummy connector disposed at a top surface of the chip. A seal ring encircles a region directly underlying the dummy connector, with the region overlapping the dummy connector. | 04-11-2013 |
| 20130087926 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device. | 04-11-2013 |
| 20130087927 | MULTIMEDIA PROVIDING SERVICE - Provided is a semiconductor device of higher density, thin thickness and low cost not plagued with low reliability ascribable to concentration of internal stress in an ultimate product. The semiconductor device includes a semiconductor element, and a support substrate arranged on a surface of the semiconductor element opposite to its surface provided with a pad. The support substrate is wider in area than the semiconductor element. The semiconductor device also includes a burying insulating layer on the support substrate for burying the semiconductor element in it, and a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area above the outer periphery of the semiconductor element for augmenting mechanical strength of the burying insulating layer and the fan-out interconnection (FIG. | 04-11-2013 |
| 20130087928 | Semiconductor Device and Method of Forming Conductive TSV With Insulating Annular Ring - A semiconductor wafer has an insulating layer formed over an active surface of the wafer. A conductive layer is formed over the insulating layer. A first via is formed from a back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. A conductive material is deposited in the first via to form a conductive TSV. An insulating material can be deposited in the first via to form an insulating core within the conductive via. After forming the conductive TSV, a second via is formed around the conductive TSV from the back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. An insulating material is deposited in the second via to form an insulating annular ring. The conductive via can be recessed within or extend above a surface of the semiconductor die. | 04-11-2013 |
| 20130093097 | Package-On-Package (PoP) Structure and Method - A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL. | 04-18-2013 |
| 20130093098 | THROUGH SUBSTRATE VIA STRUCTURES AND METHODS OF FORMING THE SAME - The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill. | 04-18-2013 |
| 20130093099 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having first and second chips stacked upon each other includes first, second and third through vias positioned on a same vertical lines in the first and second chips and formed through the first and second chips. A first input/output circuit connected with the second through via of the first chip. A second input/output circuit connected with the second through via of the second chip. The second through via of the second chip is connected with the first through via of the first chip. | 04-18-2013 |
| 20130093100 | Semiconductor Device and Method of Forming Conductive Pillar Having an Expanded Base - A semiconductor device has a first semiconductor die and conductive vias in the first semiconductor die. The conductive vias can be formed by extending the vias partially through a first surface of the first semiconductor die. A portion of a second surface of the first semiconductor die is removed to expose the conductive vias. A plurality of conductive pillars is formed over the first surface the first semiconductor die. The conductive pillars include an expanded base electrically connected to the conductive vias. A width of the expanded base of the conductive pillars is greater than a width of a body of the conductive pillars. A conductive layer is formed over a second surface of the first semiconductor die. The conductive layer is electrically connected to the conductive vias. A second semiconductor die is mounted to the first semiconductor die with a second conductive pillar having an expanded base. | 04-18-2013 |
| 20130099387 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts. | 04-25-2013 |
| 20130099388 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes a first semiconductor chip having one surface, and an other surface which faces away from the one surface, and first through electrodes which pass through the one surface and the other surface and project out of the other surface; a second semiconductor chip stacked over the one surface of the first semiconductor chip and having second through electrodes which are connected with the first through electrodes; a heat dissipation member disposed over the second semiconductor chip; and a first heat absorbing member disposed to face the other surface of the first semiconductor chip and defined with through holes into which projecting portions of the first through electrodes are inserted. | 04-25-2013 |
| 20130099389 | MULTILAYERED CIRCUIT TYPE ANTENNA PACKAGE - A multilayered antenna package including: a radio frequency integrated circuit (RFIC) interface layer that is configured to transmit a radio frequency (RF) signal; a first dielectric layer that is disposed on the RFIC interface layer; a coplanar waveguide layer that is disposed on the first dielectric layer and is configured to receive the RF signal transmitted by RFIC layer; a second dielectric layer disposed on the coplanar waveguide layer; and an antenna portion that is disposed on the second dielectric layer and is configured to irradiate a signal that is transmitted from the coplanar waveguide layer. | 04-25-2013 |
| 20130099390 | ELECTRONIC DEVICE - In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer. | 04-25-2013 |
| 20130105986 | SEMICONDUCTOR DEVICE WITH VIAS ON A BRIDGE CONNECTING TWO BUSES | 05-02-2013 |
| 20130105987 | LAMINATE INTERCONNECT HAVING A COAXIAL VIA STRUCTURE | 05-02-2013 |
| 20130105988 | SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP WITH THROUGH OPENING | 05-02-2013 |
| 20130105989 | Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect | 05-02-2013 |
| 20130105990 | SEMICONDUCTOR DEVICE | 05-02-2013 |
| 20130113110 | Semiconductor Structure Having Lateral Through Silicon Via And Manufacturing Method Thereof - The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad. | 05-09-2013 |
| 20130113111 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device and methods directed toward preventing a leakage current between a contact plug and a line adjacent to the contact plug, and minimizing capacitance between adjacent lines. | 05-09-2013 |
| 20130113112 | SEMICONDUCTOR DEVICE - A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect. | 05-09-2013 |
| 20130113113 | WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE, METHOD OF FORMING THE WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug. | 05-09-2013 |
| 20130119552 | Method for Forming Chip-on-Wafer Assembly - A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip. | 05-16-2013 |
| 20130119553 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor package including an electrical device having a first lateral surface; and a core substrate including a cavity in which the electrical device is positioned, wherein the core substrate is inclined in a thickness direction of the core substrate and has a second lateral surface that defines the cavity. | 05-16-2013 |
| 20130119554 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME - There is provided a semiconductor device comprising, a first metal pattern formed at a first metal level and extending in a first direction, a second metal pattern formed at the first metal level, extending in a second direction that is different than the first direction, and disposed on a side of the first metal pattern to be separated from the first metal pattern, a first via structure formed on the first metal pattern, a third metal pattern formed at a second metal level that is different than the first metal level and electrically connected to the first metal pattern by the first via structure, and a first pad electrically connected to the first metal pattern and a second pad electrically connected to the third metal pattern. | 05-16-2013 |
| 20130119555 | Through-Package-Via (TPV) Structures On Inorganic Interposer And Methods For Fabricating Same - The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses ways in that a stress relief barrier can be used to reduce the effects of stress caused by the different CTEs while also, in some applications, acting as an adhesion promoter between the metallization and the interposer. The stress relief barrier acts to absorb some of the stress caused by the different CTEs and promotes better adhesion for the conductive metal layer, thus helping to increase reliability while also providing for smaller designs. | 05-16-2013 |
| 20130119556 | CHIP PACKAGE - A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively. | 05-16-2013 |
| 20130119557 | SYSTEMS COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - Two systems including: a first system including a first die connected to a second die; and a second system including a third die connected to a fourth die; wherein the connected includes at least one through silicon via (TSV), and wherein the first die is substantially the same as the third die, and the second die is substantially different than the fourth die. | 05-16-2013 |
| 20130119558 | Stacked Semiconductor Package - Provided is a stacked semiconductor package. The stacked semiconductor package of the present invention comprises: a substrate unit, which includes a connection substrate electrically connecting a first substrate having a contact pad and a second substrate having a contact pad; a first chip laminate at which a plurality of first semiconductor chips are stacked in multi-steps on the first substrate; a second chip laminate at which a plurality of second semiconductor chips are stacked in multi-steps on the second substrate; a first conductive wire which electrically connects a first bonding pad of the first semiconductor chip and the contact pad of the first substrate, a second conductive wire which electrically connects a second bonding pad of the second semiconductor chip and the contact pad of the second substrate, and a bonding unit which has a contact adhesive layer having a certain thickness, which is disposed between the first semiconductor chip in the top layer of the first chip laminate and the second semiconductor chip in the top layer of the second chip laminate, and which vertically stacks and bonds the first chip laminate and the second chip laminate. | 05-16-2013 |
| 20130119559 | Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die - A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers. | 05-16-2013 |
| 20130119560 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 05-16-2013 |
| 20130127064 | METHOD AND APPARATUS TO IMPROVE RELIABILITY OF VIAS - In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density. | 05-23-2013 |
| 20130127065 | CMUT DEVICES AND FABRICATION METHODS - Capacitive micromachined ultrasonic transducer (“CMUT”) devices and fabrication methods are provided. The CMUT devices can include integrated circuit devices utilizing direct connections to various CMOS electronic components. The use of integrated connections can reduce overall package size and improve functionality for use in ultrasonic imaging applications. CMUT devices can also be manufactured on multiple silicon chip layers with each layer connected utilizing through silicon vias (TSVs). External power connections can be provided if high biasing voltages are required. Forward and side looking CMUT arrays can be manufactured for use in a variety of ultrasound technologies. | 05-23-2013 |
| 20130127066 | Integrated Circuit Including Interconnect Levels - An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area. | 05-23-2013 |
| 20130127067 | THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. | 05-23-2013 |
| 20130134600 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and method for manufacturing the same. The semiconductor device includes a substrate, a dielectric layer, a metal layer, an interconnection metal and an insulation circular layer. The substrate has at least one through hole. The dielectric layer is disposed adjacent to the substrate. The metal layer is disposed adjacent to the dielectric layer. The interconnection metal is disposed in the at least one through hole. An insulation circular layer surrounds the interconnection metal, wherein the insulation layer has an upper surface and the upper surface contacts the dielectric layer. Whereby, the metal layer can be electrically connected to another surface of the substrate through the interconnection metal. | 05-30-2013 |
| 20130134601 | SEMICONDUCTOR DEVICE HAVING SHIELDED CONDUCTIVE VIAS AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device having a shielding layer and a method for making the same. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer. | 05-30-2013 |
| 20130134602 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 05-30-2013 |
| 20130134603 | Semiconductor Devices Including Protected Barrier Layers - Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern. | 05-30-2013 |
| 20130140708 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized. | 06-06-2013 |
| 20130140709 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads | 06-06-2013 |
| 20130140710 | SEMICONDUCTOR DEVICE INCLUDING A PROTECTIVE FILM - A semiconductor device includes a semiconductor chip having a wire and a passivation film formed on the outermost surface with an opening partially exposing the wire. A resin layer is stacked on the semiconductor chip and provided with a through-hole in a position opposed to a portion of the wire facing the opening. A pad is formed on a peripheral portion of the through-hole in the resin layer and in the through-hole so that an external connection terminal is arranged on the surface thereof. The peripheral portion of the resin layer is formed more thickly than the remaining portion of the resin layer other than the peripheral portion. | 06-06-2013 |
| 20130140711 | SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via. | 06-06-2013 |
| 20130147051 | METHOD OF PROTECTING AGAINST VIA FAILURE AND STRUCTURE THEREFOR - A method is for forming a decoy via and a functional via. The method includes forming the functional via between a metal portion of a first interconnect layer and a portion of a second interconnect layer. The method further includes forming the decoy via in a protection region between the metal portion of the first interconnect layer and a metal portion of the third interconnect level. | 06-13-2013 |
| 20130147052 | OFFSET OF CONTACT OPENING FOR COPPER PILLARS IN FLIP CHIP PACKAGES - An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die. | 06-13-2013 |
| 20130147053 | Semiconductor Device and Method of Making Single Layer Substrate with Asymmetrical Fibers and Reduced Warpage - A semiconductor device includes a first carrier having a first resin disposed over the first carrier. A fabric is disposed over the first resin. A second resin is formed over the first resin and around the fabric to form an asymmetrical pre-impregnated (PPG) substrate. The first carrier is removed. A second carrier is provided and a first conductive layer is formed over the second carrier. A portion of the first conductive layer is removed. The first conductive layer is transferred from the second carrier to the first resin. The first conductive layer is oriented asymmetrically such that the first conductive layer is offset with respect to the fabric to minimize warpage. The second carrier is removed. A via is formed through the second resin and fabric to expose the first conductive layer. A second conductive layer formed in the via over the first conductive layer. | 06-13-2013 |
| 20130147054 | Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP - A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. | 06-13-2013 |
| 20130147055 | Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV through Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings. | 06-13-2013 |
| 20130147056 | RESIZED WAFER WITH A NEGATIVE PHOTORESIST RING AND DESIGN STRUCTURES THEREOF - A resized wafer using a negative photoresist ring, methods of manufacture and design structures thereof are disclosed. The method includes forming a ring within a radius of a wafer. The method also includes patterning a photoresist formed on the wafer, by exposing the photoresist to energy. Additionally, the method includes forming troughs in a substrate of the wafer based on the patterning of the photoresist, wherein the ring blocks formation of the troughs underneath the ring. The method also includes filling the troughs with a metal and resizing the wafer at an area of the ring. | 06-13-2013 |
| 20130147057 | THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT - Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in | 06-13-2013 |
| 20130147058 | CHIP PACKAGE AND CHIP PACKAGE METHOD - A chip package includes a substrate, a pad positioned on the substrate, a base board, at least one adhesive layer and at least one chip. The base board is positioned on the pad. At least one mounting hole is defined through the base board. The at least one adhesive layer is received in the at least one mounting hole. The at least one chip is received in the at least one mounting hole and adhere to the pad via the at least one adhesive layer. | 06-13-2013 |
| 20130147059 | CHIP-TO-WAFER BONDING METHOD AND THREE-DIMENSIONAL INTEGRATED SEMICONDUCTOR DEVICE - A chip-to-wafer bonding method and a three-dimensional integrated semiconductor device are provided. The method comprises providing a chip and a wafer having a bonding region of the same size and shape as the chip; preparing hydrophilic areas and hydrophobic areas on the chip; preparing in the bonding region hydrophilic areas and hydrophobic areas respectively corresponding to the hydrophilic and hydrophobic areas on the chip; adding a liquid drop onto the hydrophilic areas in the bonding region; and pre-aligning and placing the chip on the bonding region of the wafer, such that the hydrophilic areas on the chip each contacts the corresponding hydrophilic area in the bonding region via the liquid. The sum of perimeters of the hydrophilic areas on the chip is larger than a perimeter of the chip. The sum of perimeters of the hydrophilic areas in the bonding region is larger than a perimeter of the bonding region. | 06-13-2013 |
| 20130147060 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes and extend laterally in opposite directions so as to define a zigzag arrangement together. | 06-13-2013 |
| 20130147061 | Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices - An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias. | 06-13-2013 |
| 20130154105 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE TRACE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation. | 06-20-2013 |
| 20130154106 | Stacked Packaging Using Reconstituted Wafers - An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement. | 06-20-2013 |
| 20130154107 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COUPLING FEATURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature. | 06-20-2013 |
| 20130154108 | Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP - A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole. | 06-20-2013 |
| 20130154109 | METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE - The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage. | 06-20-2013 |
| 20130154110 | DIRECT WRITE INTERCONNECTIONS AND METHOD OF MANUFACTURING THEREOF - A semiconductor device package having direct write interconnections and method of manufacturing thereof is disclosed. A device package is formed by providing a substrate structure, attaching at least one device to the substrate structure that each include a substrate and one or more connection pads formed on the substrate, depositing a dielectric layer over the at least one device and onto the substrate structure by way of a direct write application, the dielectric layer including vias formed therethrough, and forming an interconnect structure on the dielectric layer that is electrically coupled to the connection pads of the at least one device, the interconnect structure extending through the vias in the dielectric layer so as to be connected to the connection pads. | 06-20-2013 |
| 20130154111 | SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE AND METHOD OF MANUFACTURING THE SAME AND STACKED PACKAGE INCLUDING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a wafer having an upper surface and a lower surface, circuit layers formed on the upper surface and the lower surface of the wafer, respectively, and a through electrode formed to penetrate the wafer is presented. The through electrode can be configured to electrically coupled the circuit layers formed on the upper surface and the lower surface of the wafer. The semiconductor device can be stacked to form a stacked package. | 06-20-2013 |
| 20130154112 | Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof - The disclosure is related to a substrate suitable for use in a stack of interconnected substrates, comprising: a base layer having a front side and a back side surface parallel to the plane of the base layer; one or more interconnect structures, each of said structures comprising: a via filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer, and on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via; characterized in that the backside surface of said base layer comprises one or more isolation ring trenches each of said trenches surrounding one or more of said interconnect structures. The disclosure is equally related to methods for producing said substrates and stacks of substrates. | 06-20-2013 |
| 20130154113 | PERFORATION PATTERNED ELECTRICAL INTERCONNECTS - This disclosure describes systems and methods for increasing the usable surface area of electrical contacts within a device, such as a thin film solid state device, through the implementation of electrically conductive interconnects. Embodiments described herein include the use of a plurality of electrically conductive interconnects that penetrate through a top contact layer, through one or more multiple layers, and into a bottom contact layer. The plurality of conductive interconnects may form horizontal and vertical cross-sectional patterns. The use of lasers to form the plurality of electrically conductive interconnects from reflowed layer material further aids in the manufacturing process of a device. | 06-20-2013 |
| 20130161824 | Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief - A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer. | 06-27-2013 |
| 20130161825 | THROUGH SUBSTRATE VIA STRUCTURE AND METHOD FOR FABRICATING THE SAME - A through substrate via (TSV) structure is provided, including: a substrate; an opening formed in a portion of the semiconductor substrate; a dielectric layer formed on the sidewall of the opening; a conductive pillar formed inside the opening; and at least a portion of the dielectric layer is removed to form void. Also provided is a method for fabricating a through substrate via (TSV) structure. | 06-27-2013 |
| 20130161826 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure. | 06-27-2013 |
| 20130161827 | SEMICONDUCTOR CHIP HAVING PLURAL PENETRATION ELECTRODE PENETRATING THERETHROUGH - Disclosed herein is a semiconductor chip that includes: a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and a wiring configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode. | 06-27-2013 |
| 20130161828 | TSV VIA PROVIDED WITH A STRESS RELEASE STRUCTURE AND ITS FABRICATION METHOD - A TSV via structure comprising an upper part made on the side of the front face of a substrate in which electronic components are located and a lower part with height and cross-section smaller than the height and cross-section the upper part, the arrangement of the connection element in the substrate being such that it releases stresses generated by the different materials of said structure. | 06-27-2013 |
| 20130161829 | WAFER-TO-WAFER STACK WITH SUPPORTING POST - A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip. | 06-27-2013 |
| 20130161830 | SEMICONDUCTOR CHIPS HAVING REDISTRIBUTED POWER/GROUND LINES DIRECTLY CONNECTED TO POWER/GROUND LINES OF INTERNAL CIRCUITS AND METHODS OF FABRICATING THE SAME - Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided. | 06-27-2013 |
| 20130168869 | Metal Layout of an Integrated Power Transistor and the Method Thereof - The present disclosure discloses a metal layout of an integrated power transistor. The metal layout comprises a 1 | 07-04-2013 |
| 20130168870 | DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - A method for manufacturing an electronic interconnect device is described, the method comprising: providing an electronic members each having one or more electrical contacts on a first member side thereof; providing a carrier having a carrier base and having sets of one or more electrically conductive projections on a surface of the carrier base; attaching the electronic members with the corresponding contacts thereof to the respective set of projections to thereby electrically connect the one or more electrical contacts of the respective chip with the corresponding one or more electrically conductive projections of the respective set; encapsulating exposed portions of the electronic member with an encapsulating material to form an encapsulation. | 07-04-2013 |
| 20130168871 | SEMICONDUCTOR PACKAGE WITH PACKAGE ON PACKAGE STRUCTURE - A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated. | 07-04-2013 |
| 20130168872 | VIA ARRANGEMENT AND SEMICONDUCTOR DEVICE WITH THE VIA ARRANGEMENT - A semiconductor device may include a first line of vias including a first via and a second via immediately adjacent to the first via. The semiconductor device may further include a second line of vias arranged immediately adjacent to and parallel to the first line of vias, the second line of vias including a third via immediately adjacent to the first via and the second via, the second line of vias further including a fourth via immediately adjacent to the third via, the first via, and the second via. The shortest distance between the second via and the fourth via may be greater than the shortest distance between the first via and the second via. | 07-04-2013 |
| 20130168873 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A power semiconductor device and a manufacturing method thereof, the power semiconductor device including a plurality of first electrodes and a plurality of second electrodes, a plurality of first via electrodes on a first insulating layer and contacting the plurality of first electrodes, a plurality of second via electrodes on the first insulating layer and contacting the plurality of second electrodes, a first electrode pad contacting the plurality of first via electrodes, a second electrode pad contacting the plurality of second via electrodes, a plurality of third via electrodes on a second insulating layer and contacting the first electrode pad, a plurality of fourth via electrodes on the second insulating layer and contacting the second electrode pad, a third electrode pad contacting the plurality of third via electrodes, and a fourth electrode pad contacting the plurality of fourth via electrodes. | 07-04-2013 |
| 20130175697 | Interlevel Dielectric Stack for Interconnect Structures - A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity. | 07-11-2013 |
| 20130175698 | Integrated Circuit Constructions Having Through Substrate Vias And Methods Of Forming Integrated Circuit Constructions Having Through Substrate Vias - An integrated circuit construction includes a stack of two or more integrated circuit substrates. At least one of the substrates includes through substrate vias (TSVs) individually comprising opposing ends. A conductive bond pad is adjacent one of the ends on one side of the one substrate. A conductive solder mass is adjacent the other end projecting elevationally on the other side of the one substrate. Individual of the solder masses are bonded to a respective bond pad on an immediately adjacent substrate of the stack. Epoxy flux surrounds the individual solder masses. An epoxy material different in composition from the epoxy flux surrounds the epoxy flux on the individual solder masses. Methods of forming integrated circuit constructions are also disclosed. | 07-11-2013 |
| 20130175699 | STACKABLE MICROELECTRONIC PACKAGE STRUCTURES - A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package. | 07-11-2013 |
| 20130175700 | SEMICONDUCTOR DIE CONNECTION SYSTEM AND METHOD - A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate. | 07-11-2013 |
| 20130175701 | Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection - A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers. | 07-11-2013 |
| 20130175702 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip. | 07-11-2013 |
| 20130175703 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an electric conduction portion having a flat plate shape, a semiconductor element being arranged vertically over the electric conduction portion and being electrically connected thereto, a casing whose lower portion of an inner wall has a coupling portion coupled with a circumferential edge portion of the electric conduction portion and whose upper portion of the inner wall surrounds the whole circumference of the electric conduction portion and a sealing material that vertically downwardly encapsulates the semiconductor element and the electric conduction portion. The electric conduction portion and the casing are integrally molded, and a space having a shape coupled to a circumferential edge portion of the electric conduction portion is provided in the lower portion of the inner wall of the casing as the coupling portion. | 07-11-2013 |
| 20130181354 | Semiconductor Interposer Having a Cavity for Intra-Interposer Die - A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate. | 07-18-2013 |
| 20130181355 | Support Structure for TSV in MEMS Structure - An embodiment is a method for forming a microelectromechanical system (MEMS) device. The method comprises forming a MEMS structure over a first substrate, wherein the MEMS structures comprises a movable element; forming a bonding structure over the first substrate; and forming a support structure over the first substrate, wherein the support structure protrudes from the bonding structure. The method further comprises bonding the MEMS structure to a second substrate; and forming a through substrate via (TSV) on a backside of the second substrate, wherein the overlying TSV is aligned with the bonding structure and the support structure. | 07-18-2013 |
| 20130181356 | MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microelectronic dies to the substrate with an active side of the individual dies facing toward the substrate and with a plurality of terminals on the active side of the individual dies aligned with corresponding holes in the substrate. The singulated dies are attached to the substrate after forming the holes in the substrate. | 07-18-2013 |
| 20130181357 | MANUFACTURING METHOD FOR AN ELECTRONIC SUBSTRATE - The manufacturing method for electronic substrate includes: forming an active region on a first face of a substrate; forming a first part of an interconnection pattern as a passive element on a second face of the substrate; forming an insulating layer as a stress-relieving layer on the second face of the substrate; and forming a second part of the interconnection pattern as the passive element on the insulating layer. | 07-18-2013 |
| 20130181358 | SEMICONDUCTOR DEVICE INCLUDING A FIRST WIRING HAVING A BENDING PORTION A VIA - A first wiring ( | 07-18-2013 |
| 20130187284 | Low Cost and High Performance Flip Chip Package - A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies. | 07-25-2013 |
| 20130187285 | CARRIER, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided. | 07-25-2013 |
| 20130187286 | LEAD FRAMELESS HERMETIC CIRCUIT PACKAGE - A open cavity semiconductor chip package that is leadless and does not have a metal lead frame as in conventional packages. The absence of a lead frame minimizes leakage paths and allows the novel package to be more readily fabricated as a hermetic package. A dual sided insulative or dielectric film is employed as the base interconnect between a semiconductor chip and outside contacts. Electrical connection from the top side of the film to the bottom side of the film is made through conductive micro-vias. The semiconductor chip is mounted on a paddle in a central opening in the film and wire bonded to pads on the film. After mounting of the chip, a cover or lid is attached to the film to encapsulate the assembly and maintain hermeticity of the package. | 07-25-2013 |
| 20130187287 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad. | 07-25-2013 |
| 20130187288 | PACKAGE-ON-PACKAGE ASSEMBLY - A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material. | 07-25-2013 |
| 20130187289 | SEMICONDUCTOR DEVICE STRUCTURES AND ELECTRONIC DEVICES INCLUDING SAME HYBRID CONDUCTIVE VIAS, AND METHODS OF FABRICATION - A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed. | 07-25-2013 |
| 20130187290 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 07-25-2013 |
| 20130187291 | INTEGRATED CIRCUIT DEVICES HAVING BURIED INTERCONNECT STRUCTURES THEREIN THAT INCREASE INTERCONNECT DENSITY - Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively. | 07-25-2013 |
| 20130193584 | ON-CHIP RADIAL CAVITY POWER DIVIDER/COMBINER - Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port. | 08-01-2013 |
| 20130193585 | Fabrication method and structure of through silicon via - A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion. | 08-01-2013 |
| 20130200523 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove. | 08-08-2013 |
| 20130200524 | PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME - A method of forming a semiconductor package may include providing a first package including a first semiconductor chip mounted on a first package substrate having a via-hole and molded by a first mold layer, providing a second package including a second semiconductor chip mounted on a second package substrate having a connection pad and molded by a second mold layer, stacking the first package on the second package to vertically align the via-hole with the connection pad, forming a through-hole penetrating the first and second packages and exposing the connection pad, and forming an electrical connection part in the through-hole. The electrical connection part may electrically connect the first package and the second package to each other. | 08-08-2013 |
| 20130200525 | VIA CONNECTION STRUCTURES, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS OF FABRICATING THE STRUCTURES AND DEVICES - A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure. | 08-08-2013 |
| 20130200526 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME - Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode. | 08-08-2013 |
| 20130200527 | Semiconductor Device and Method of Forming Pre-Molded Substrate to Reduce Warpage During Die Molding - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and conductive layer formed over the substrate. A first encapsulant is deposited over the substrate outside a die attach area of the substrate. The first encapsulant surrounds each die attach area over the substrate and the die attach area is devoid of the first encapsulant. A channel connecting adjacent die attach areas is also devoid of the first encapsulant. A first semiconductor die is mounted over the substrate within the die attach area after forming the first encapsulant. A second semiconductor die is mounted over the first die within the die attach area. An underfill material can be deposited under the first and second die. A second encapsulant is deposited over the first and second die and first encapsulant. The first encapsulant reduces warpage of the substrate during die mounting. | 08-08-2013 |
| 20130200528 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure. | 08-08-2013 |
| 20130207273 | Metal Line and Via Formation Using Hard Masks - A device includes a dielectric layer, a metal line in the dielectric layer, and a via underlying and connected to the metal line. Two dummy metal patterns are adjacent to the metal line, and are aligned to a straight line. A dummy metal line interconnects the two dummy metal patterns. A width of the dummy metal line is smaller than lengths and widths of the two dummy metal patterns, wherein the width is measure in a direction perpendicular to the straight line. Bottoms of the two dummy metal patterns and the dummy metal line are substantially level with a bottom surface of the metal line. | 08-15-2013 |
| 20130207274 | WAFER-SCALE PACKAGE STRUCTURES WITH INTEGRATED ANTENNAS - Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip. | 08-15-2013 |
| 20130207275 | Methods of Forming Device Level Conductive Contacts to Improve Device Performance and Semiconductor Devices Comprising Such Contacts - Disclosed herein are various methods of forming device level conductive contacts to improve device performance and various semiconductor devices with such improved deice level contact configurations. In one example, a device disclosed herein includes a first device level conductive contact positioned in a first layer of insulating material, wherein the first device level conductive contact is conductively coupled to a semiconductor device, a second device level conductive contact positioned above and conductively coupled to the first device level contact, wherein the second device level contact is positioned in a second layer of insulating material, and a first wiring layer for the device that is positioned above and conductively coupled to the second device level conductive contact. | 08-15-2013 |
| 20130207276 | NOVEL PROCESS FOR FORMING A BIG VIA - The present disclosure provides a semiconductor device. The semiconductor device includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine. | 08-15-2013 |
| 20130207277 | ELECTRONIC DEVICE AND FABRICATION METHOD THEREOF - An electronic device | 08-15-2013 |
| 20130207278 | PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF - Silsesquioxane polymers that cure to porous silsesquioxane polymers, silsesquioxane polymers that cure to porous silsesquioxane polymers in negative tone photo-patternable dielectric formulations, methods of forming structures using negative tone photo-patternable dielectric formulations containing silsesquioxane polymers that cure to porous silsesquioxane polymers, structures containing porous silsesquioxane polymers and monomers and method of preparing monomers for silsesquioxane polymers that cure to porous silsesquioxane polymers. | 08-15-2013 |
| 20130207279 | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING VIAS CROSSING THE SUBSTRATE - A method for forming an integrated circuit including the steps of:
| 08-15-2013 |
| 20130214423 | METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES INCLUDING INTERPOSERS WITH CONDUCTIVE VIAS, AND RELATED STRUCTURES AND DEVICES - Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods. | 08-22-2013 |
| 20130214424 | STRUCTURE AND MANUFACTURING METHOD FOR REDUCING STRESS OF CHIP - The invention provides a structure and a manufacturing method thereof for reducing a stress of a chip. The structure comprises a through-silicon via (TSV), a plurality of reinforcing base and a plurality of base bodies. The reinforcing bases are disposed near and around the TSV. The base bodies are disposed near and around the TSV, and the base is disposed on a side of the reinforcing base. The reinforcing base or the base body does not connected with the TSV. | 08-22-2013 |
| 20130214425 | DUAL SIDE PACKAGE ON PACKAGE - An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material. | 08-22-2013 |
| 20130214426 | Semiconductor Package Including an Organic Substrate and Interposer Having Through-Semiconductor Vias - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 08-22-2013 |
| 20130214427 | SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS STACKED WITH EACH OTHER - A first semiconductor chip includes a first surface and a second surface opposite to the first surface. A second semiconductor chip is stacked over the second surface of the first semiconductor chip. The second semiconductor chip is larger in size than the first semiconductor chip. A first sealing resin covers the first and second semiconductor chips so that the first surface exposes from the first sealing resin. A first width of the first sealing resin that is around the first semiconductor chip is larger than a second width of the first sealing resin that is around the second semiconductor chip. | 08-22-2013 |
| 20130214428 | SEMICONDUCTOR DEVICE HAVING NON-PLANAR INTERFACE BETWEEN A PLUG LAYER AND A CONTACT LAYER - A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer. | 08-22-2013 |
| 20130214429 | STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERS - A through via contains a conductor ( | 08-22-2013 |
| 20130221534 | Through Silicon Via Layout Pattern - A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape. | 08-29-2013 |
| 20130221535 | Diffusion Barrier Layer, Metal Interconnect Arrangement and Method of Manufacturing the Same - A diffusion barrier layer, a metal interconnect arrangement and a method of manufacturing the same are disclosed. In one embodiment, the metal interconnect arrangement may comprise a conductive plug/interconnect wire for electrical connection, and a diffusion barrier layer provided on at least a portion of a surface of the conductive plug/interconnect wire. The diffusion barrier layer may comprise insulating amorphous carbon. | 08-29-2013 |
| 20130221536 | ENHANCED FLIP CHIP STRUCTURE USING COPPER COLUMN INTERCONNECT - A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only. | 08-29-2013 |
| 20130221537 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A semiconductor device is provided in the present invention. The semiconductor device includes a silicon substrate, configured to bear a chip; a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; and an interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip. With the semiconductor device according to the embodiments of the present invention, the power supply voltage can be directly sent from the silicon substrate to the chip after being generated, thereby shortening the power supply link and reducing the power supply/ground noise. | 08-29-2013 |
| 20130221538 | SEMICONDUCTOR DEVICE - To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed. | 08-29-2013 |
| 20130221539 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT WITH A THROUGH-CONTACT AND SEMICONDUCTOR COMPONENT WITH THROUGH-CONTACT - Through the intermetal dielectric ( | 08-29-2013 |
| 20130221540 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE COMPRISING AN INTER-DIE CONNECTION ON THE BASIS OF FUNCTIONAL MOLECULES - In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips. | 08-29-2013 |
| 20130221541 | INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES, AND FABRICATION METHODS THEREOF - An integrated circuit which includes an interconnect structure disposed at least partially in at least one opening of a dielectric layer. The integrated circuit further includes at least one air gap disposed between the dielectric layer and the interconnect structure. The integrated circuit further includes at least one first liner material disposed under the at least one air gap, the at least one first liner material extending along a bottom portion of a sidewall of the at least one opening of the dielectric layer. | 08-29-2013 |
| 20130228932 | Package on Package Structure - A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit. | 09-05-2013 |
| 20130228933 | BEOL Interconnect With Carbon Nanotubes - An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode. | 09-05-2013 |
| 20130228934 | INTEGRATED CIRCUIT DEVICES INCLUDING INTERCONNECTIONS INSULATED BY AIR GAPS AND METHODS OF FABRICATING THE SAME - Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections. | 09-05-2013 |
| 20130228935 | SEMICONDUCTOR DEVICE HAVING SIGNAL LINE AND POWER SUPPLY LINE INTERSECTING WITH EACH OTHER - Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring. | 09-05-2013 |
| 20130228936 | METHOD OF FORMING THROUGH SILICON VIA OF SEMICONDUCTOR DEVICE USING LOW-K DIELECTRIC MATERIAL - A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate. | 09-05-2013 |
| 20130234336 | PROCESSES FOR FORMING INTEGRATED CIRCUITS AND INTEGRATED CIRCUITS FORMED THEREBY - Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant. | 09-12-2013 |
| 20130234337 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved. | 09-12-2013 |
| 20130234338 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a plurality of contact electrodes that reach corresponding conductive layers. Each of the contact electrodes includes a columnar portion, a stopper, and a first connection portion. The columnar portion extends in a stacked direction of the stacked body. The stopper covers the side of the columnar portion. The first connection portion is provided at a lower edge of the columnar portion. The first connection portion is in contact with the corresponding conductive layer. A cross-section dimension of the first connection portion in a direction orthogonal to the stacked direction is larger than a cross-section of the lower edge of the columnar portion. An etching rate of a material for the stopper is lower than an etching rate of a material for the first insulating layer. | 09-12-2013 |
| 20130234339 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, AND MANAGEMENT SYSTEM OF SEMICONDUCTOR DEVICE - After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack. | 09-12-2013 |
| 20130234340 | VERTICALLY STACKABLE DIES HAVING CHIP IDENTIFIER STRUCTURES - A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact. | 09-12-2013 |
| 20130234341 | INTERPOSER SUBSTRATE MANUFACTURING METHOD AND INTERPOSER SUBSTRATE - A method for manufacturing an interposer substrate includes: forming a conductive portion on a first surface of a semiconductor substrate via a first insulating layer, the conductive portion being formed of a first metal; forming a through hole at a second surface side of the semiconductor substrate located on an opposite side to the first surface so as to expose the first insulating layer; forming a second insulating layer on at least an inner wall surface and a bottom surface of the through hole; exposing the conductive portion by removing portions of the first and second insulating layers using a dry etching method that uses an etching gas containing a fluorine gas, the portions of the first and second insulating layers being located on the bottom surface of the through hole; and forming a conductive layer on the second insulating layer and electrically connecting the conductive layer to the conductive portion, wherein when exposing the conductive portion, forming a tapered portion is performed. | 09-12-2013 |
| 20130234342 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip including a plurality of driver circuits and an output switching circuit coupled to the plurality of driver circuits. The device also includes a second semiconductor chip and a plurality of through silicon vias provided on at least one of the first and second semiconductor chips. The output switching circuit is coupled between the plurality of driver circuits and the plurality of the through silicon vias, and outputs each of signals from the plurality of driver circuits to corresponding one of the plurality of through silicon vias. | 09-12-2013 |
| 20130234343 | THROUGH-HOLE SUBSTRATE AND METHOD OF PRODUCING THE SAME - A substrate ( | 09-12-2013 |
| 20130241075 | CONTACT OR VIA CRITICAL DIMENSION CONTROL WITH NOVEL CLOSED LOOP CONTROL SYSTEM IN CHEMICAL MECHANICAL PLANARIZATION PROCESS - Closed loop control may be used to improve uniformity of contact or via critical dimension using chemical mechanical planarization. For example, real-time closed loop control may be used to adjust oxide buffing or over-polishing time in a chemical mechanical planarization process to more uniformly and consistently achieve a target critical dimension of a semiconductor wafer. | 09-19-2013 |
| 20130241076 | ELECTRONIC DEVICE WITH REDUCED NON-DEVICE EDGE AREA - A first product may be provided that comprises a substrate having a first surface, a first side, and a first edge where the first surface meets the first side; and a device disposed over the substrate, the device having a second side, where at least a first portion of the second side is disposed within 3 mm from the first edge of the substrate. The first product may further comprise a first barrier film that covers at least a portion of the first edge of the substrate, at least a portion of the first side of the substrate, and at least the first portion of the second side of the device. | 09-19-2013 |
| 20130241077 | Semiconductor Package and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant. | 09-19-2013 |
| 20130241078 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate having one surface, an other surface which faces away from the one surface, and through holes which pass through the one surface and the other surface; through electrodes filled in the through holes; and a gettering layer formed of polysilicon interposed between the through electrodes and inner surfaces of the semiconductor substrate whose form is defined by the through holes. | 09-19-2013 |
| 20130241079 | NOVEL CONDUCTOR LAYOUT TECHNIQUE TO REDUCE STRESS-INDUCED VOID FORMATIONS - A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device. | 09-19-2013 |
| 20130241080 | Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP - A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure. | 09-19-2013 |
| 20130249104 | Semiconductor Device and Method of Forming Conductive Layer Over Metal Substrate for Electrical Interconnect of Semiconductor Die - A semiconductor device has a substrate with a cavity. A conductive layer is formed within the cavity and over the substrate outside the cavity. A plurality of indentations can be formed in a surface of the substrate opposite the cavity for stress relief. A first semiconductor die is mounted within the cavity. A plurality of conductive vias can be formed through the first semiconductor die. An insulating layer is disposed between the first semiconductor die and substrate with the first conductive layer embedded within the first insulating layer. An encapsulant is deposited over the first semiconductor die and substrate. An interconnect structure is formed over the encapsulant. The interconnect structure is electrically connected to the first semiconductor die and first conductive layer. The substrate is removed to expose the first conductive layer. A second semiconductor die is mounted to the conductive layer over the first semiconductor die. | 09-26-2013 |
| 20130249105 | Semiconductor Device and Method of Forming Micro-Vias Partially through Insulating Material over Bump Interconnect Conductive Layer for Stress Relief - A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief. | 09-26-2013 |
| 20130249106 | Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer - A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure. | 09-26-2013 |
| 20130249107 | MULTI-CHIP SEMICONDUCTOR APPARATUS - A multi-chip semiconductor apparatus includes a plurality of semiconductor chips electrically connected and stacked. Each of the semiconductor chips trims a voltage level used in the semiconductor chip in response to a chip select signal. | 09-26-2013 |
| 20130249108 | SEMICONDUCTOR PACKAGES, ELECTRONIC SYSTEMS EMPLOYING THE SAME AND METHODS OF MANUFACTURING THE SAME - Semiconductor packages are provided. The semiconductor package includes a first chip having a first inclined sidewall in an edge of the first chip; and a second chip having a second inclined sidewall in an edge of the second chip and the second chip being horizontally adjacent to the first chip such that the first and second inclined sidewalls are in substantial contact with each other. | 09-26-2013 |
| 20130249109 | INTERPOSER FOR HERMETIC SEALING OF SENSOR CHIPS AND FOR THEIR INTEGRATION WITH INTEGRATED CIRCUIT CHIPS - Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed. | 09-26-2013 |
| 20130249110 | METHOD AND APPARATUS FOR REDUCED PARASITICS AND IMPROVED MULTI-FINGER TRANSISTOR THERMAL IMPEDANCE - A transistor, a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. Providing for a method and an apparatus that reduces a transistor's parasitics and reduces a transistor's thermal impedance, resulting in higher device bandwidths and higher output power. More particularly, providing for a method and an apparatus for applying compact, multiple connections to the gate of a FET (or HEMT) or the base of a BJT (or HBT) from many sides resulting in reduced parasitics and improved transistor thermal impedance. | 09-26-2013 |
| 20130249111 | Semiconductor Device and Method of Forming RDL Wider than Contact Pad Along First Axis and Narrower than Contact Pad along Second Axis - A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer. | 09-26-2013 |
| 20130249112 | PASSIVE WITHIN VIA - A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein. | 09-26-2013 |
| 20130256900 | ULTRATHIN BURIED DIE MODULE AND METHOD OF MANUFACTURING THEREOF - A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer via an adhesive and a die is positioned within the die opening of the initial laminate flex layer. A second uncut laminate flex layer is secured to the second surface of the initial laminate flex layer via an adhesive and the adhesive between each pair of neighboring layers is cured. A plurality of vias and metal interconnects are formed in and on the first and second uncut laminate flex layers, with each of the metal interconnects extending through a respective via and being directly metalized to a metal interconnect on the initial laminate flex layer or a die pad on the die. | 10-03-2013 |
| 20130256901 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS - Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material. | 10-03-2013 |
| 20130256902 | INTERCONNECT STRUCTURE HAVING SMALLER TRANSITION LAYER VIA - An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via. | 10-03-2013 |
| 20130256903 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A interconnect structure includes a conductive layer formed in a dielectric layer. An adhesion layer is formed between the dielectric layer and a substrate. The adhesion layer has a carbon content ratio greater than a carbon content ratio of the dielectric layer. | 10-03-2013 |
| 20130256904 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance. | 10-03-2013 |
| 20130256905 | Monolithic Power Converter Package with Through Substrate Vias - According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. The high side power input and a power output of the half-bridge each are disposed on a top surface of the monolithic die. The high side power input is electrically coupled to the substrate through a high side power connection. The power output is electrically coupled to the substrate through a power output connection. The low side power input of the half-bridge comprises a plurality of through substrate vias that extend through the monolithic die to electrically connect a low side power pad to the monolithic die. | 10-03-2013 |
| 20130256906 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad. | 10-03-2013 |
| 20130256907 | BONDED PROCESSED SEMICONDUCTOR STRUCTURES AND CARRIERS - Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods. | 10-03-2013 |
| 20130256908 | INTER-DIE CONNECTION WITHIN AN INTEGRATED CIRCUIT FORMED OF A STACK OF CIRCUIT DIES - An integrated circuit is formed of a plurality of circuit dies | 10-03-2013 |
| 20130256909 | PATTERNED ADHESIVE TAPE FOR BACKGRINDING PROCESSES - The present disclosure relates to the field of fabricating microelectronic devices, wherein a microelectronic device substrate, such as a microelectronic wafer, may be thinned by a backgrinding process using a patterned adhesive tape that reduces slurry seepage and adhesive contamination. The patterned adhesive tape may comprise a base film and adhesive material patterned on the base film such that an edge or periphery portion of the microelectronic device substrate may contact the adhesive material, but substantially no adhesive material contacts interconnectors formed on the microelectronic device substrate. | 10-03-2013 |
| 20130256910 | 3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH THROUGH-SILICON VIAS - A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow. | 10-03-2013 |
| 20130264717 | MULTI-LEVEL STACK HAVING MULTI-LEVEL CONTACT AND METHOD - A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at least n−1 insulating layers. A via formation layer is formed over the stack. A first via is etched in the via formation layer at a first edge of the stack. A first multi-level contact is formed in the first via. For a particular embodiment, a second via may be etched in the via formation layer at a second edge of the stack and a second multi-level contact may be formed in the second via. | 10-10-2013 |
| 20130264718 | LAYOUT OF MEMORY STRAP CELL - A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source. | 10-10-2013 |
| 20130264719 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area. | 10-10-2013 |
| 20130264720 | Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages - A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer. | 10-10-2013 |
| 20130270708 | METHOD FOR FORMING BURIED CONDUCTIVE LINE AND STRUCTURE OF BURIED CONDUCTIVE LINE - A method for forming a buried conductive line is described. A substrate having a trench therein and a contact area thereon is provided, wherein the trench has an end portion in the contact area and a conductive layer is filled in the trench. A mask layer is formed covering the conductive layer in the contact area. The conductive layer is etched back using the mask layer as a mask. | 10-17-2013 |
| 20130270709 | NON-BRIDGING CONTACT VIA STRUCTURES IN PROXIMITY - A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer. | 10-17-2013 |
| 20130270710 | GUARD RING DESIGN STRUCTURE FOR SEMICONDUCTOR DEVICES - A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells. | 10-17-2013 |
| 20130270711 | APPARATUS AND METHOD FOR INTEGRATION OF THROUGH SUBSTRATE VIAS - An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer. | 10-17-2013 |
| 20130270712 | Through silicon via structure and method of fabricating the same - A through silicon via structure and a method of fabricating the through silicon via structure are disclosed. After an interlayer dielectric is formed, a via hole is then formed to pass through the interlayer dielectric; thereafter, a dielectric liner is formed within the via hole and extends onto the interlayer dielectric; thereafter, the via hole is filled with a conductive material; and a chemical-mechanical polishing process is performed to planarize the conductive material, using the dielectric liner on the interlayer dielectric as a stop layer of the chemical-mechanical polishing process. | 10-17-2013 |
| 20130270713 | DUAL DAMASCENE STRUCTURE HAVING THROUGH SILICON VIA AND MANUFACTURING METHOD THEREOF - A dual damascene structure having a through silicon via and a manufacturing method thereof are provided. The method includes forming a first, a second, and a third dielectric layers a on a substrate having a conductive structure. A trench is formed in the third dielectric layer. A hard mask layer is formed on the third dielectric layer and a surface of the trench. A first opening having a tapered sidewall is formed in the hard mask layer. A second opening is formed in the second and the third dielectric layers. The substrate exposed by the second opening and the first opening is etched to form a through hole so as to form a dual damascene opening. A liner layer is formed on a surface of the dual damascene opening and the conductive structure is exposed. The dual damascene opening is filled with a conductive material. | 10-17-2013 |
| 20130270714 | CONTACT STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes conductive patterns vertically stacked on the substrate and having pad regions extended further at edge portions of the conductive patterns as the conductive patterns descend from an uppermost conductive pattern to a lowermost conductive pattern, a first contact plug disposed on a first pad region of the lowermost conductive pattern, a buffer conductive pattern disposed on a second pad region positioned above the first pad region, and a second contact plug formed on the buffer conductive pattern. | 10-17-2013 |
| 20130270715 | PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES - A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. | 10-17-2013 |
| 20130277852 | Method for Creating a 3D Stacked Multichip Module - A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2 | 10-24-2013 |
| 20130277853 | Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Conductive Features - Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof. | 10-24-2013 |
| 20130277854 | 3D INTEGRATED CIRCUIT SYSTEM WITH CONNECTING VIA STRUCTURE AND METHOD FOR FORMING THE SAME - A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars. | 10-24-2013 |
| 20130277855 | HIGH DENSITY 3D PACKAGE - Embodiments of the present provide an integrated circuit system, which includes an interposer having a plurality of electrical conductive vias running through the interposer, one or more high-power chips mounted on a first surface of the interposer, wherein the one or more high-power chips generate at least 10 W of heat during normal operation, one or more low-power chips mounted on a second surface of the interposer, wherein the one or more low-power chips generate less than 5 W of heat during normal operation, and the first surface and the second surface are opposite and substantially parallel to each other, and an encapsulating material formed over and configured to encapsulate the one or more high-power chips and the one or more low-power chips. Since low-power chips and high-power chips are respectively mounted on front side and back side of the interposer, the footprint of the interposer and manufacturing cost associated therewith is reduced. | 10-24-2013 |
| 20130277856 | METHOD FOR STABILIZING EMBEDDED SILICON - A method for disclosing an integrated circuit embedded in a resin is disclosed. In one embodiment, stabilizing vias can be formed within the resin and can couple to corresponding pads in the integrated circuit. The stabilizing vias can be used in areas prone to failure when the combined resin/integrated circuit is stressed or undergoes some amount of displacement. In one embodiment, the stabilizing vias can be non-functional vias that do not carry electrical signals or power to or from the integrated circuit. | 10-24-2013 |
| 20130277857 | STACK TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING AND TESTING THE SAME - There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding. | 10-24-2013 |
| 20130277858 | ELECTRICAL INTERCONNECTION STRUCTURE AND ELECTRICAL INTERCONNECTION METHOD - An electrical interconnection structure includes: a signal transmission structure having a first through silicon via (TSV) and signal circuits connected to two opposite ends of the first TSV, respectively; and a grounding structure having a second TSV and grounding layers connected to two opposite ends of the second TSV, respectively. The grounding layers surround the signal circuits along the pathways thereof such that the ends of the first TSV are surrounded by the grounding layers with gaps therebetween. By changing the gaps between the grounding layers and the ends of the first TSV, the capacitance between the grounding layers and the signal circuits is adjusted so as to regulate the impedance therebetween. | 10-24-2013 |
| 20130277859 | FABRICATION OF SEMICONDUCTOR DEVICE INCLUDING CHEMICAL MECHANICAL POLISHING - A method of fabricating a semiconductor device includes forming a first insulation film over a semiconductor substrate, the semiconductor substrate including an outer region and an inner region located at an inner side of the outer region, forming a first wiring over the first insulation film in the inner region, forming a second insulation film over the first wiring and over the first insulation film, decreasing a film thickness of the second insulation film in the inner region with regard to a film thickness of the second insulation film in the outer region, and polishing the second insulation film after the decreasing of the film thickness of the second insulation film. | 10-24-2013 |
| 20130277860 | Chip Pad Resistant to Antenna Effect and Method - A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC. | 10-24-2013 |
| 20130277861 | VERTICALLY STACKABLE DIES HAVING CHIP IDENTIFIER STRUCTURES - A particular device includes a first die that includes a portion of a chip identifier structure, the portion including a first set of at least two through vias that are each connected to a corresponding external electrical contact of a first set of external electrical contacts. Each of the first set of through vias has a pad configured to be coupled to an adjacent through via of a second die in the chip identifier structure. Each external electrical contact of the first set of external electrical contacts is configured to transmit a chip select signal. The first die further includes at least a portion of a chip communication structure including a second set of at least one through via. Each via of the second set is connected to one external electrical contact of a second set of external electrical contacts. | 10-24-2013 |
| 20130285251 | ELONGATED VIA STRUCTURES - An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface. | 10-31-2013 |
| 20130285252 | PACKAGE CARRIER - A package carrier includes a metal substrate, a pad, a dielectric layer, and a circuit layer. The metal substrate has a first surface and a second surface opposite to the first surface. The pad is disposed on the first surface. The dielectric layer is disposed on the first surface and covers the pad. A thickness of the dielectric layer is less than 150 μm. The circuit layer is embedded in the dielectric layer and connected to the pads. | 10-31-2013 |
| 20130285253 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes: a step of forming an inorganic insulating film and an organic insulating film on one surface of a first substrate; a step of forming an opening portion by dry-etching a laminated film of them; a step of forming a bump electrode inside the opening portion; and a step (bonding step) of bonding the one surface of the first substrate having a bump electrode formed thereon and one surface of a second substrate having a bump electrode formed thereon to each other. A surface treatment on the inorganic insulating film is performed subsequent to the step of forming the opening portion but prior to the bonding step. By performing the surface treatment on the organic insulating film, connecting property between the substrates can be improved. | 10-31-2013 |
| 20130285254 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBTRATE - A wiring substrate includes a core substrate. The core substrate includes a first surface, a second surface, and an opening extending through the core substrate between the first and second surfaces. A first conductive film is formed on the first surface and covers the opening. A second conductive film is formed on the second surface. The second conductive film covers the opening. An electronic component is arranged in the opening and connected to the first conductive film. An insulator fills the opening. A first wiring portion includes alternately stacked insulative layers and wiring layers and covers the first surface of the core substrate and the first conductive film. A second wiring portion includes alternately stacked insulative layers and wiring layers, and covers the second surface of the core substrate and the second conductive film. | 10-31-2013 |
| 20130285255 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion. | 10-31-2013 |
| 20130285256 | METHOD AND AN APPARATUS FOR FORMING ELECTRICALLY CONDUCTIVE VIAS IN A SUBSTRATE, AN AUTOMATED ROBOT-BASED MANUFACTURING SYSTEM, A COMPONENT COMPRISING A SUBSTRATE WITH VIA HOLES, AND AN INTERPOSER DEVICE - A method is disclosed for forming conductive vias in a substrate by filling preformed via holes, preferably through via holes, with conductive material. The method includes providing a plurality of preformed objects at least partly including ferromagnetic material on a surface of the substrate; providing a magnetic source on an opposite side of the substrate with respect to the plurality of preformed objects, thereby at least partly aligning at least a portion of the preformed objects with a magnetic field associated with the magnetic source; and moving the magnetic source relative the substrate, or vice versa, thereby moving the at least portion of the preformed objects into at least a portion of the via holes. | 10-31-2013 |
| 20130285257 | 3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH - A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow. | 10-31-2013 |
| 20130292841 | SEMICONDUCTOR INTERCONNECT STRUCTURE - The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer. | 11-07-2013 |
| 20130292842 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another; and interconnections electrically connecting the repair pads of the semiconductor chips. | 11-07-2013 |
| 20130292843 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a substrate having one surface and an other surface which substantially faces away from the one surface; at least two alignment bumps formed on the one surface of the substrate and having different diameters; and at least two alignment grooves defined on the other surface of the substrate and having different diameters. | 11-07-2013 |
| 20130292844 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first interposer; first and second semiconductor chips horizontally mounted over the first interposer and electrically connected with the first interposer; and a second interposer disposed over the first and second semiconductor chips and electrically connected with the first and second semiconductor chips, wherein the first semiconductor chip includes a plurality of first through electrodes, and the second semiconductor chip includes a plurality of second through electrodes, and wherein the first through electrodes of the first semiconductor chip and the second through electrodes of the second semiconductor chip are electrically connected with each other through the first and second interposers. | 11-07-2013 |
| 20130292845 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip. | 11-07-2013 |
| 20130292846 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package including a first semiconductor chip and a second semiconductor chip respectively disposed at a bottom and at a top so that active surfaces thereof face each other. Further includes is a first molding member for sealing the first semiconductor chip and exposing the active surface of the first semiconductor chip through a top surface, a first rewiring formed on the top surface of the first molding member and the active surface of the first semiconductor chip, a second rewiring formed on a bottom surface of the first molding member, a through-via for penetrating through the first molding member and electrically connecting the first and second rewirings, and a first connection member disposed between the first and second semiconductor chips. Also provided are various systems including same and various methods for making same. | 11-07-2013 |
| 20130292847 | Semiconductor Devices and Methods of Manufacturing the Same - A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad. | 11-07-2013 |
| 20130292848 | SEMICONDUCTOR PACKAGES INCLUDING MOLDING LAYERS - Semiconductor packages including molding layer and methods of fabricating the same are provided. The method may include forming a bare package including a semiconductor chip on a package substrate and forming a molding layer surrounding the semiconductor chip on the package substrate while contacting an upper surface of the molding layer with a lower surface of a release film. The lower surface of the release film and the upper surface of the molding layer comprising uneven surfaces and the molding layer may expose an upper surface of the semiconductor chip. | 11-07-2013 |
| 20130292849 | SYSTEM-IN PACKAGES - System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects. | 11-07-2013 |
| 20130292850 | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant - A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. | 11-07-2013 |
| 20130292851 | Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die - A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die. | 11-07-2013 |
| 20130299994 | INTEGRATED CIRCUITS AND PROCESSES FOR FORMING INTEGRATED CIRCUITS HAVING AN EMBEDDED ELECTRICAL INTERCONNECT WITHIN A SUBSTRATE - Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer. | 11-14-2013 |
| 20130299995 | Semiconductor Device and Method of Depositing Underfill Material With Uniform Flow Rate - A semiconductor device has a substrate and insulating layer formed over a surface of the substrate. A first conductive layer is formed over the surface of the substrate. A second conductive layer is formed over an opposing surface of the substrate. A conductive via is formed through the substrate. An opening is formed in the insulating layer while leaving the first conductive layer intact. The opening narrows with a non-linear side or linear side. The opening can have a rectangular shape. A semiconductor die is mounted over the surface of the substrate. An underfill material is deposited between the semiconductor die and substrate. The opening in the insulating layer reduces a flow rate of the underfill material proximate to the opening. The flow rate of the underfill material proximate to the opening is substantially equal to a flow rate of the underfill material away from the opening. | 11-14-2013 |
| 20130299996 | METHOD OF MAKING AN ELECTRODE CONTACT STRUCTURE AND STRUCTURE THEREFOR - In one embodiment, a method for forming a semiconductor device having a shield electrode includes forming first and second shield electrode contact portions within a contact trench. The first shield electrode contact portion can be formed recessed within the contact trench and includes a flat portion. The second shield electrode contact portion can be formed within the contact trench and makes contact to the first shield electrode contact portion along the flat portion. | 11-14-2013 |
| 20130299997 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES - Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods. | 11-14-2013 |
| 20130299998 | Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings. | 11-14-2013 |
| 20130299999 | DISTRIBUTED SEMICONDUCTOR DEVICE METHODS, APPARATUS, AND SYSTEMS - Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice. | 11-14-2013 |
| 20130307159 | PHYSICAL DESIGN SYMMETRY AND INTEGRATED CIRCUITS ENABLING THREEDIMENTIONAL (3D) YIELD OPTIMIZATION FOR WAFER TO WAFER STACKING - One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack. | 11-21-2013 |
| 20130307160 | Via Structure For Three-Dimensional Circuit Integration - Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount. | 11-21-2013 |
| 20130307161 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening. | 11-21-2013 |
| 20130307162 | WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A wiring board includes a first insulation layer, a first conducive layer having first conductive patterns formed on the first insulation layer, a wiring structure positioned on the first insulation layer and including a second insulation layer and a second conductive layer having second conductive patterns formed on the second insulation layer, multiple conductive patterns formed on the wiring structures such that the conductive patterns are connected to the second conductive patterns, respectively, multiple first electrodes formed on the first conductive patterns, respectively, and multiple second electrodes formed on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively. The first electrodes and the second electrodes have top surfaces which form the same plane. | 11-21-2013 |
| 20130313716 | SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT - A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. | 11-28-2013 |
| 20130313717 | SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE - After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed, and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer. | 11-28-2013 |
| 20130313718 | Substrates Comprising Integrated Circuitry, Methods Of Processing A Substrate Comprising Integrated Circuitry, And Methods Of Back-Side Thinning A Substrate Comprising Integrated Circuitry - A method of processing a substrate having integrated circuitry includes forming through-substrate vias partially through the substrate from a first side of the substrate. At least one through-substrate structure is formed partially through the substrate from the first substrate side. The at least one through-substrate structure extends deeper into the substrate than do the through-substrate vias. Substrate material is removed from a second side of the substrate to expose the through-substrate vias and the at least one through-substrate structure on the second substrate side. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture. | 11-28-2013 |
| 20130313719 | CHIP PACKAGES AND METHODS FOR MANUFACTURING A CHIP PACKAGE - A method for manufacturing a chip package is provided. The method including: holding a carrier including a plurality of dies; forming a separation between the plurality of dies by removing from the carrier one or more portions of the carrier between the plurality of dies; forming an encapsulation material in the removed one or more portions between the plurality of dies; separating the dies through the encapsulation material. | 11-28-2013 |
| 20130313720 | PACKAGING SUBSTRATE WITH RELIABLE VIA STRUCTURE - A packaging substrate includes a high reliability via structure that extends through multiple layers of the packaging substrate. The via structure includes an opening formed through multiple layers of the packaging substrate and an electrically conductive layer that is deposited in the opening. The opening is formed in a single material removal process and the conductive layer is formed in a single deposition process. Because the conductive layer is formed in a single deposition process, the conductive layer provides an interface-free conductive path between the multiple layers. | 11-28-2013 |
| 20130313721 | Semiconductor Module with Micro-Buffers - The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die. | 11-28-2013 |
| 20130313722 | THROUGH-SILICON VIA (TSV) SEMICONDUCTOR DEVICES HAVING VIA PAD INLAYS - A semiconductor device includes an insulating layer on a surface of a substrate, a through-via structure vertically passing through the substrate and the insulating layer and being exposed on the insulating layer, and a via pad on a surface of the exposed through-via structure. The via pad includes a via pad body, and a via pad inlay below the via pad body and protruding into the insulating layer and surrounding the through-via structure. The via pad body and the via pad inlay include a via pad barrier layer directly on the insulating layer and a via pad metal layer on the via pad barrier layer. | 11-28-2013 |
| 20130313723 | SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS - A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays. | 11-28-2013 |
| 20130313724 | SHIELDED COPLANAR LINE - In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench. | 11-28-2013 |
| 20130313725 | MULTILAYER INTERCONNECT STRUCTURE AND METHOD FOR INTEGRATED CIRCUITS - A multilayer interconnect structure is formed by, providing a substrate ( | 11-28-2013 |
| 20130320553 | NOVEL BEAD FOR 2.5D/3D CHIP PACKAGING APPLICATION - An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters. | 12-05-2013 |
| 20130320554 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An interconnect is spaced apart from the circuit area and extends from the top surface into the substrate. The interconnect includes a sidewall formed of an electrically insulating material. An opening is provided in the sidewall. | 12-05-2013 |
| 20130320555 | EDA TOOL AND METHOD, AND INTEGRATED CIRCUIT FORMED BY THE METHOD - A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks. | 12-05-2013 |
| 20130320556 | Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers - Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material. | 12-05-2013 |
| 20130320557 | SEMICONDUCTOR PACKAGE HAVING RELIABLE ELECTRICAL CONNECTION AND ASSEMBLING METHOD - A semiconductor package includes a printed circuit board, a chip, a protection frame, and a covering layer. The chip is mounted on the printed circuit board and is electrically connected to the printed circuit board through a number of first bonding wires. The protection frame includes a sidewall surrounding the chip and the bonding wires and defines a number of through holes passing through an inner surface and an outer surface of the sidewall. The protection frame is filled with adhesive. The adhesive adheres to the inner surface and covers the chip and the boding wires. The covering layer is coated on the outer surface and covers the through holes. | 12-05-2013 |
| 20130320558 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for forming a semiconductor device includes forming a sealing insulation film over a semiconductor substrate including a device isolation film and an active region, forming a bit line contact plug that protrudes from an upper part of the sealing insulation film and is coupled to the active region, forming a spacer over a sidewall of the protruded bit line contact plug, and forming a bit line coupled to an upper part of the bit line contact plug. | 12-05-2013 |
| 20130320559 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate. | 12-05-2013 |
| 20130320560 | DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE INTERCONNECT - An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry. | 12-05-2013 |
| 20130320561 | PLUG VIA STACKED STRUCTURE, STACKED SUBSTRATE HAVING VIA STACKED STRUCTURE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t′ formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness α from a top of the circuit pattern, wherein T≦t″+α is satisfied, T represents a sum of the thicknesses t and t′ and t″ is a thickness of a portion of the circuit pattern formed on the via plug. | 12-05-2013 |
| 20130320562 | SEMICONDUCTOR DEVICE - The present invention aims to relax stress induced by through-silicon via formed on semiconductor substrate in order to prevent property fluctuation of a transistor. A semiconductor device includes a semiconductor substrate, a through-silicon via formed in semiconductor substrate, an insulating film formed between the semiconductor substrate and the through-silicon via, and a transistor formed on the semiconductor substrate so as to be apart from the through-silicon via with a predetermined distance. The insulating film does not exist on a region close to a surface of the semiconductor substrate between the semiconductor substrate and the through-silicon via. A gap is formed to be surrounded by the semiconductor substrate, the through silicon via, and the insulating film under the region close to the surface of the semiconductor substrate. | 12-05-2013 |
| 20130320563 | Three dimensional memory structure - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 12-05-2013 |
| 20130320564 | AVD HARDMASK FOR DAMASCENE PATTERNING - A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point. | 12-05-2013 |
| 20130328208 | DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME - A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions. | 12-12-2013 |
| 20130328209 | Stack Arrangement - In an embodiment, a stack arrangement is provided. The stack arrangement may include a semiconductor arrangement, the semiconductor arrangement including a substrate; a via formed through the substrate; and a conductive portion arranged in the via. The stack arrangement may further include an interconnect portion arranged over the via; a bond pad portion arranged between the semiconductor arrangement and the interconnect portion, the bond pad portion may include a bond pad circumferential portion arranged at least partially circumferential with respect to the via and at a first distance away from the conductive portion; and at least one bond pad electrical connection extending from within the bond pad circumferential portion to the conductive portion; wherein the interconnect portion may be arranged away from the conductive portion via the bond pad portion. | 12-12-2013 |
| 20130328210 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device includes a substrate, a plurality of signal lines, and at least one power line. The substrate includes an integrated circuit unit. The signal lines are disposed on the substrate and are configured to provide the integrated circuit unit with signals. The power line is disposed on the substrate and is configured to provide the integrated circuit unit with power supply on the substrate. The power line includes a stacked structure including a first power line and a second power line stacked on the first power line. | 12-12-2013 |
| 20130328211 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor device includes a semiconductor chip, a core substrate, first and second insulating layers, and first and second wiring layers. Adhesiveness of the insulating layer to a metal is higher than adhesiveness of the core substrate to the metal. A through hole extends through the insulating layer in the thickness direction. A through via covers the hole wall surface of the through hole, extends in the thickness direction traversing the insulating layer, and electrically connects the first and second wiring layers. | 12-12-2013 |
| 20130328212 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes: a semiconductor chip: a first insulating layer, wherein the semiconductor chip is embedded in the first insulating layer such that the first surface and the side surface of the semiconductor chip are covered by the first insulating layer; a wiring structure on the first surface of the first insulating layer and comprising an insulating layer and a wiring layer; an outermost wiring layer on the wiring structure and having: a reinforcing wiring pattern; and a via wiring which penetrates the reinforcing wiring pattern and electrically connected to the reinforcing wiring pattern, wherein the via wiring is formed through the insulating layer of the wiring structure and electrically connected to the wiring layer of the wiring structure; a second insulating layer on the wiring structure to cover the outermost wiring layer. | 12-12-2013 |
| 20130328213 | ELECTRONIC DEVICE INCLUDING A CARRIER AND A SEMICONDUCTOR CHIP ATTACHED TO THE CARRIER AND MANUFACTURING THEREOF - One aspect is a device including a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one first through-connection from a first face of the first insulating layer to a second face of the first insulating layer. A semiconductor chip is attached to the carrier and a second insulating layer is over the carrier and the semiconductor chip. A metal layer is over the second insulating layer. A second through-connection is through the second insulating layer electrically coupling the semiconductor chip to the metal layer. A third through-connection is through the second insulating layer electrically coupling the carrier to the metal layer. | 12-12-2013 |
| 20130328214 | THROUGH-HOLE ELECTRODE SUBSTRATE - A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate. | 12-12-2013 |
| 20130328215 | Die Edge Contacts for Semiconductor Devices - A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. | 12-12-2013 |
| 20130334697 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a bottom integrated circuit having bottom through silicon vias with a bottom via pitch; mounting outer interconnects over the bottom integrated circuit; and mounting a top integrated circuit between the outer interconnects, the top integrated circuit having top through silicon vias with a top via pitch less than the bottom via pitch. | 12-19-2013 |
| 20130334698 | MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONIC ELEMENTS THEREIN - A microelectronic assembly tolerant to misplacement of microelectronic elements therein may include a molded structure containing a plurality of microelectronic elements. Each microelectronic element has elements contacts having first and second dimensions in respective first and second directions that are transverse to each other, where the first dimension is at least twice the second dimension. In addition, the assembly may include a conductive redistribution layer including conductive vias extending through a dielectric layer to the element contacts of the respective microelectronic elements, where the conductive vias have a third dimension in a third direction and a fourth dimension in a fourth direction, and where the fourth direction is transverse to the third and first directions and the fourth dimension is greater than the third dimension. | 12-19-2013 |
| 20130334699 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer. | 12-19-2013 |
| 20130334700 | ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT - A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric. | 12-19-2013 |
| 20130334701 | THROUGH SILICON VIA WAFER AND METHODS OF MANUFACTURING - A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure. | 12-19-2013 |
| 20130334702 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device of the present invention includes a first dielectric layer located on an upper surface of a semiconductor substrate including contact area and a non-contact area, an etching stop layer pattern formed to expose the first dielectric layer in the non-contact area and cover the first dielectric layer in the contact area, a contact hole extended to the semiconductor substrate of the contact area through the etching stop layer pattern and the first dielectric layer, a contact plug located in the contact hole, and a conductive line connected to the contact plug. | 12-19-2013 |
| 20130334703 | WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A wiring substrate includes a core substrate including a first wiring layer, an interlayer insulating layer formed by a resin layer containing fiber reinforcement material formed on the core substrate and a primer layer formed on the resin layer containing fiber reinforcement material, and the interlayer insulating layer having a via hole reaching the first wiring layer, and a second wiring layer formed on the primer layer, and connected to the first wiring layer through the via hole. | 12-19-2013 |
| 20130334704 | Deposition and Selective Removal of Conducting Helplayer for Nanostructure Processing - A method for making one or more nanostructures is disclosed, the method comprising: depositing a conducting layer on an upper surface of a substrate; depositing a patterned layer of catalyst on the conducting layer; growing the one or more nanostructures on the layer of catalyst; and selectively removing the conducting layer between and around the one or more nanostructures. A device is also disclosed, comprising a substrate, wherein the substrate comprises one or more exposed metal islands separated by one or more insulating areas; a conducting helplayer disposed on the substrate covering at least some of the one or more exposed metal islands or insulating areas; a catalyst layer disposed on the conducting helplayer; and one or more nanostructures disposed on the catalyst layer. | 12-19-2013 |
| 20130334705 | SEMICONDUCTOR DEVICE - The semiconductor device | 12-19-2013 |
| 20130341799 | Through silicon via structure and method of fabricating the same - A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole. | 12-26-2013 |
| 20130341800 | Integrated Circuit Packages and Methods for Forming the Same - A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. | 12-26-2013 |
| 20130341801 | Redeposition Control in MRAM Fabrication Process - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode. | 12-26-2013 |
| 20130341802 | INTEGRATED CIRCUIT PACKAGE HAVING OFFSET VIAS - Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the centre of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate. | 12-26-2013 |
| 20130341803 | METHOD TO ENABLE CONTROLLED SIDE CHIP INTERCONNECTION FOR 3D INTEGRATED PACKAGING SYSTEM - Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures. | 12-26-2013 |
| 20140001641 | METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES | 01-02-2014 |
| 20140001642 | INTERPOSERS INCLUDING FLUIDIC MICROCHANNELS AND RELATED STRUCTURES AND METHODS | 01-02-2014 |
| 20140001643 | HYBRID PACKAGE TRANSMISSION LINE CIRCUITS | 01-02-2014 |
| 20140001644 | Package Structures and Methods for Forming the Same | 01-02-2014 |
| 20140001645 | 3DIC Stacking Device and Method of Manufacture | 01-02-2014 |
| 20140001646 | SOLID HOLE ARRAY AND MANUFACTURE METHOD THEREOF | 01-02-2014 |
| 20140001647 | FLIP-CHIP ELECTRONIC DEVICE AND PRODUCTION METHOD THEREOF | 01-02-2014 |
| 20140001648 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20140001649 | SEMICONDUCTOR PACKAGE AND PACKAGE ON PACKAGE HAVING THE SAME | 01-02-2014 |
| 20140001650 | ELECTRONIC DEVICE INCLUDING INTERCONNECTS WITH A CAVITY THEREBETWEEN AND A PROCESS OF FORMING THE SAME | 01-02-2014 |
| 20140008812 | SEMICONDUCTOR REFLOW PROCESSING FOR FEATURE FILL - A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature. | 01-09-2014 |
| 20140008813 | COMPLIANT MONOPOLOAR MICRO DEVICE TRANSFER HEAD WITH SILICON ELECTRODE - A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure. | 01-09-2014 |
| 20140015143 | METHODS OF FORMING NANO-SCALE PORES, NANO-SCALE ELECTRICAL CONTACTS, AND MEMORY DEVICES INCLUDING NANO-SCALE ELECTRICAL CONTACTS, AND RELATED STRUCTURES AND DEVICES - Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm | 01-16-2014 |
| 20140015144 | MULTI-CHIP PACKAGE - A multi-chip package includes a main substrate; a plurality of first semiconductor chips stacked on an upper surface of the main substrate and having bonding pads which are electrically connected with the main substrate; and a semiconductor package attached to side surfaces of the stacked first semiconductor chips and electrically connected with the main substrate. | 01-16-2014 |
| 20140015145 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed. | 01-16-2014 |
| 20140015146 | SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. | 01-16-2014 |
| 20140021628 | METHOD FOR FORMING INTERLAYER CONNECTORS IN A THREE-DIMENSIONAL STACKED IC DEVICE - A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2 | 01-23-2014 |
| 20140021629 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy. | 01-23-2014 |
| 20140021630 | HIGH PERFORMANCE IC CHIP HAVING DISCRETE DECOUPLING CAPACITORS ATTACHED TO ITS IC SURFACE - In the present invention, discrete decoupling capacitors are mounted on the surface of an IC chip. Since a discrete capacitor can provide the capacitance of the magnitude μF, the attached capacitors can serve as the local power reservoir to decouple the external power ground noise caused by wirebonds, packages, and other system components. | 01-23-2014 |
| 20140021631 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a supporting substrate; a semiconductor substrate that includes a first surface in which at least one layer is formed and a second surface that is positioned on an opposite side to the first surface, and is pasted to a surface of the supporting substrate with adhesive such that the first surface faces the supporting substrate side; a protective film that is formed on the second surface of the semiconductor substrate and on a surface of the adhesive extending outwardly from a region between the supporting substrate and the semiconductor substrate, and including a perimeter part that is positioned outside a perimeter part of the adhesive, and positioned inside a perimeter part of the supporting substrate; and an electrode material that is formed so as to be embedded in a penetration hole that penetrates the protective film and the semiconductor substrate. | 01-23-2014 |
| 20140021632 | VERTICAL TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced. | 01-23-2014 |
| 20140021633 | Integrated Circuit Device Having Through-Silicon-Via Structure and Method of Manufacturing the Same - An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration. | 01-23-2014 |
| 20140021634 | Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device - A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier. | 01-23-2014 |
| 20140021635 | MICROELECTRIC PACKAGE UTILIZING MULTIPLE BUMPLESS BUILD-UP STRUCTURES AND THROUGH-SILICON VIAS - A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes. | 01-23-2014 |
| 20140021636 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 01-23-2014 |
| 20140021637 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer. | 01-23-2014 |
| 20140027922 | VIA IN SUBSTRATE WITH DEPOSITED LAYER - An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties. | 01-30-2014 |
| 20140027923 | NON-LITHOGRAPHIC HOLE PATTERN FORMATION - A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions. | 01-30-2014 |
| 20140027924 | SEMICONDUCTOR DEVICES INCLUDING SPACERS ON SIDEWALLS OF CONDUCTIVE LINES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices including spacers on sidewalls of conductive lines are provided. The semiconductor device includes bit lines on a semiconductor substrate, a storage node contact plug penetrating an insulation layer between the bit lines, triple-layered bit line spacers between the bit lines and the storage node contact plugs, and storage node electrodes on the storage node contact plugs. Each of the triple-layered bit line spacers includes a first spacer adjacent to one of the bit lines, a third spacer adjacent to the storage node contact plugs and a second spacer between the first and third spacers. The second spacer includes a lower portion having a lower dielectric constant than the first and third spacers and an upper portion having the same material as the first and third spacers. Related methods are also provided. | 01-30-2014 |
| 20140027925 | THROUGH-HOLED INTERPOSER, PACKAGING SUBSTRATE, AND METHODS OF FABRICATING THE SAME - A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer. | 01-30-2014 |
| 20140027926 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element. | 01-30-2014 |
| 20140027927 | METHOD FOR MANUFACTURING A COMPONENT HAVING AN ELECTRICAL THROUGH-CONNECTION - A method for manufacturing a component having an electrical through-connection is described. The method includes the following steps: providing a semiconductor substrate having a front side and a back side opposite from the front side, producing an insulating trench, which annularly surrounds a contact area, on the front side of the semiconductor substrate, filling the insulating trench with an insulating material, producing an electrical contact structure on the front side of the semiconductor substrate by depositing an electrically conductive material in the contact area, removing the semiconductor material remaining in the contact area on the back side of the semiconductor substrate in order to produce a contact hole which opens up the bottom side of the contact structure, and depositing a metallic material in the contact hole in order to electrically connect the electrical contact structure to the back side of the semiconductor substrate. | 01-30-2014 |
| 20140027928 | SEMICONDUCTOR DEVICE HAVING CRACK-RESISTING RING STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer. | 01-30-2014 |
| 20140027929 | Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP - A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array. | 01-30-2014 |
| 20140035153 | RECONSTITUTED WAFER-LEVEL PACKAGE DRAM - A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements. | 02-06-2014 |
| 20140035154 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side. | 02-06-2014 |
| 20140035155 | DEVICE WITH INTEGRATED POWER SUPPLY - Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts. | 02-06-2014 |
| 20140035156 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency. | 02-06-2014 |
| 20140035157 | SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE MANUFACTURING MOLD - There is provided a semiconductor package including: at least one internal lead having at least one electronic component mounted on a surface thereof; a molding unit sealing the electronic component and the internal lead; at least one external lead extending from the internal lead and protruding outwardly from ends of the molding unit; and a stopper provided on the external lead. | 02-06-2014 |
| 20140035158 | Integrated Semiconductor Device and Wafer Level Method of Fabricating the Same - The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad. | 02-06-2014 |
| 20140035159 | MULTILEVEL INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME - A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via. | 02-06-2014 |
| 20140035160 | TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA - An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements. | 02-06-2014 |
| 20140035161 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip. | 02-06-2014 |
| 20140035162 | Interface Substrate with Interposer - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 02-06-2014 |
| 20140035163 | Semiconductor Package with Interface Substrate Having Interposer - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 02-06-2014 |
| 20140035164 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure. | 02-06-2014 |
| 20140042637 | LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE - A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system. | 02-13-2014 |
| 20140042638 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, which includes: a soft layer having opposite first and second surfaces and first conductive through hole vias; a chip embedded in the soft layer and having an active surface exposed from the first surface of the soft layer; a support layer formed on the second surface of the soft layer and having second conductive through hole vias in electrical connection with the first conductive through hole vias; a first RDL structure formed on the first surface of the soft layer and electrically connected to the active surface of the chip; and a second RDL structure formed on the support layer and electrically connected to the first RDL structure through the first and second conductive through hole vias. The invention prevents package warpage by providing the support layer, and allows disposing of other packages or electronic elements by electrically connecting the RDL structures through the conductive through hole vias. | 02-13-2014 |
| 20140042639 | APPARATUS, SYSTEM, AND METHOD FOR WIRELESS CONNECTION IN INTEGRATED CIRCUIT PACKAGES - Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed. | 02-13-2014 |
| 20140042640 | DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS - A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns. | 02-13-2014 |
| 20140048946 | SENSOR PACKAGES AND METHOD OF PACKAGING DIES OF VARIOUS SIZES | 02-20-2014 |
| 20140048947 | SYSTEM PACKAGE - A system package includes an interposer, a control chip mounted onto the interposer, and first and second semiconductor chips mounted onto the interposer and electrically coupled to the control chip through the interposer. The first and second chips are configured to operate under the control of the control chip. The first semiconductor chip is positioned along one side of the control chip, and the second semiconductor chip is positioned along another side of the control chip. | 02-20-2014 |
| 20140048948 | SEMICONDUCTOR MEMORY DEVICE INCLUDING ALIGNMENT KEY STRUCTURES - A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions. | 02-20-2014 |
| 20140048949 | THERMALLY ENHANCED INTERCONNECT SUBSTRATE WITH EMBEDDED SEMICONDUCTOR DEVICE AND BUILT-IN STOPPER AND METHOD OF MAKING THE SAME - The present invention relates to a thermally enhanced interconnect substrate and a method of making the same. In accordance with one preferred embodiment, the method includes: forming a stopper on a metal layer of a laminate substrate; removing a selected portion of the metal layer to form a paddle layer; mounting a semiconductor device on the paddle layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the laminate substrate; forming first and second build-up circuitries that cover the semiconductor device, the paddle layer and the stiffener at both sides; and providing a plated through-hole that provides an electrical connection between the first and second build-up circuitries. Accordingly, the paddle layer can provide excellent heat spreading, and the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry. | 02-20-2014 |
| 20140048950 | THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH EMBEDDED SEMICONDUCTOR DEVICE AND BUILT-IN STOPPER AND METHOD OF MAKING THE SAME - The present invention relates to a thermally enhanced semiconductor assembly and a method of making the same. In accordance with one preferred embodiment, the method includes: forming a stopper on a metal layer; mounting a semiconductor device on the metal layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the metal layer; forming a build-up circuitry that covers the stopper, the semiconductor device and the stiffener; providing a plated through-hole that provides an electrical connection between the build-up circuitry and the metal layer; and removing selected portions of the metal layer to form a thermal pad and a terminal. Accordingly, the thermal pad can provide excellent heat spreading, and the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry. | 02-20-2014 |
| 20140048951 | SEMICONDUCTOR ASSEMBLY WITH DUAL CONNECTING CHANNELS BETWEEN INTERPOSER AND CORELESS SUBSTRATE - A semiconductor assembly includes a semiconductor device, a through-via interposer, a coreless substrate and a stiffener. The semiconductor device is flip mounted on the interposer, and the interposer is affixed on the coreless substrate by adhesive and extends into an aperture of a stiffener which provides mechanical support for the coreless substrate. The electrically connection between the interposer and the coreless substrate includes bond wire and conductive micro-via. The coreless substrate can provide fan-out routing for the interposer. | 02-20-2014 |
| 20140048952 | SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA STRUCTURES AND REDISTRIBUTION STRUCTURES - Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer. | 02-20-2014 |
| 20140048953 | SEMICONDUCTOR STRUCTURES INCLUDING SUB-RESOLUTION ALIGNMENT MARKS - A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed. | 02-20-2014 |
| 20140048954 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES WITH PLURAL ACTIVE CHIPS - A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle. | 02-20-2014 |
| 20140048955 | SEMICONDUCTOR ASSEMBLY BOARD WITH BACK-TO-BACK EMBEDDED SEMICONDUCTOR DEVICES AND BUILT-IN STOPPERS - In a preferred embodiment, a semiconductor assembly board with back-to-back embedded devices and built-in stoppers includes an intermediate layer, a first stopper, a first semiconductor device, a first core layer, a second stopper, a second semiconductor device, a second core layer, a first build-up circuitry, a second build-up circuitry and a plated through hole. The first and second semiconductor devices are mounted on opposite surfaces of the intermediate layer using the first and second stoppers as placement guides that are laterally aligned with peripheral edges of the first and second semiconductor devices. The first and second core layers laterally cover the first and second semiconductor devices. The first and second build-up circuitries cover the semiconductor devices and the core layers in the opposite vertical directions and provide signal routing for the first and second semiconductor devices. | 02-20-2014 |
| 20140048956 | FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES - Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts. | 02-20-2014 |
| 20140054789 | Multi-Level Vertical Plug Formation With Stop Layers of Increasing Thicknesses - A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers. | 02-27-2014 |
| 20140054790 | THREE-DIMENSIONAL INTEGRTED CIRCUIT STRUCTURE AND METHOD OF ALUMINUM NITRIDE INTERPOSER SUBSTRATE - A three-dimensional integrateds circuit structure includes a first metal circuit substrate, an interposer substrate disposed on the first metal circuit substrate and electrically connected therewith, and at least one semiconductor component disposed on the interposer substrate. The interposer substrate is used to dissipate the heat generated by the operation of the semiconductor components, so as to achieve the objective of increasing the lifespan of the semiconductor components. | 02-27-2014 |
| 20140054791 | THROUGH SILICON VIA PACKAGING STRUCTURES AND FABRICATION METHOD - A method is provided for fabricating a through silicon via packaging structure. The method includes providing a first type substrate, and forming a second type substrate deferent from the first type substrate on the first type substrate. The method also includes forming a semiconductor device on a first surface of the second type substrate, and forming an interlayer dielectric layer on the first surface of the second type substrate. Further, the method includes forming a metal interconnection structure in the interlayer dielectric layer, and forming a through silicon via structure perforating the second type substrate and electrically connecting with the metal interconnection structure. Further, the method also includes removing the first type substrate using a gas etching process or a wet etching process to expose a second surface of the second type substrate and a bottom surface of the through silicon via structure. | 02-27-2014 |
| 20140054792 | PACKAGE ASSEMBLY AND METHOD OF MANUFACTURING THE SAME - A package assembly includes a substrate, an electronic component, and an encapsulation body. The electronic component is located on the substrate and electrically connected to the substrate. The encapsulation body encapsulates the electronic component with the substrate. A portion of the substrate corresponding to the electronic component defines a plurality of through holes. A diameter of each of the plurality of through holes gradually reduces from a top surface of the substrate toward a bottom surface of the substrate. The plurality of through holes prevent melting remnants of the encapsulation body from flowing outside of the substrate. | 02-27-2014 |
| 20140054793 | Chip on Film (COF) Substrate, COF Package and Display Device Including the Same - A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film. | 02-27-2014 |
| 20140061935 | METHOD FOR MANUFACTURING A LAYER ARRANGEMENT, AND A LAYER ARRANGEMENT - A method for manufacturing a layer arrangement in accordance with various embodiments may include: providing a first layer having a side; forming one or more nanoholes in the first layer that are open towards the side of the first layer; depositing a second layer over the side of the first layer. | 03-06-2014 |
| 20140061936 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 03-06-2014 |
| 20140061937 | Fan-Out Package Comprising Bulk Metal - A device includes a polymer, a device die in the polymer, and a plurality of Through Assembly Vias (TAVs) extending from a top surface to a bottom surface of the polymer. A bulk metal feature is located in the polymer and having a top-view size greater than a top-view size of each of the plurality of TAVs. The bulk metal feature is electrically floating. The polymer, the device die, the plurality of TAVs, and the bulk metal feature are portions of a package. | 03-06-2014 |
| 20140061938 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed allowing detection of a connection state of a Through Silicon Via (TSV) at a wafer level. The semiconductor device includes a first line formed over a Through Silicon Via (TSV), a second line formed over the first line, and a first power line and a second power line formed over the same layer as the second line. Therefore, the semiconductor device can screen not only a chip-to-chip connection state after packaging completion, but also a connection state between the TSV and the chip at a wafer level, so that unnecessary costs and time encountered in packaging of a defective chip are reduced. | 03-06-2014 |
| 20140061939 | SEMICONDUCTOR DEVICES HAVING BIT LINE CONTACT PLUGS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction. | 03-06-2014 |
| 20140061940 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Technology that achieves high integration of a semiconductor device employing TSV technology is provided. A through electrode is configured by a small-diameter through electrode having a first diameter and being formed on a main surface side of a semiconductor wafer, and a large-diameter through electrode having a second diameter larger than the above-described first diameter and being formed on a back surface side of the semiconductor wafer, and the small-diameter through electrode is arranged inside the large-diameter through electrode in a planar view so that a center position of the small-diameter through electrode and a center position of the large-diameter through electrode do not overlap with each other in the planar view. | 03-06-2014 |
| 20140061941 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching stopper film over a first interlayer insulating film; forming an inorganic insulating film over the etching stopper film; forming a resist film over the inorganic insulating film; selectively etching the etching stopper film and the inorganic insulating film by using the resist film as a mask to form a first opening in the etching stopper film and to form a second opening in the inorganic insulating film; removing the resist film by O | 03-06-2014 |
| 20140061942 | HETEROGENEOUS ANNEALING METHOD AND DEVICE - A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts. | 03-06-2014 |
| 20140061943 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 03-06-2014 |
| 20140061944 | Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP - A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. | 03-06-2014 |
| 20140061945 | Semiconductor Package Including a Substrate and an Interposer - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 03-06-2014 |
| 20140061946 | Semiconductor Package Including Interposer with Through-Semiconductor Vias - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 03-06-2014 |
| 20140070422 | Semiconductor Device with Discrete Blocks - A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers. | 03-13-2014 |
| 20140070423 | TUNABLE COMPOSITE INTERPOSER - A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure. | 03-13-2014 |
| 20140070424 | SEMICONDUCTOR PACKAGE, METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE, AND INTERPOSER STRUCTURE OF THE SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. | 03-13-2014 |
| 20140070425 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires. | 03-13-2014 |
| 20140070426 | INTEGRATED CIRCUIT DEVICES INCLUDING A VIA STRUCTURE AND METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING A VIA STRUCTURE - Integrated circuit devices are provided. The integrated circuit devices may include a via structure including a conductive plug, a conductive barrier layer spaced apart from the conductive plug, and an insulating layer between the conductive plug and conductive barrier layer. Related methods of forming integrated circuit devices are also provided. | 03-13-2014 |
| 20140070427 | Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding - A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers. | 03-13-2014 |
| 20140077383 | STRUCTURE AND METHOD OF MAKING AN OFFSET-TRENCH CRACKSTOP THAT FORMS AN AIR GAP ADJACENT TO A PASSIVATED METAL CRACKSTOP - A structure and method of making an offset-trench crackstop, which forms an air gap in a passivation layer that is adjacent to a passivated top metal layer of a metal crackstop in an integrated circuit (IC) die. The offset-trench crackstop may expose a portion of a topmost dielectric layer in the crackstop region, not expose a topmost patterned metal layer of the metal crackstop, and may be interposed between the metal crackstop and an active device region. Alternatively, the offset-trench crackstop may expose a portion of the topmost dielectric layer, which separates an outermost metal layer and an innermost metal layer of the metal crackstop, and does not expose any of the topmost patterned metal layer of the metal crackstop, where the innermost metal layer of the metal crackstop is interposed between the offset-trench crackstop in the crackstop region and the active device region of the IC die. | 03-20-2014 |
| 20140077384 | BIT CELL WITH TRIPLE PATTERNED METAL LAYER STRUCTURES - An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure that is a first one of a word line structure, a ground line structure, a power line structure, and a bit line structure; providing, via a second patterning process of the metal layer, a second structure that is different from the first structure and that is a second one of the word line structure, the ground line structure, the power line structure, and the bit line structure; and providing, via a third patterning process of the metal layer, a third structure that is different from the first structure and the second structure, and that is a third one of the word line structure, the ground line structure line, the power line structure, and the bit line structure. | 03-20-2014 |
| 20140077385 | SEMICONDUCTOR PACKAGE DEVICE HAVING PASSIVE ENERGY COMPONENTS - A semiconductor package device is disclosed that includes a passive energy component integrated therein. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to the first surface. The semiconductor package device also includes a passive energy component positioned over the second surface. The passive energy component is electrically connected to one or more integrated circuits. The semiconductor package device also includes an encapsulation structure disposed over the second surface and at least substantially encapsulates the passive energy component. | 03-20-2014 |
| 20140077386 | 3D IC and 3D CIS Structure - An embodiment integrated circuit includes a first device supporting a first back end of line layer, the first back end of line layer including a first alignment marker, and a second device including a spin-on glass via and supporting a second back end of line layer, the second back end of line layer including a second alignment marker, the spin-on glass via permitting the second alignment marker to be aligned with the first alignment marker using ultraviolet light. | 03-20-2014 |
| 20140077387 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. | 03-20-2014 |
| 20140077388 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a device chip coupled to an electrode chip. The device chip includes a first device electrode on a first substrate, and the electrode chip includes a first pad electrode extending at least partially through a second substrate. The first pad electrode is electrically connected to the first device electrode and includes spaced conductive sections which serve as a heat dissipating structure to transfer heat received from the device chip and the electrode chip. A method for making a semiconductor device includes using the substrate of the electrode chip as a support during thinning the substrate of the device chip. | 03-20-2014 |
| 20140077389 | Semiconductor Device and Method of Using Substrate Having Base and Conductive Posts to Form Vertical Interconnect Structure in Embedded Die Package - A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts. | 03-20-2014 |
| 20140077390 | ELECTRONIC APPARATUS - An electronic apparatus includes a multilayered structure in which a plurality of semiconductor chips provided with semiconductor devices are stacked, penetrating electrodes penetrating the semiconductor chips and electrically connecting the semiconductor devices of the plurality of semiconductor chips, an MEMS chip mounted on the multilayered structure and provided with an MEMS device, wherein pads connecting to the penetrating electrodes are provided on the MEMS chip. | 03-20-2014 |
| 20140077391 | SEMICONDUCTOR DEVICE - A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes. | 03-20-2014 |
| 20140077392 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device has insulating films | 03-20-2014 |
| 20140077393 | APPARATUS AND METHOD FOR HIGH DENSITY MULTI-CHIP STRUCTURES - Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which improves device performance and speed. | 03-20-2014 |
| 20140084476 | Thermal Dissipation Through Seal Rings in 3DIC Structure - A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via. | 03-27-2014 |
| 20140084477 | NOISE ATTENUATION WALL - An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects. | 03-27-2014 |
| 20140084478 | MOLD CHASE FOR INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards a mold chase for integrated circuit package assembly and associated techniques and configurations. In one embodiment, a method includes receiving a package substrate, the package substrate including a first die mounted on the package substrate by a plurality of first interconnect structures, and a plurality of second interconnect structures disposed on the package substrate and configured to route electrical signals of a second die, protecting a top surface of individual interconnect structures of the plurality of second interconnect structures from deposition of a mold material, and depositing the mold material on the package substrate between the individual interconnect structures of the plurality of second interconnect structures. Other embodiments may be described and/or claimed. | 03-27-2014 |
| 20140084479 | Integrated Circuit Formed Using Spacer-Like Copper Deposition - A method of forming a semiconductor device includes depositing a metal spacer over a core supported by a first extremely low-k dielectric layer having metal contacts embedded therein, etching away an upper portion of the metal spacer to expose the core between remaining lower portions of the metal spacer, removing the core from between the remaining lower portions of the metal spacer, and depositing a second extremely low-k dielectric layer over the remaining lower portions of the metal spacer. | 03-27-2014 |
| 20140084480 | SEMICONDUCTOR PACKAGE SUBSTRATES HAVING LAYERED CIRCUIT SEGMENTS AND RELATED METHODS - The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer. | 03-27-2014 |
| 20140084481 | SYSTEM AND METHOD OF NOVEL ENCAPSULATED MULTI METAL BRANCH FOOT STRUCTURES FOR ADVANCED BACK END OF LINE - A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers. | 03-27-2014 |
| 20140084482 | MICRO DEVICE STABILIZATION POST - A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface. | 03-27-2014 |
| 20140084483 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure comprises a substrate, a plurality of first electronic components, at least a second electronic component, a first covering layer and a wiring layer. A surface of the substrate includes a first region and a second region. The first electronic components are disposed in the first region, wherein at least one of the first electronic components has a first conductive contact. The second electronic component is disposed in the second region. The first covering layer includes a recess and a first exposing region for exposing the first conductive contact. The wiring layer is formed on the recess and electronically coupled to the first conductive contact. | 03-27-2014 |
| 20140084484 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element. | 03-27-2014 |
| 20140084485 | RELIABLE PACKAGING AND INTERCONNECT STRUCTURES - Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. | 03-27-2014 |
| 20140084486 | RELIABLE INTERCONNECT FOR SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material. | 03-27-2014 |
| 20140091473 | NOVEL THREE DIMENSIONAL INTEGRATED CIRCUITS STACKING APPROACH - A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die. | 04-03-2014 |
| 20140091474 | LOCALIZED HIGH DENSITY SUBSTRATE ROUTING - Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over |
