Class / Patent application number | Description | Number of patent applications / Date published |
257771000 | Alloy containing aluminum | 26 |
20080258307 | Integration type semiconductor device and method for manufacturing the same - A semiconductor device includes: a plurality of power MOS cells on a semiconductor substrate; a plurality of lead wires connecting to a source and a drain of each power MOS cell through a contact hole; a plurality of collecting electrodes connecting in parallel with the lead wires through a via hole; an interlayer protection film on the collecting electrode; a thick film electrode connecting to the collecting electrode through the opening; and a terminal protection film having an opening for bonding connection. The openings are formed in the interlayer protection film such that a portion between the openings becomes a beam shape | 10-23-2008 |
20090008786 | Sputtering Target - The present invention provides a sputtering target comprising aluminum and one or more alloying elements including Ni, Co, Ti, V, Cr, Mn, Mo, Nb, Ta, W, and rare earth metals (REM). The addition of very small amounts of alloying element to pure aluminum and aluminum alloy target improves the uniformity of the deposited wiring films through affecting the target's recrystallization process. The range of alloying element content is 0.01 to 100 ppm and preferably in the range of 0.1 to 50 ppm and more preferably from 0.1 to 10 ppm weight which is sufficient to prevent dynamic recrystallization of pure aluminum and aluminum alloys, such as 30 ppm Si alloy. The addition of small amount of alloying elements increases the thermal stability and electromigration resistance of pure aluminum and aluminum alloys thin films while sustaining their low electrical resistivity and good etchability. This invention also provides a method of manufacturing microalloyed aluminum and aluminum alloy sputtering target. | 01-08-2009 |
20090032958 | Intermetallic conductors - Intermetallic conductive materials are used to form interconnects in an integrated circuit. In some cases, the intermetallic conductive material may be an intermetallic alloy of aluminum. | 02-05-2009 |
20090079081 | ELECTRONIC DEVICE WITH WIRE BONDS ADHERED BETWEEN INTEGRATED CIRCUITS DIES AND PRINTED CIRCUIT BOARDS - An electronic device that has an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors corresponding to each of the contact pads respectively, wire bonds electrically connecting each of the contact pads to the corresponding conductors and, an adhesive surface positioned between the contacts pads and the corresponding conductors. The wire bonds are secured to the adhesive surface to hold them in a low profile configuration. | 03-26-2009 |
20090194880 | WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE - Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste. | 08-06-2009 |
20100065969 | Integrated circuit device - An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer. | 03-18-2010 |
20100171222 | HIGH RELIABILITY Au ALLOY BONDING WIRE AND SEMICONDUCTOR DEVICE OF SAME - [Issues to be Solved] Providing enhanced bonding reliability of Au alloy bonding wire with low electrical resistivity to Al electrode of semiconductor device, and its application of semiconductor device is bonded with Al electrode pad by the same wire. | 07-08-2010 |
20100181676 | SUBSTRATE BONDING WITH METAL GERMANIUM SILICON MATERIAL - A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate is formed a first layer comprising silicon. A second layer comprising germanium and silicon is formed on the first layer. A third layer comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting the MEMS. | 07-22-2010 |
20100276807 | FABRICATION OF METAL FILM STACKS HAVING IMPROVED BOTTOM CRITICAL DIMENSION - A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier. | 11-04-2010 |
20110169168 | THROUGH-SILICON VIA FORMED WITH A POST PASSIVATION INTERCONNECT STRUCTURE - An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced apart from the TSV, and an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV. | 07-14-2011 |
20110309512 | Semiconductor Device - Embodiments of the invention provide a semiconductor device having high reliability as they ease the thermal stress or a heat distortion or strain occurring during the manufacturing process or during operation, and the embodiments function with stability for a long time. A semiconductor device has a semiconductor substrate, an insulating ceramic plate on which the semiconductor substrate is mounted and stress buffer | 12-22-2011 |
20120018890 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a supporting board, an electrode surface processing layer formed on the supporting board, a semiconductor element, and a solder material containing a first metal composed mainly of bismuth and a second metal having a higher melting point than the first metal and joining the electrode surface processing layer and the semiconductor element, the first metal containing particles of the second metal inside the first metal. The composition ratio of the second metal is higher than the first metal in a region of the solder material corresponding to the center portion of the semiconductor element, and the composition ratio of the second metal is at least 83.8 atomic percent in the region corresponding to the center portion. | 01-26-2012 |
20120098137 | ELEMENT MOUNTING SUBSTRATE AND SEMICONDUCTOR MODULE - Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics. | 04-26-2012 |
20120217641 | Preventing the Cracking of Passivation Layers on Ultra-Thick Metals - A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33. | 08-30-2012 |
20120223432 | MOISTURE BARRIER FOR A WIRE BOND - An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the wire and a silicon nitride or silicon carbonyl layer covering the intermetallic compound interface | 09-06-2012 |
20120319283 | SEMICONDUCTOR DEVICE HAVING EXTERNAL ELECTRODES EXPOSED FROM ENCAPSULATION MATERIAL - A semiconductor device includes a semiconductor element including an anode electrode and a cathode electrode, an encapsulating material which covers the semiconductor element, a first external electrode which is electrically connected to the cathode electrode and is at least partially exposed outside of the encapsulating material, a second external electrode which is electrically connected to the anode electrode and is at least partially exposed outside of the encapsulating material, and a sacrificial metallic body which is arranged outside of the encapsulating material so as to be in direct contact with the first external electrode or to be electrically connected to the first external electrode through saltwater, and contains metal having larger ionization tendency than any metal contained in the first external electrode. | 12-20-2012 |
20130082387 | POWER SEMICONDUCTOR ARRANGEMENT AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR ARRANGEMENT - In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization. | 04-04-2013 |
20130087919 | LIGHTWEIGHT AND COMPACT THROUGH-SILICON VIA STACK PACKAGE WITH EXCELLENT ELECTRICAL CONNECTIONS AND METHOD FOR MANUFACTURING THE SAME - A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections. | 04-11-2013 |
20130161820 | METHOD FOR BONDING TWO SILICON SUBSTRATES, AND A CORRESPONDEING SYSTEM OF TWO SILICON SUBSTRATES - A method for bonding two silicon substrates and a corresponding system of two silicon substrates. The method includes: providing first and second silicon substrates; depositing a first bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1 and 5% on a first bonding surface of the first silicon substrate; depositing a second bonding layer of germanium above the first bonding surface or above a second bonding surface of the second silicon substrate; subsequently joining the first and second silicon substrates, so that the first and the second bonding surfaces lie opposite each other; and implementing a thermal treatment step to form an eutectic bonding layer of aluminum-germanium or containing aluminum-germanium as the main component, between the first silicon substrate and the second silicon substrate, spikes which contain aluminum as a minimum and extend into the first silicon substrate, forming at least on the first bonding surface. | 06-27-2013 |
20140145341 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element that includes an electrode layer on a surface of the semiconductor element; a low-strength layer that is provided on a surface of the electrode layer; a bonding layer that is provided on a surface of the low-strength layer; and a conductive plate that is provided on a surface of the bonding layer. Strength of the bonding layer is higher than strength of the electrode layer, and strength of the low-strength layer is lower than the strength of the electrode layer. | 05-29-2014 |
20140151889 | TECHNIQUES FOR ENHANCING DIELECTRIC BREAKDOWN PERFORMANCE - Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (E | 06-05-2014 |
20140353833 | Stress Compensation Layer to Improve Device Uniformity - The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices. | 12-04-2014 |
20150054163 | Systems and Methods to Enhance Passivation Integrity - A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids. | 02-26-2015 |
20160013149 | ELECTRONIC DEVICE | 01-14-2016 |
20160064350 | CONNECTION ARRANGEMENT OF AN ELECTRIC AND/OR ELECTRONIC COMPONENT - A connection arrangement includes at least one electric and/or electronic component. The at least one electric and/or electronic component has at least one connection face, which is connected in a bonded manner to a join partner by means of a connection layer. The connection layer can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer is arranged adjacent to the connection layer in a bonded manner. The reinforcement layer has a higher modulus of elasticity than the connection layer. A particularly good protective effect is achieved if the reinforcement layer is formed in a frame-like manner by an outer and an inner boundary and, at least with the outer boundary thereof, encloses the connection face of the at least one electric and/or electronic component. | 03-03-2016 |
20160082552 | ZN BASED LEAD-FREE SOLDER AND SEMICONDUCTOR POWER MODULE - Zn based lead-free solder is obtained in which its range of practical melting points is between 300° C. and 350° C. The Zn based lead-free solder includes a Cr content of 0.05 through 0.2 wt %, an Al content of 0.25 through 1.0 wt %, an Sb content of 0.5 through 2.0 wt %, a Ge content of 1.0 through 5.8 wt %, and a Ga content of 5 through 10 wt %; or the Zn based lead-free solder includes a Cr content of 0.05 through 0.2 wt %, an Al content of 0.25 through 1.0 wt %, an Sb content of 0.5 through 2.0 wt %, a Ge content of 1.0 through 5.8 wt %, and an In content of 10 through 20 wt %. | 03-24-2016 |