| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257769000 | Platinum group metal or silicide thereof | 44 |
| 20080230915 | SEMICONDUCTOR PACKAGE USING WIRES CONSISTING OF Ag OR Ag ALLOY - A semiconductor package using Ag or Ag alloy wire which can maintain superior reliability against a noble metal and lower its manufacturing cost is provided. The semiconductor package comprises a semiconductor substrate. A semiconductor chip is attached to the package substrate and has one or more pads which comprise a noble metal. And one or more wires are bonded so as to electrically connect the one or more pads and the package substrate and comprise Ag or Ag alloy. | 09-25-2008 |
| 20080315426 | METAL CAP WITH ULTRA-LOW k DIELECTRIC MATERIAL FOR CIRCUIT INTERCONNECT APPLICATIONS - An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided. | 12-25-2008 |
| 20090008785 | ETCH PROCESS FOR IMPROVING YIELD OF DIELECTRIC CONTACTS ON NICKEL SILICIDES - The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device | 01-08-2009 |
| 20090134522 | Micro-Electromechanical System Memory Device and Method of Making the Same - A method of manufacturing a non-volatile memory bitcell comprises the steps of depositing a first layer of conductive material on a substrate and patterning and etching the first layer of conductive material to form three non-linearly disposed electrodes. The method also comprises the steps of depositing a first layer of sacrificial material on the electrodes and the substrate and providing an elongate cantilever structure on the first layer of sacrificial material such that the cantilever structure and at least a portion of each electrode overlap each other. The method also includes the steps of depositing a second layer of sacrificial material on the cantilever structure and the first layer of sacrificial material and providing a capping layer on the second layer of sacrificial material and providing holes in the capping layer such that at least a portion of the second layer of sacrificial material is exposed. Finally, the method provides the step of removing the first and second layers of sacrificial material through the holes provided in the capping layer, thereby defining a cavity in which the cantilever structure is suspended. | 05-28-2009 |
| 20090152729 | Semiconductor device - An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating resin. Lead frames are provided in both sides of the lead frame. A portion of the lead frame is encapsulated with the encapsulating resin to function as an inner lead. The encapsulating resin is composed of a resin composition that contains substantially no halogen. Further, an exposed portion of the Al pad provided in the semiconductor chip is electrically connected to the inner lead via the AuPd wire. | 06-18-2009 |
| 20090189287 | NOBLE METAL CAP FOR INTERCONNECT STRUCTURES - An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface. | 07-30-2009 |
| 20090309228 | METHOD FOR FORMING SELF-ALIGNED METAL SILICIDE CONTACTS - The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching. | 12-17-2009 |
| 20100090345 | DIRECT GROWTH OF METAL NANOPLATES ON SEMICONDUCTOR SUBSTRATES - Metal nanoplates are grown on n-type and p-type semiconductor wafer substrates through galvanic reactions between substantially pure aqueous metal solutions and the substrates. The morphology of the resulting metal nanoplates that protrude from the substrate can be tuned by controlling the concentration of the metal solution and the reaction time of the solution with the semiconductor wafer. Nanoplate size gradually increases with prolonged growth time and the nanoplate thicknesses increases in a unique stepwise fashion due to polymerization and fusion of adjacent nanoplates. Further, the roughness of the nanoplates can also be controlled. In a particular embodiment, Ag nanoplates are grown on a GaAs substrate through reaction with a solution of AgNO | 04-15-2010 |
| 20100140804 | Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance - Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed. | 06-10-2010 |
| 20100171221 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor device and its manufacturing method including the steps of: forming a first semiconductor element layer having a first wiring over a substrate; forming a second semiconductor element layer having a second wiring and fixed to a first structure body having a first sheet-like fiber body, a first organic resin, and a first electrode; preparing a second structure body having a second sheet-like fiber body, a second organic resin which is not cured, and a second electrode; disposing the second structure body between the first and second semiconductor element layers so that the first wiring, the second electrode, and the second wiring are overlapped with each other over the substrate; and curing the second organic resin. | 07-08-2010 |
| 20100301485 | ELECTRONIC DEVICE, CONDUCTIVE COMPOSITION, METAL FILLING APPARATUS, AND ELECTRONIC DEVICE MANUFACTURING METHOD - An electronic device includes a plurality of stacked substrates. Each of the substrates includes a semiconductor substrate, a columnar conductor, and a ring-shaped insulator. The columnar conductor extends along a thickness direction of the semiconductor substrate. The ring-shaped insulator includes an inorganic insulating layer mainly composed of a glass. The inorganic insulating layer fills a ring-shaped groove that is provided in the semiconductor substrate to surround the columnar conductor. | 12-02-2010 |
| 20110079910 | DUAL METAL INTERCONNECTS FOR IMPROVED GAP-FILL, RELIABILITY, AND REDUCED CAPACITANCE - Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed. | 04-07-2011 |
| 20110204521 | CHIP-SCALE SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A chip-scale semiconductor device package includes a die, an insulating substrate having a through hole, a first metal layer, a second metal layer, and an insulating layer. The first metal layer is on a first surface of the insulating substrate and a first side of the through hole. The insulating layer is overlaid on a second surface of the insulating substrate and surrounds a second side of the through hole. The second metal is on the insulating layer and the second side of the through hole. The die is in the through hole and includes a first electrode and a second electrode. The first electrode is electrically connected to the first metal layer, and the second electrode is electrically connected to the second metal layer. | 08-25-2011 |
| 20110233784 | COMPOSITE SUBSTRATE FOR A SEMICONDUCTOR CHIP - A composite substrate for a semiconductor chip includes a first covering layer containing a semiconductor material, a second covering layer, and a core layer arranged between the first covering layer and the second covering layer, wherein the core layer has a greater coefficient of thermal expansion than the covering layers. | 09-29-2011 |
| 20110241213 | Silicide Contact Formation - A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less. | 10-06-2011 |
| 20110260325 | SEMICONDUCTOR DEVICE - To provide a semiconductor device including vertically formed nanowires in which parasitic capacitance is prevented from increasing and time constant associated with an operation speed is improved. Two different layers, which are a film thickness adjustment layer and a protective insulating layer, are provided as an interlayer insulating film between an electrode and a planar main surface of an electrically conductive substrate. This structural characteristic can reduce parasitic capacitance generated among the nanowires which electrically connect the planar main surface and the electrode to each other, the electrically conductive substrate, and the electrode, while controlling peel-off of a low dielectric film having a poor adhesion by separating the low dielectric film from the electrode with the protective insulating layer interposed therebetween. | 10-27-2011 |
| 20120001336 | CORROSION-RESISTANT COPPER-TO-ALUMINUM BONDS - A connection formed by a copper wire ( | 01-05-2012 |
| 20120038051 | BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME - A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect. | 02-16-2012 |
| 20120061842 | STACK PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stack package includes a substrate, a lower semiconductor chip stacked on the substrate and electrically connected to the substrate through a lower via, a plurality of upper semiconductor chips stacked on the lower semiconductor chip and electrically connected to the lower via through an upper via, wherein the upper semiconductor chips are larger in size than the lower semiconductor chip, and an edge guide electrically connecting edge vias of the upper semiconductor chips and the substrate. | 03-15-2012 |
| 20120061843 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having a first surface, on which an electrode pad is arranged, and a second surface which is the other side of the semiconductor chip, an insulation member formed on the second surface of the semiconductor chip, and comprising a via hole at a position spaced apart from the semiconductor chip, and a conductive filler filling the via hole. | 03-15-2012 |
| 20120139118 | SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP FOR REDUCING OPEN FAILURES - A semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface, a chip pad disposed on the first surface of the substrate, and a through-silicon via (TSV) including a plurality of sub vias electrically connected to the chip pad at different positions. | 06-07-2012 |
| 20120153487 | SUBSTRATE FOR ELECTRON-BEAM DRAWING - A substrate for electron-beam drawing, characterized by including a base layer | 06-21-2012 |
| 20120181697 | METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE - A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm. | 07-19-2012 |
| 20120193797 | 3D INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A 3D integrated circuit structure comprises a first chip, wherein the first chip comprises: a substrate; a semiconductor device formed on the substrate and a dielectric layer formed on both the substrate and the semiconductor device; a conductive material layer formed within a through hole penetrating through both the substrate and the dielectric layer; a stress releasing layer surrounding the through hole; and a first interconnecting structure connecting the conductive material layer with the semiconductor device. By forming a stress releasing layer to partially release the stress caused by the conductive material in the via, the stress caused by mismatch of CTE between the conductive material and the semiconductor (for example, silicon) surrounding it can be reduced, thereby enhancing the performance of the semiconductor device and the corresponding 3D integrated circuit consisting of the semiconductor devices. | 08-02-2012 |
| 20120241963 | SELF-ALIGNED SILICIDE FORMATION ON SOURCE/DRAIN THROUGH CONTACT VIA - According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process. | 09-27-2012 |
| 20120292774 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor element having an electrode pad; a substrate over which the semiconductor element is mounted and has an electrical bonding part; and a bonding wire electrically connecting the electrode pad to the electrical bonding part, wherein a main metal component of the electrode pad is the same or different from a main metal component of the bonding wire, and when the main metal component of the electrode pad is different from the main metal components of the bonding wire, a rate of interdiffusion of the main metal components of the bonding wire and the electrode pad at a junction of the bonding wire and the electrode pad under a post-curing temperature of an encapsulating resin is lower than that of interdiffusion of gold (Au) and aluminum (Al) at a junction of aluminum (Al) and gold (Au) under the post-curing temperature. | 11-22-2012 |
| 20120326316 | METAL CONTACTS FOR MOLECULAR DEVICE JUNCTIONS AND SURFACE-DIFFUSION-MEDIATED DEPOSITION - Metal contact formation for molecular device junctions by surface-diffusion-mediated deposition (SDMD) is described. In an example, a method of fabricating a molecular device junction by surface-diffusion-mediated deposition (SDMD) includes forming a molecular layer above a first region of a substrate. A region of metal atoms is formed above a second region of the substrate proximate to, but separate from, the first region of the substrate. A metal contact is then formed by migrating metal atoms from the region of metal atoms onto the molecular layer. | 12-27-2012 |
| 20120326317 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The present invention discloses a semiconductor device and a manufacturing method therefor. Conventionally, platinum is deposited in a device substrate to suppress diffusion of nickel in nickel silicide. However, introducing platinum by means of deposition makes the platinum only stay on the surface but fails to effectively suppress the diffusion of nickel over a desirable depth. According to the present invention, a semiconductor device is formed by implanting platinum into a substrate and forming NiSi in a region of the substrate where platinum is implanted. With the present invention, platinum can be distributed over a desirable depth range so as to more effectively suppress nickel diffusion. | 12-27-2012 |
| 20120326318 | BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF - A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region. | 12-27-2012 |
| 20130001789 | INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME - Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided. | 01-03-2013 |
| 20130069237 | PLATINUM-CONTAINING CONSTRUCTIONS, AND METHODS OF FORMING PLATINUM-CONTAINING CONSTRUCTIONS - Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide. Chemical-mechanical polishing is utilized to form a planarized surface extending across the platinum-containing material and the metal oxide. | 03-21-2013 |
| 20130069238 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A first wiring is disposed over a semiconductor substrate. A first via is disposed over the first wiring. Further, the bottom surface of the first via is in contact with the first wiring. A first insulation layer is disposed over the semiconductor substrate, and is in contact with at least the top surface of the first wiring and the side surface of the first via. At least a part of each side surface of the first wiring and the first via cuts off each metal crystal grain. | 03-21-2013 |
| 20130249099 | Techniques to Form Uniform and Stable Silicide - In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided. | 09-26-2013 |
| 20130277846 | CIRCUIT ARRANGEMENT FOR A THERMALLY CONDUCTIVE CHIP ASSEMBLY AND A MANUFACTURING METHOD - The circuit arrangement according to the invention provides a substrate ( | 10-24-2013 |
| 20130334693 | RAISED SILICIDE CONTACT - A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate. | 12-19-2013 |
| 20140061930 | OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE - A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal. | 03-06-2014 |
| 20140070419 | Platinum-Containing Constructions, and Methods of Forming Platinum-Containing Constructions - Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide. Chemical-mechanical polishing is utilized to form a planarized surface extending across the platinum-containing material and the metal oxide. | 03-13-2014 |
| 20140131877 | STRESS RELIEF STRUCTURES IN PACKAGE ASSEMBLIES - A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners of the substrate, the at least one stress relief structure being adjacent to at least one die of the one or more dies. | 05-15-2014 |
| 20140264885 | Apparatus and Method for Wafer Separation - A plurality of macro and micro alignment marks may be formed on a wafer. The macro alignment marks may be formed in pairs at opposite edges of the wafer. The micro alignment marks may be formed to align to streets on the wafer along a first and second direction. A molding compound may be formed on the wafer. The macro alignment marks may be exposed from the molding compound. A pair of the micro alignment marks may be exposed from the molding compound at opposite ends of the streets along the first and the second direction. The wafer may be aligned to a dicing tool using pairs of the macro alignment marks. The dicing tool may be aligned to the streets using pairs of the micro alignment marks. The wafer may be diced using successive pairs of micro alignment marks along the first and second direction. | 09-18-2014 |
| 20140374912 | Micro-Spring Chip Attachment Using Solder-Based Interconnect Structures - Standard solder-based interconnect structures are utilized as mechanical fasteners to attach an IC die in a “flip-chip” orientation to a support structure (e.g., a package base substrate or printed circuit board). Electrical connections between the support structure and the IC die are achieved by curved micro-springs that are disposed in peripheral regions of the IC die and extend through a gap region separating the upper structure surface and the processed surface of the IC die. The micro-springs are fixedly attached to one of the support structure and the IC die, and have a free (tip) end that contacts an associated contact pad disposed on the other structure/IC die. Conventional solder-based connection structures (e.g., solder-bumps/balls) are disposed on “dummy” (non-functional) pads disposed in a central region of the IC die. After placing the IC die on the support structure, a standard solder reflow process is performed to complete the mechanical connection. | 12-25-2014 |
| 20150028484 | RANDOM LOCAL METAL CAP LAYER FORMATION FOR IMPROVED INTEGRATED CIRCUIT RELIABILITY - A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier. | 01-29-2015 |
| 20150303142 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor substrate provided with an integrated circuit is polished by CMP or the like, and the semiconductor substrate is made into a thin film by forming an embrittlement layer in the semiconductor substrate and separating a part of the semiconductor substrate; thus, semiconductor chips such as IC chips and LSI chips which are thinner than ever are obtained. Moreover, such thinned LSI chips are stacked and electrically connected through wirings penetrating through the semiconductor substrate; thus, a three dimensional semiconductor integrated circuit with improved packing density is obtained. | 10-22-2015 |
| 20160060788 | METHOD OF FORMING METAL FILM - Provided is a metal film forming method which can form a metal film having excellent adhesion industrially advantageously and a metal film formed by using the method. A method of forming a metal film on a base includes an atomization step of atomizing a raw-material solution into a mist, in which the raw-material is prepared by dissolving or dispersing a metal in an organic solvent containing an oxidant, a chelating agent, or a protonic acid; a carrier-gas supply step of supplying a carrier gas to the mist; a mist supply step of supplying the mist onto the base using the carrier gas; and a metal-film formation step of forming the metal film on part or all of a surface of the base to causing the mist to thermally react. | 03-03-2016 |
| 20160172195 | NANOSTRUCTURES HAVING LOW DEFECT DENSITY AND METHODS OF FORMING THEREOF | 06-16-2016 |
