| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257767000 | Resistive to electromigration or diffusion of the contact or lead material | 9 |
| 20090014884 | SLOTS TO REDUCE ELECTROMIGRATION FAILURE IN BACK END OF LINE STRUCTURE - A back-end of the line (BEOL) structure and method are disclosed. In one embodiment the BEOL structure may include: a copper line in an ultra low-k dielectric, the copper line connected on one end to a cathode via and on another end to an anode via; and a plurality of slots extending laterally along a length of the copper line, the plurality of slots being non-continuous along the length of the copper line, and wherein the plurality of slots reduce electromigration failure in the BEOL structure by enabling copper extrusions to occur along the plurality of slots. | 01-15-2009 |
| 20090278260 | REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE - An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other. | 11-12-2009 |
| 20090294973 | INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS - An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w | 12-03-2009 |
| 20090302476 | Structures and Methods to Enhance CU Interconnect Electromigration (EM) Performance - The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect. | 12-10-2009 |
| 20100200993 | DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES - Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack. | 08-12-2010 |
| 20100224998 | Integrated Circuit with Ribtan Interconnects - An integrated circuit (IC) includes an interconnect system made of electrically conducting ribtan material. The integrated circuit includes a substrate, a set of circuit elements that are formed on the substrate, an interconnect system that interconnects the circuit elements. At least part of the interconnect system is made of a metallic ribtan material. | 09-09-2010 |
| 20100224999 | Method for Producing Metallic Interconnect Lines - The invention relates to a method for producing metallic interconnect lines on the surface of a substrate comprising:
| 09-09-2010 |
| 20130140701 | Solderable Contact and Passivation for Semiconductor Dies - A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites. | 06-06-2013 |
| 20160163651 | OPTIMIZED WIRES FOR RESISTANCE OR ELECTROMIGRATION - Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings. | 06-09-2016 |
