| Entries |
| Document | Title | Date |
|---|
| 20080203575 | Integrated Circuit with Re-Route Layer and Stacked Die Assembly - An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die. | 08-28-2008 |
| 20080211103 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse. | 09-04-2008 |
| 20080211104 | High Temperature, Stable SiC Device Interconnects and Packages Having Low Thermal Resistance - A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of ternary or quaternary materials. The compositions meet the conflicting requirements of an interconnect or joint that can be exposed to high temperature, and is thermally and electrically conductive, void and creep resistant, corrosion resistant, and reliable upon temperature and power cycling. | 09-04-2008 |
| 20080211105 | Method of assembling chips - A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material. | 09-04-2008 |
| 20080217783 | SEMICONDUCTOR DEVICE - A semiconductor device is provided having an insulating layer structure with a low dielectric constant and excellent barrier properties against copper. This semiconductor device has a copper wiring layer and includes at least one layered structure having a copper wiring line, an amorphous carbon film with a density of 2.4 g/cm | 09-11-2008 |
| 20080217784 | SUBSTRATE WITH FEEDTHROUGH AND METHOD FOR PRODUCING THE SAME - A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material. | 09-11-2008 |
| 20080230913 | Stackable semiconductor device and fabrication method thereof - The invention provides a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads formed on the active surface thereof and a groove formed between adjacent solder pads to form a first metal layer therein that is electrically connected to the solder pads; subsequently thinning the non-active surface of the wafer to where the grooves are located to expose the first metal layer therefrom, and forming a second metal layer on the non-active surface of the wafer for electrically connecting with the first metal layer; and separating the dies to form a plurality of stackable semiconductor devices. Thereby, the first and second metal layers formed on the active surface and the non-active surface of the semiconductor device can be stacked and connected to constitute a multi-die stack structure, thereby increasing integration without increasing the area of the stacked dies. Further, the problems known in the prior art of poor electrical connection, complicated manufacturing process and increased cost as a result of using wire bonding and TSV can be avoided. | 09-25-2008 |
| 20080230914 | SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT, MULTI-LAYER PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARD - A transition layer | 09-25-2008 |
| 20080246155 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate having a semiconductor element formed on a surface thereof; an interwiring insulating film formed above the semiconductor substrate; a wiring formed in the interwiring insulating film; a first intervia insulating film formed under the interwiring insulating film; a first via formed in the first intervia insulating film and connected to a lower surface of the wiring; a second intervia insulating film formed on the interwiring insulating film; a second via formed in the second intervia insulating film and connected to an upper surface of the wiring; and a CuSiN film formed in at least one of a position between the interwiring insulating film and the first intervia insulating film, and a position between the interwiring insulating film and the second intervia insulating film. | 10-09-2008 |
| 20080246156 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads. | 10-09-2008 |
| 20080251927 | Electromigration-Resistant Flip-Chip Solder Joints - A semiconductor device contact structure practically eliminating the copper diffusion into the solder as well as the current crowding at the contact with the subsequent electromigration in the solder. A column-like electroplated copper stud ( | 10-16-2008 |
| 20080251928 | Carbonization of metal caps - An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring. | 10-16-2008 |
| 20080258306 | Semiconductor Device and Method for Fabricating the Same - The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers. | 10-23-2008 |
| 20080265424 | SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate. | 10-30-2008 |
| 20080272494 | Semiconductor device - A semiconductor device is provided, including: a first barrier metal film provided by a PVD process in a recess formed in at least one insulating film, and containing at least one metal element belonging to any of the groups 4-A, 5-A, and 6-A; a second barrier metal film continuously provided by at least one of CVD and ALD processes on the first barrier metal film without being opened to atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; a third barrier metal film continuously provided by the PVD process on the second barrier metal film without being opened to the atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; and a first Cu film continuously provided on the third barrier metal film without being opened to the atmosphere and thereafter heated. | 11-06-2008 |
| 20080277797 | INTERCONNECT STRUCTURES - A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure. | 11-13-2008 |
| 20080284033 | Semiconductor device and method for manufacturing semiconductor device - A semiconductor device includes a first metal foil, an insulating sheet mounted on an upper surface of the first metal foil main, at least one second metal foil mounted on the insulating sheet, at least one solder layer mounted on the at least one second metal foil, and at least one semiconductor element mounted on the at least one second metal foil through the at least one solder layer. The at least one semiconductor has a thickness of 50 μm or greater and less than 100 μm. | 11-20-2008 |
| 20080303161 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes: preparing a semiconductor element having a first metal layer made of first metal on a surface thereof, and a metal substrate made of second metal, the metal substrate having a fourth metal layer made of fourth metal on a surface thereof, and mounting the semiconductor element on the surface thereof; providing metal nanopaste between the first metal layer and the fourth metal layer, the metal nanopaste being formed by dispersing fine particles made of third metal with a mean diameter of 100 nm or less into an organic solvent; and heating, or heating and pressurizing the semiconductor element and the metal substrate between which the metal nanopaste is provided, thereby removing the solvent. Further, each of the first, third and fourth metals is made of any metal of gold, silver, platinum, copper, nickel, chromium, iron, lead, and cobalt, an alloy containing at least one of the metals, or a mixture of the metals or the alloys. By the manufacturing method, it is possible to bond the semiconductor element to the metal substrate favorably. | 12-11-2008 |
| 20080315423 | SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a chip including a first face having a contact area, where the chip is attached to the carrier such that the contact area faces away from the carrier, a copper connector configured for attachment to the contact area, and a solder material configured to couple the copper connector to the contact area. | 12-25-2008 |
| 20080315424 | Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 12-25-2008 |
| 20090001591 | REDUCING RESISTIVITY IN METAL INTERCONNECTS BY COMPRESSIVE STRAINING - Techniques for reducing resistivity in metal interconnects by compressive straining are generally described. In one example, an apparatus includes a dielectric substrate, a thin film of metal coupled with the dielectric substrate, and an interconnect metal coupled to the thin film of metal, the thin film of metal having a lattice parameter that is smaller than the lattice parameter of the interconnect metal to compressively strain the interconnect metal. | 01-01-2009 |
| 20090008784 | Power semiconductor substrates with metal contact layer and method of manufacture thereof - A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track, wherein a layer of a metallic material is disposed on the contact area by means of pressure sintering. The associated method comprises the steps of: producing a power semiconductor substrate that includes a planar insulating base, conductor tracks and contact areas; arranging a pasty layer, composed of a metallic material and a solvent, on at least one contact area of the power semiconductor substrate; and applying pressure to the pasty layer. | 01-08-2009 |
| 20090026622 | Semiconductor Device and Method for Manufacturing Same - A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved. | 01-29-2009 |
| 20090026623 | BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF - A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region. | 01-29-2009 |
| 20090026624 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING METAL LINE THEREOF - A method for manufacturing a metal line of a semiconductor device includes forming an interlayer dielectric layer over the whole surface of a semiconductor substrate including a first metal line. A plurality of trenches are formed in trench areas each having a predetermined depth from a surface thereof by selectively removing portions of the interlayer dielectric layer. A first metal film is formed in the plurality of trenches. A first photoresist pattern is formed over the interlayer dielectric layer exposing contact areas and the first metal line. Via holes are formed in the contact areas by etching the interlayer dielectric layer using the first photoresist pattern and the first metal film as masks. A second metal film is formed in the via holes. Accordingly, misalignment of masks caused during formation of the metal line can be restrained, thereby minimizing the defect rate and improving yield. | 01-29-2009 |
| 20090026625 | ADHESION ENHANCEMENT FOR METAL/DIELECTRIC INTERFACE - An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner. | 01-29-2009 |
| 20090039516 | Power semiconductor component with metal contact layer and production method therefor - A power semiconductor component having a basic body and at least one contact area. At least one first thin metallic layer of a first material is arranged on the contact area. A second metallic layer—thicker than the first—of a second material is arranged on the first material by a pressure sintering connection of said material. The associated method has the following steps: producing a plurality of power semiconductor components in a wafer; applying at least one first thin metallic layer on at least one contact area of a respective power semiconductor component; arranging a pasty layer, composed of the second material and a solvent, on at least one of the first metallic layers for each power semiconductor component; pressurizing the pasty layer; and singulating the semiconductor components. | 02-12-2009 |
| 20090051036 | Semiconductor Package Having Buss-Less Substrate - A ball grid array device with an insulating substrate ( | 02-26-2009 |
| 20090072407 | THERMO-COMPRESSION BONDED ELECTRICAL INTERCONNECT STRUCTURE AND METHOD - An electrical structure and method for forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure and a first solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. A second portion of the non-solder metallic core structure is thermo-compression bonded to the second electrically conductive pad. | 03-19-2009 |
| 20090079080 | Semiconductor Device with Multi-Layer Metallization - One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer. | 03-26-2009 |
| 20090085215 | Semiconductor component comprising copper metallizations - A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy. | 04-02-2009 |
| 20090096107 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device, an element forming region and a metal wiring layer are covered with a passivation layer on a semiconductor substrate which is cut out in a rectangular shape. At four corners of the device, the passivation layer is provided with corner non-wiring regions formed directly on the semiconductor substrate. Thus, crack generation on the passivation layer due to heat stress can be suppressed. | 04-16-2009 |
| 20090108455 | INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF - A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material. | 04-30-2009 |
| 20090108456 | Solder-top Enhanced Semiconductor Device and Method for Low Parasitic Impedance Packaging - A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes:
| 04-30-2009 |
| 20090134521 | INTEGRATED CIRCUIT AND MANUFACTURING METHOD OF COPPER GERMANIDE AND COPPER SILICIDE AS COPPER CAPPING LAYER - A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer onto said copper conductive structure by exposing said structure to a GeH | 05-28-2009 |
| 20090160060 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Embodiments relate to a method of manufacturing a semiconductor device having a porous low-k dielectric layer. According to embodiments, a method may include forming an inter metal dielectric (IMD) layer on and/or over a semiconductor substrate, forming copper lines having a stepped structure in the IMD layer, forming a barrier insulating layer on and/or over upper surfaces of the copper lines and the IMD layer, exposing a portion of the upper surface of the IMD layer by photolithography and etching processes, and forming air cavities in the IMD layer using a wet etching process on and/or over the exposed portion of the upper surface of the IMD layer. According to embodiments, a value of the dielectric constant (k) of the IMD layer or the porous low-k dielectric layer may be close to that of a vacuum state. | 06-25-2009 |
| 20090166874 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device and manufacturing method thereof are provided. The semiconductor device can include an interlayer dielectric layer on a substrate, a metal layer on the interlayer dielectric layer, and an impure anti-reflection film on the metal layer. The impure anti-reflection film can be formed through an in situ process. | 07-02-2009 |
| 20090174077 | Method for Structuring a Substrate - A method and intermediate product for structuring a substrate is disclosed. At least one seed layer including a first metal compound is positioned at least partially on the substrate. The seed layer is subjected to a solution comprising ions of a second metal compound. The ions are reduced in the solution by reduction means so that the second metal compound is deposited as mask layer on the seed layer. | 07-09-2009 |
| 20090184425 | Conductive line structure and the method of forming the same - The conductive line structure of a semiconductor device including a base; at least one patterned conductive layer formed over the base; a conductive line formed over the at least one patterned conductive layer; a protection layer that encompasses the top surface and sidewall of the conductive line to prevent undercut generated by etching. The structure further comprises an underlying layer under the conductive line. The underlying layer includes Ni, Cu or Pt. The conductive line includes gold or copper. The at least one patterned conductive layer includes at least Ti/Cu. The protection layer includes electro-less plating Sn, Au, Ag or Ni. | 07-23-2009 |
| 20090189286 | FINE PITCH SOLDER BUMP STRUCTURE WITH BUILT-IN STRESS BUFFER - A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure. In employing the polyimide material as the primary structural component of the vertical chip package interconnect in this particular inventive manner, the inherent stress buffering property of the polyimide material is utilized to full advantage by effectively reducing the high stresses encountered during chip manufacture processing steps, such as chip join, reflow, preconditioning and reliability thermal cycle stressing. | 07-30-2009 |
| 20090212436 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and method for forming the same are provided. The semiconductor structure comprises a semiconductor substrate, a plurality of top metallizations on the semiconductor substrate, a high density plasma layer filling gaps between the top metallizations and having a substantially planar upper surface overlying the top metallizations, and a passivation layer overlying the high density plasma layer. A metal bump can be formed overlying the top metallizations through the passivation layer and HDPCVD layer for subsequent bonding. | 08-27-2009 |
| 20090212437 | SEMICONDUCTOR DEVICE - In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device. | 08-27-2009 |
| 20090218696 | SEMICONDUCTOR DEVICE INCLUDING A PADDING UNIT - A semiconductor device includes bit lines formed over a substrate and a padding unit formed over the bit lines. The padding unit includes stacked padding layers. A lower padding layer is formed between the bit lines and an upper padding layer. The upper layer as a slit formed therein. The lower padding layer prevents damage to the bit lines due to plasma gas entering through the slit. | 09-03-2009 |
| 20090236747 | Semiconductor device and method for fabricating the same - A multilevel interconnect structure in a semiconductor device comprises a first insulating layer ( | 09-24-2009 |
| 20090243111 | SEMICONDUCTOR SUBSTRATE, ELECTRODE FORMING METHOD, AND SOLAR CELL FABRICATING METHOD - The present invention is directed to a semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure constituted of a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least one layer and disposed on the first electrode layer; wherein the upper electrode layer is formed by firing a conductive paste having a total silver content of 75 wt % or more and 95 wt % or less, the content of silver particles having an average particle diameter of 4 μm or greater and 8 μm or smaller with respect to the total silver content in the upper electrode layer being higher than that in the first electrode layer. As a consequence, it is possible to form the electrode, which has the high aspect ratio and hardly suffers an inconvenience such as a break, on the semiconductor substrate by a simple method. | 10-01-2009 |
| 20090243112 | Copper interconnection structure, semiconductor device, and method for forming copper interconnection structure - A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C), hydrogen (element symbol: H) and oxygen (element symbol: O). The interconnection is located on the insulating layer, and the interconnection includes copper (element symbol: Cu). The barrier layer is located between the insulating layer and the interconnection. The barrier layer includes an additional element, carbon (element symbol: C) and hydrogen (element symbol: H). The barrier layer has atomic concentrations of carbon (element symbol: C) and hydrogen (element symbol: H) maximized in a region of a thickness of the barrier layer where the atomic concentration of the additional element is maximized. | 10-01-2009 |
| 20090250821 | CORROSION RESISTANT VIA CONNECTIONS IN SEMICONDUCTOR SUBSTRATES AND METHODS OF MAKING SAME - Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present invention relate to disposing a corrosion resistant metal layer within a recess formed in a semiconductor substrate such that the metal subsequently deposited within the via will adhere to the corrosion resistant metal layer, then backgrinding the bottom surface of the semiconductor substrate to expose the corrosion resistant metal. For example, the metal deposited within the recess may be copper, while the corrosion resistant metal may be a noble metal such as palladium. | 10-08-2009 |
| 20090256263 | STRUCTURE AND METHOD FOR HYBRID TUNGSTEN COPPER METAL CONTACT - The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of the at least one tungsten (W) stud below the upper surface of the interlevel dielectric to provide at least one recessed tungsten (W) stud; forming a first low-k dielectric layer atop the upper surface of the interlevel dielectric layer and the at least one recessed tungsten (W) stud; forming a opening through the first low-k dielectric layer to expose an upper surface of the at least one recessed tungsten stud; and filling the opening with copper (Cu). | 10-15-2009 |
| 20090283913 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes: a copper (Cu) wire having a first region and a second region in which densities of silicon (Si) and oxygen (O) atoms are higher than in the first region; a compound film that is selectively formed on the Cu wire and contains Cu and Si; and a dielectric film formed on a side surface side of the Cu wire. | 11-19-2009 |
| 20090294970 | HIGH FREQUENCY INTERCONNECT PAD STRUCTURE - An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance. | 12-03-2009 |
| 20090294971 | ELECTROLESS NICKEL LEVELING OF LGA PAD SITES FOR HIGH PERFORMANCE ORGANIC LGA - A structure comprises: a substrate; at least one conductor on the substrate; at least one contact pad on the substrate; a mask over the conductor (wherein the mask comprises an opening over the contact pad and wherein the mask comprises a bottom surface contacting the substrate and a top surface opposite the bottom surface); and a contact pad plating layer on the contact pad and within the opening of the mask. The contact pad plating layer comprises a bottom surface contacting the contact pad and a top surface opposite the bottom surface, and the top surface of the contact pad plating layer is coplanar with the top surface of the mask. | 12-03-2009 |
| 20090294972 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film. | 12-03-2009 |
| 20090309226 | Interconnect Structure for Electromigration Enhancement - An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material. | 12-17-2009 |
| 20090309227 | FABRICATION OF INTERCONNECTS IN LOW-K INTERLAYER DIELECTRICS - A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug. | 12-17-2009 |
| 20100038793 | INTERCONNECT STRUCTURES COMPRISING CAPPING LAYERS WITH LOW DIELECTRIC CONSTANTS AND METHODS OF MAKING THE SAME - Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising Si | 02-18-2010 |
| 20100052174 | COPPER PAD FOR COPPER WIRE BONDING - An integrated circuit package comprising an integrated circuit that includes transistors coupled to copper interconnect structures. The integrated circuit package also comprises copper pads located on the integrated circuit and directly contacting uppermost ones of the copper interconnect structures. Each of copper pads has a thickness of at least about 2 microns. The integrated circuit package further comprises copper wires pressure-welded directly to the copper pads. | 03-04-2010 |
| 20100052175 | REDUCING LEAKAGE AND DIELECTRIC BREAKDOWN IN DIELECTRIC MATERIALS OF METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY FORMING RECESSES - By recessing metal lines and/or the dielectric material of a metallization layer of sophisticated semiconductor devices, the time to dielectric breakdown may be increased due to reducing electrical fields and diffusion paths at the top of the metal lines. | 03-04-2010 |
| 20100090344 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion. | 04-15-2010 |
| 20100096756 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity. | 04-22-2010 |
| 20100109161 | REDUCING METAL VOIDS IN A METALLIZATION LAYER STACK OF A SEMICONDUCTOR DEVICE BY PROVIDING A DIELECTRIC BARRIER LAYER - Metallization systems on the basis of copper and low-k dielectric materials may be efficiently formed by providing an additional dielectric material of enhanced surface conditions after the patterning of the low-k dielectric material. Consequently, defects such as isolated copper voids and the like may be reduced without significantly affecting overall performance of the metallization system. | 05-06-2010 |
| 20100133693 | Semiconductor Package Leads Having Grooved Contact Areas - A packaged semiconductor device ( | 06-03-2010 |
| 20100133694 | METAL INTERCONNECT AND IC CHIP INCLUDING METAL INTERCONNECT - A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect. | 06-03-2010 |
| 20100140803 | SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT, MULTI-LAYER PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARD - A method of manufacturing a semiconductor device having a transition layer, including (a) forming a wiring and a die pad on a wafer, (b) forming a thin film layer on an entire surface of the wafer obtained in the step (a), (c) forming a resist layer on the thin film layer, and forming a thickening layer on a resist layer unformed section, (d) peeling the resist layer, (e) removing the thin film layer by etching, and (f) dividing the wafer to thereby form semiconductor devices. | 06-10-2010 |
| 20100148368 | SEMICONDUCTOR DEVICE - A semiconductor device where an outside connection terminal of a semiconductor element and an electrode of a wiring board are connected to each other via a conductive adhesive, the conductive adhesive includes a first conductive adhesive; and a second conductive adhesive covering the first conductive adhesive; wherein the first conductive adhesive contains a conductive filler including silver (Ag); and the second conductive adhesive contains a conductive filler including a metal selected from a group consisting of tin (Sn), zinc (Zn), cobalt (Co), iron (Fe), palladium (Pd), and platinum (Pt). | 06-17-2010 |
| 20100164113 | METHOD FOR FORMING COPPER WIRING IN SEMICONDUCTOR DEVICE - A method for forming copper wirings in a semiconductor device may include depositing a lower insulating film over a semiconductor substrate; forming vias in the lower insulating film; depositing tungsten over the entire surface of upper portion of the lower insulating film so that the vias are gap-filled with the tungsten; forming tungsten plugs by performing a tungsten chemical mechanical polishing process to remove excess tungsten deposited over the upper portion of the lower insulating film; removing the tungsten remaining over the upper portion of the lower insulating film by performing a tungsten etchback process; depositing an upper insulating film over the upper portion of the lower insulating film; exposing upper portions of the tungsten plugs by forming trenches on the upper insulating film; depositing copper over the entire surface of the upper insulating film so that the trenches are gap-filled with the copper; and planarizing the copper over the upper portion of the trenches. | 07-01-2010 |
| 20100181675 | SEMICONDUCTOR PACKAGE WITH WEDGE BONDED CHIP - A semiconductor package with wedge bonded chip. One embodiment provides a semiconductor chip, a wire bond and a metal element. The chip includes a bond pad with a copper layer. The wire bond is wedge bonded to the bond pad and ball bonded to the metal element. | 07-22-2010 |
| 20100213612 | THROUGH-SILICON VIA FORMED WITH A POST PASSIVATION INTERCONNECT STRUCTURE - An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced apart from the TSV, and an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV. | 08-26-2010 |
| 20100213613 | ARRANGEMENT FOR ELECTRICALLY CONNECTING SEMICONDUCTOR CIRCUIT ARRANGEMENTS TO AN EXTERNAL CONTACT DEVICE AND METHOD FOR PRODUCING THE SAME - An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability. | 08-26-2010 |
| 20100213614 | Methods for Passivating Metallic Interconnects - One or more embodiments of the present invention relates to a method for passivating metallic interconnects, said method including: forming a metallic conductor embedded in at least one surrounding dielectric layer, said metallic conductor including a metal or alloy chosen from a group consisting of Cu, Ag, and alloys including one or more of these metals, said metallic conductor and said at least one surrounding dielectric layer having top surfaces; and forming a capping passivation film directly on the top surface of the metallic conductor, but not over the top surface of the at least one surrounding dielectric layer, wherein said capping passivation film including one or more materials selected from the group consisting of copper sulfide, silver sulfide, copper selenide, silver selenide, copper telluride, and silver telluride, wherein the copper sulfide refers to CuS | 08-26-2010 |
| 20100237505 | METAL-METAL BONDING OF COMPLIANT INTERCONNECT - Embodiments of the invention provide a first component with a compliant interconnect bonded to a second component with a land pad by a metal to metal bond. In some embodiments, the first component may be a microprocessor die and the second component a package substrate. | 09-23-2010 |
| 20100244266 | METALLIC BONDING STRUCTURE FOR COPPER AND SOLDER - The present invention discloses a metallic bonding structure for copper and solder, which applies to connect at least one electronic element. The metallic bonding structure comprises at least one copper-based member and at least one zinc bonding member. The copper-based members are arranged on the electronic element through at least one solder member. The zinc bonding members are arranged between the copper-based members and the solder members. The solder members are tin-based solder bumps. | 09-30-2010 |
| 20100244267 | INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND RELATED METHOD OF MANUFACTURE - A semiconductor device having a device substrate is provided. The semiconductor device comprises an electrically-conductive pad formed overlying the device substrate, an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity, the electrically-conductive platform having a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion, and a cushioning material disposed in the cavity. | 09-30-2010 |
| 20100252930 | Method for Improving Performance of Etch Stop Layer - A method of forming an interconnect structure includes providing a dielectric layer; forming a metal line in the dielectric layer; and forming a composite etch stop layer (ESL), which includes forming a lower ESL over the metal line and the dielectric layer; and forming an upper ESL over the lower ESL. The upper ESL and the lower ESL have different compositions. The step of forming the lower ESL and the step of forming the upper ESL are in-situ performed. | 10-07-2010 |
| 20100276806 | Plastic package and method of fabricating the same - A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals. | 11-04-2010 |
| 20100314768 | INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING - An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure. | 12-16-2010 |
| 20100314769 | FOR REDUCING ELECTROMIGRATION EFFECT IN AN INTEGRATED CIRCUIT - An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterised in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region. | 12-16-2010 |
| 20100327450 | SEMICONDUCTOR DEVICE BONDING WIRE AND WIRE BONDING METHOD - It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 μm in thickness. | 12-30-2010 |
| 20110006431 | METHOD FOR ALIGNING AND BONDING ELEMENTS AND A DEVICE COMPRISING ALIGNED AND BONDED ELEMENTS - The present invention is related to a method for aligning and bonding a first element ( | 01-13-2011 |
| 20110018135 | METHOD OF ELECTRICALLY CONNECTING A WIRE TO A PAD OF AN INTEGRATED CIRCUIT CHIP AND ELECTRONIC DEVICE - A wire is electrically connected to an electrical bonding pad of an integrated circuit chip and electronic device through an intermediate electrical interconnect block that is interposed between the electrical bonding pad and one end of the electrical lead wire. | 01-27-2011 |
| 20110024910 | METALLURGY FOR COPPER PLATED WAFERS - Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer. An electrically insulating protective layer overlies the first aluminum metallization layer and the top wafer fabrication passivation layer. The protective layer is preferably formed from an organic material and includes a plurality of contact openings. Underbump metallization stacks are formed in the contact openings. Each underbump metallization stack is electrically connected to the first aluminum metallization layer through its associated contact opening in the protective layer. Solder bumps are preferably then adhered to the underbump metallization stacks. | 02-03-2011 |
| 20110042815 | SEMICONDUCTOR DEVICE AND ON-VEHICLE AC GENERATOR - An object of the present invention is to provide, at low costs, an environmental friendly bonding material for a semiconductor, having sustained bonding reliability even when used at a temperature as high as 200° C. or higher for a long period of time, the semiconductor device having a semiconductor element, a supporting electrode body bonded to a first face of the semiconductor element via a first bonding member, and a lead electrode body bonded to a second face of the semiconductor element supported by the supporting electrode body via a second bonding member, the semiconductor device having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu | 02-24-2011 |
| 20110074034 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE - A semiconductor component and methods for manufacturing the semiconductor component that includes a double exposure of a layer of photoresist or the use of multiple layers of photoresist. A metallization structure is formed on a layer of electrically conductive material that is disposed on a substrate and a layer of photoresist is formed on the metallization structure. The layer of photoresist is exposed to light and developed to remove a portion of the photoresist layer, thereby forming an opening. Then, a larger portion of the photoresist layer is exposed to light and an electrically conductive interconnect is formed in the opening. The larger portion of the photoresist layer that was exposed to light is developed to expose edges of the electrically conductive interconnect and portions of the metallization structure. A protection layer is formed on the top and edges of the electrically conductive interconnect and on the exposed portions of the metallization structure. | 03-31-2011 |
| 20110079909 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A generation of a void in a recessed section is inhibited. A method for manufacturing a semiconductor device includes: an operation of forming recessed sections in an insulating film, which is formed on a semiconductor substrate; an operation of forming a seed film in the recessed section; an operation of forming a cover metal film in the recessed section; an operation of selectively removing the cover metal film to expose the seed film over the bottom section of the recessed section; and an operation to carrying out a growth of a plated film to fill the recessed section by utilizing the seed film exposed in the bottom section of the recessed section as a seed. | 04-07-2011 |
| 20110089566 | WIRE BONDING STRUCTURE AND METHOD THAT ELIMINATES SPECIAL WIRE BONDABLE FINISH AND REDUCES BONDING PITCH ON SUBSTRATES - A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer. | 04-21-2011 |
| 20110095431 | THERMO-COMPRESSION BONDED ELECTRICAL INTERCONNECT STRUCTURE - An electrical structure and method for forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure and a first solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. A second portion of the non-solder metallic core structure is thermo-compression bonded to the second electrically conductive pad. | 04-28-2011 |
| 20110095432 | ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, METHOD OF MAKING THE SAME AND METHOD OF MOUNTING THE SAME, CIRCUIT BOARD AND ELECTRONIC INSTRUMENT - A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes on a wafer; a step of providing a resin later as a stress relieving layer on the wafer, avoiding the electrodes; a step of forming a chromium layer as wiring from electrodes over the resin layer; and step of forming solder balls as external electrodes on the chromium layer over the resin layer; and a step of cutting the wafer into individual semiconductor chips; in the steps of forming the chromium layer and solder balls, metal thin film fabrication technology is used during the wafer process. | 04-28-2011 |
| 20110115092 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - There is provided a semiconductor device and a manufacturing method therefor, the semiconductor device requiring flip-chip mounting of a fine pitch electrode, wherein the fine electrode is easily manufactured, resin sealing is not required, and reliability can be improved. In the semiconductor device, one or more LSI chips ( | 05-19-2011 |
| 20110147940 | ELECTROLESS CU PLATING FOR ENHANCED SELF-FORMING BARRIER LAYERS - Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer. | 06-23-2011 |
| 20110156259 | METAL-TO-CONTACT OVERLAY STRUCTURES AND METHODS OF MANUFACTURING THE SAME - The present invention provides a semiconductor device with a metal-to-contact overlay structure. The semiconductor device includes a substrate, a dielectric layer on the substrate, a contact coupled to the substrate in the dielectric layer, a first conductive region on the contact in the dielectric layer, a dielectric sidewall on the contact in the dielectric layer, the dielectric sidewall surrounding the first conductive region, and a second conductive region on the first conductive region on the dielectric layer. | 06-30-2011 |
| 20110169166 | SEMICONDUCTOR DEVICE SEALED IN A RESIN SECTION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same. | 07-14-2011 |
| 20110193232 | CONDUCTIVE PILLAR STRUCTURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - A conductive pillar structure for a die includes a passivation layer having a metal contact opening over a substrate. A bond pad has a first portion inside the metal contact opening and a second portion overlying the passivation layer. The second portion of the bond pad has a first width. A buffer layer over the bond pad has a pillar contact opening with a second width to expose a portion of the bond pad. A conductive pillar has a first portion inside the pillar contact opening and a second portion over the buffer layer. The second portion of the conductive pillar has a third width. A ratio of the second width to the first width is between about 0.35 and about 0.65. A ratio of the second width to the third width is between about 0.35 and about 0.65. | 08-11-2011 |
| 20110215476 | METHOD FOR FABRICATING CIRCUIT COMPONENT - A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar. | 09-08-2011 |
| 20110233783 | SUBSTRATE ARRANGEMENT - In an embodiment, a substrate arrangement is provided. The substrate arrangement may include a semiconductor substrate including a first contact portion and a second contact portion on a first surface of the semiconductor substrate, wherein the semiconductor substrate is arranged such that the first contact portion and the second contact portion face each other. The substrate arrangement may further include an electrical connector configured to connect the first contact portion and the second contact portion. | 09-29-2011 |
| 20110260324 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE - A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers. | 10-27-2011 |
| 20110291281 | PARTIAL AIR GAP FORMATION FOR PROVIDING INTERCONNECT ISOLATION IN INTEGRATED CIRCUITS - Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap. | 12-01-2011 |
| 20110298135 | INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF - A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material. | 12-08-2011 |
| 20110304049 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - To suppress peeling of an Au pad for external coupling provided in a rewiring containing Cu as a main component. | 12-15-2011 |
| 20110309511 | METHOD FOR PRODUCING LOW-k FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - Hydrophobicity of a low dielectric constant film comprising a porous silica film is improved by applying a raw material for forming a porous silica film onto a substrate, and performing vapor-phase transport treatment to expose the substrate to an atmosphere of organic amine vapor to which no water is added. Simultaneously, reduction in a dielectric constant, reduction in leakage current, and improvement in mechanical strength are attained by controlling a pore diameter in a predetermined range. | 12-22-2011 |
| 20120013011 | Conductive Lines and Pads and Method of Manufacturing Thereof - A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer. | 01-19-2012 |
| 20120025383 | INTEGRATED CIRCUIT STRUCTURE INCORPORATING A CONDUCTOR LAYER WITH BOTH TOP SURFACE AND SIDEWALL PASSIVATION AND A METHOD OF FORMING THE INTEGRATED CIRCUIT STRUCTURE - Disclosed are embodiments of a structure having a metal layer with top surface and sidewall passivation and a method of forming the structure. In one embodiment, a metal layer is electroplated onto a portion of a seed layer at the bottom of a trench. Then, the sidewalls of the metal layer are exposed and, for passivation, a second metal layer is electroplated onto the top surface and sidewalls of the metal layer. In another embodiment, a trench is formed in a dielectric layer. A seed layer is formed over the dielectric layer, lining the trench. A metal layer is electroplated onto the portion of the seed layer within the trench and a second metal layer is electroplated onto the top surface of the metal layer. Thus, in this case, passivation of the top surface and sidewalls of the metal layer is provided by the second metal layer and the dielectric layer, respectively. | 02-02-2012 |
| 20120025384 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 02-02-2012 |
| 20120032333 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film, thereby forming a first interconnect. Then, a protective film is formed on the first insulating film and the first interconnect, and the surface of the protective film is exposed to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film. | 02-09-2012 |
| 20120080795 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer. | 04-05-2012 |
| 20120080796 | DEVICE - According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a concave portion, and a first graphene sheet on an inner surface of the concave portion. | 04-05-2012 |
| 20120080797 | METAL WIRING STRUCTURES FOR UNIFORM CURRENT DENSITY IN C4 BALLS - In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The areal density of the cross-sectional area in the plurality of metal vias is higher at the center portion of the metal pad than at the peripheral portion of the planar portion of the metal pad. | 04-05-2012 |
| 20120091590 | Electroless Deposition of Platinum on Copper - Embodiments of the current invention describe a method of plating platinum selectively on a copper film using a self-initiated electroless process. In particular, platinum films are plated onto very thin copper films having a thickness of less than 300 angstroms. The electroless plating solution and the resulting structure are also described. This process has applications in the semiconductor processing of logic devices, memory devices, and photovoltaic devices. | 04-19-2012 |
| 20120104616 | METHOD FOR DEPOSITING A THIN FILM ELECTRODE AND THIN FILM STACK - A method for depositing at least one thin-film electrode onto a transparent conductive oxide film is provided. At first, the transparent conductive oxide film is deposited onto a substrate to be processed. Then, the substrate and the transparent conductive oxide film are subjected to a processing environment containing a processing gas acting as a donor material or an acceptor material with respect to the transparent conductive oxide film. The at least one thin-film electrode is deposited onto at least portions of the transparent conductive oxide film. A partial pressure of the processing gas acting as the donor material or the acceptor material with respect to the transparent conductive oxide film is varied while depositing the at least one thin-film electrode onto at least portions of the transparent conductive oxide film. Thus, a modified transparent conductive oxide film having reduced interface resistance and bulk resistance can be obtained. | 05-03-2012 |
| 20120139116 | BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND METHODS OF ASSEMBLING SAME - A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure. | 06-07-2012 |
| 20120139117 | Dense Seed Layer and Method of Formation - A semiconductor device includes a workpiece and a first material layer disposed over the workpiece. The first material layer has a first number of atoms at a surface. A seed layer is disposed over the first material layer. The seed layer includes a chemisorbed monolayer of a second number of atoms at the surface having a surface coverage of at least 0.5 such that the ratio of the number of first atoms at the surface to the number of second atoms at the surface is no more than 2:1. The second atoms of the seed layer include oxygen or nitrogen. | 06-07-2012 |
| 20120146226 | INTEGRATED CIRCUIT CHIP AND FABRICATION METHOD - An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar. | 06-14-2012 |
| 20120153484 | METHODS FOR DIRECTLY BONDING TOGETHER SEMICONDUCTOR STRUCTURES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS - Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods. | 06-21-2012 |
| 20120153485 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A device may includes a first conductive film, a first insulating film, a second conductive film, a third conductive film, and a fourth conductive film. The first conductive film includes copper. The first insulating film is disposed over the first conductive film. The first insulating film has a first contact hole. The contact hole reaches a first surface of the first conductive film. The second conductive film includes aluminum. The second conductive film is disposed in the first contact hole. The third conductive film includes titanium nitride. The third conductive film is disposed in the contact hole. The third conductive film covers a part of the first surface of the first conductive film. The fourth conductive film is free of titanium nitride. The fourth conductive film is disposed between the second and third conductive films. | 06-21-2012 |
| 20120153486 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. In the semiconductor device, silver arranged on a semiconductor element and silver arranged on a base are bonded. No void is present or a small void, if any, is present at an interface between the semiconductor element and the silver arranged on the semiconductor element, no void is present or a small void, if any, is present at an interface between the base and the silver arranged on the base, and one or more silver abnormal growth grains and one or more voids are present in a bonded interface between the silver arranged on the semiconductor element and the silver arranged on the base. | 06-21-2012 |
| 20120168950 | DIE STRUCTURE, MANUFACTURING METHOD AND SUBSTRATE THEREOF - A die structure, a manufacturing method and a substrate, wherein the die structure is constituted by a chip on wafer (COW) and the substrate, and the substrate is formed by stacking and then cutting a plurality of thermal and electrical conductive poles and a plurality of insulating material layers. Moreover, the fabricating of the die structure comprises a plurality of COWs carried on a carrier board is bonded on the substrate, the plurality of COWs are in contact with the plurality of thermal and electrical conductive poles on the substrate, and then the carrier board is removed. After that, a phosphor plate is adhered on the plurality of COWs so as to form a stacked structure. Thereafter, the stacked structure is cut, thus forming a plurality of die structures having at least one COW. | 07-05-2012 |
| 20120168951 | PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME - Provided are a printed circuit board (PCB) and a semiconductor package including the same. The PCB includes a core layer having a stacked structure including at least a first layer made of a first material that has a first coefficient of thermal expansion (CTE) and a second layer made of a second material that has a second CTE different from the first CTE, an upper wiring layer disposed on a first surface of the core layer, and a lower wiring layer disposed on a second surface of the core layer opposite the first surface. | 07-05-2012 |
| 20120168952 | SEMICONDUCTOR DEVICE HAVING A COPPER PLUG - Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer. | 07-05-2012 |
| 20120168953 | STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME - A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist. | 07-05-2012 |
| 20120199977 | SEMICONDUCTOR DEVICE - To prevent generation of cracks in an insulating film provided under a bonding pad, a semiconductor device includes a three-layered bonding pad, and the three-layered bonding pad includes a first metal film, a second metal film, and a third metal film, in which the second metal film has a Young's modulus higher than a Young's modulus of the first metal film and a Young's modulus of the third metal film. | 08-09-2012 |
| 20120205809 | DEVICES CONTAINING SILVER COMPOSITIONS DEPOSITED BY MICRO-DEPOSITION DIRECT WRITING SILVER CONDUCTOR LINES - Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device. | 08-16-2012 |
| 20120228774 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A barrier insulating film is constituted from a first SiCN film formed with a tetramethylsilane gas flow rate lower than usual, a second SiCN film formed over the first SiCN film and formed with a usual tetramethylsilane gas flow rate, and a SiCO film formed over the second SiCN film. | 09-13-2012 |
| 20120235302 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor manufacturing method includes: forming a seed film including a first metal over a bottom surface and a side wall of an opening portion formed over interlayer insulating films and a field portion located over the interlayer insulating film except the opening portion, forming a resist over the seed film and filling the opening portion with the resist, removing part of the resist, exposing the seed film formed over the upper portion of the side walls of the opening portion and the field portion, forming a cover film including a second metal, whose resistivity is higher than that of the first metal, over the seed film located over the upper portion of the side wall of the opening portion and the field portion, exposing the seed film by removing the resist, and forming a plating film including the first metal over the exposed seed film. | 09-20-2012 |
| 20120248614 | METHODS FOR FORMING A SEMICONDUCTOR STRUCTURE AND RELATED STRUCTURES - Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over a bond pad, forming an opening within the dielectric material to expose the bond pad, curing the dielectric material to form a surface of the dielectric material having a steep curvilinear profile, and forming a nickel material over the at least one bond pad. The dielectric material having a steep curvilinear profile may be formed by altering at least one of a curing process of the dielectric material and a thickness of the dielectric material. The dielectric material may be used to form a relatively thick Ni material on bond pads smaller than about 50 μm. Semiconductor structures formed by such methods are also disclosed. | 10-04-2012 |
| 20120273954 | SEMICONDUCTOR DEVICE WITH PROTECTIVE MATERIAL AND METHOD FOR ENCAPSULATING - A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds. | 11-01-2012 |
| 20120273955 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor. | 11-01-2012 |
| 20120273956 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-01-2012 |
| 20120299187 | Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products - Embodiments of an aluminum pad thinning in bond pad for fine pitch ultra-thick aluminum pad structures are provided herein. Embodiments include a conductive structure formed on a substrate. A first passivation layer is formed over the substrate and the conductive structure, the first passivation layer having an opening formed over the conductive structure. An ultra-thick conductive structure having a thinned trench region formed over the opening of the first passivation layer. The ultra-thick conductive structure is in contact with the conductive structure. A second passivation layer formed over the first passivation region and the ultra-thick conductive structure. The second passivation layer having an opening formed over the thinned trench region of the ultra-thick conductive structure. | 11-29-2012 |
| 20120306085 | PROTECTIVE LAYER FOR PROTECTING TSV TIPS DURING THERMO-COMPRESSIVE BONDING - A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips. | 12-06-2012 |
| 20120306086 | SEMICONDUCTOR DEVICE AND WIRING SUBSTRATE - A semiconductor device according to an embodiment includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate, and a semiconductor element mounted on the wiring layer. In this semiconductor device, the wiring layer includes a first copper-containing material containing copper and a metal having the thermal expansion coefficient smaller than that of copper and the thermal expansion coefficient of the first copper-containing material is smaller than that of copper. | 12-06-2012 |
| 20120313246 | SEMICONDUCTOR APPARATUS - The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer. | 12-13-2012 |
| 20130001787 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate; a first metal ring surrounding the semiconductor element; an insulation film formed to cover the semiconductor element and having the first metal ring disposed therein; and a groove formed in the insulation film; wherein: the first metal ring is formed by laminating multiple metal layers in such a manner that respective outside lateral faces of the multiple metal layers are flush with each other, or that outside lateral face of each of the multiple metal layers which is positioned above an underlying metal layer is positioned more inside than outside lateral face of the underlying metal layer; and the groove has first bottom which is disposed inside the first metal ring and extending to a depth of upper surface of an uppermost metal layer of the first metal ring. | 01-03-2013 |
| 20130001788 | Semiconductor Constructions - Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component. | 01-03-2013 |
| 20130009311 | SEMICONDUCTOR CARRIER, PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a first encapsulant having tapered through holes each having a wide top and a narrow bottom; tapered electrical contacts disposed in the tapered through holes; circuits disposed on a top surface of the first encapsulant and each having one end connecting one of the electrical contacts and the other end having a bonding pad disposed thereon such that the bonding pads are circumferentially arranged to define a die attach area on the top surface of the first encapsulant. As such, a semiconductor chip can be disposed on the top surface of the first encapsulant in the die attach area and electrically connected to the bonding pads through conductive elements, and further a second encapsulant encapsulates the semiconductor chip, the conductive elements, the circuits and the first encapsulant so as to prevent falling off of the electrical contacts and reduce the length of the conductive elements. | 01-10-2013 |
| 20130009312 | INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING - An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure. | 01-10-2013 |
| 20130020709 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a carrier having a plurality bonding pads disposed on a surface thereof, a packaging layer formed on the surface of the carrier and having a plurality of openings corresponding to the bonding pads, a conductive material filled in the openings and electrically connected to the bonding pads, and an electronic component installed on the packaging layer and having a plurality of conductive pillars correspondingly received in the openings and electrically connected to the conductive material. The formation of the openings in the packaging layer can control the position and size of the conductive material to enable the overall height of the conductive structure to be level and to keep the electronic component from tilting. | 01-24-2013 |
| 20130020710 | SEMICONDUCTOR SUBSTRATE, PACKAGE AND DEVICE AND MANUFACTURING METHODS THEREOF - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer. | 01-24-2013 |
| 20130026634 | Hybrid Interconnect Technology - In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials. | 01-31-2013 |
| 20130026635 | Hybrid Copper Interconnect Structure and Method of Fabricating Same - A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. The copper regions containing the different impurities levels can be achieved utilizing a combination of physical vapor deposition of a copper region having a low impurity level (i.e., less than 20 ppm) and copper reflow, with electroplating another copper region having a high impurity level (i.e., 100 ppm or greater). | 01-31-2013 |
| 20130026636 | LAMINATED AND SINTERED CERAMIC CIRCUIT BOARD, AND SEMICONDUCTOR PACKAGE INCLUDING THE CIRCUIT BOARD - A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased. | 01-31-2013 |
| 20130043594 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, between the mounting substrate and the semiconductor chip, there is a joint support layer including a metal or its alloy selected from the group of Cu, Al, Ag, Ni, Cr, Zr and Ti and a melt layer laminated across the joint support layer, and formed of a metal selected from the group of Sn, Zn and In or of an alloy of at least two metals selected from the same metals. The process of joining the mounting substrate and the semiconductor chip includes intervening a joining layer which is formed, at least for its outermost layer, by the melt layer, maintaining the temperature to be higher than the melting point of the melt layer, then forming an alloy layer which has a higher melting point than the melt layer by liquid phase diffusion. | 02-21-2013 |
| 20130082386 | INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE - An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact. | 04-04-2013 |
| 20130105979 | Package on Package Devices and Methods of Packaging Semiconductor Dies | 05-02-2013 |
| 20130113107 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a lower face of the substrate facing the active layer; a copper-plated layer provided on a lower face of the first nickel-plated layer; and a second nickel-plated layer provided on a lower face of the copper-plated layer. | 05-09-2013 |
| 20130119548 | METHOD TO FABRICATE HIGH PERFORMANCE CARBON NANOTUBE TRANSISTOR INTEGRATED CIRCUITS BY THREE-DIMENSIONAL INTEGRATION TECHNOLOGY - Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided. | 05-16-2013 |
| 20130147047 | Integrated Circuit and Method of Forming an Integrated Circuit - An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7. | 06-13-2013 |
| 20130154099 | PAD OVER INTERCONNECT PAD STRUCTURE DESIGN - A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit. The maximum pattern density check is performed at least under some circumstances if a modulus of the primary metallization material is less than a modulus of a surrounding dielectric material. The maximum pattern density check verifies that the pattern density within the underlying portion is below a maximum pattern density that depends on the thickness of the access pad. A maximum metal width check may also be performed in this portion. | 06-20-2013 |
| 20130175693 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, at least one transistor integrated with the substrate, an interlayer insulating layer on the substrate, a conductive line extending within the interlayer insulating layer and electrically connected to the transistor, and at least one capping layer containing carbon in an amount of about 2 to about 7.5 atomic percent. The capping layer may cover the interlayer insulating layer in which the conductive line extends. | 07-11-2013 |
| 20130181351 | Semiconductor Device Package with Slanting Structures - A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through hole through the substrate, wherein the conductive through hole electrically couples the via contact pad and the terminal pad on the substrate; a die having bonding pads thereon, wherein the die is formed on the top surface of the substrate; a slanting structure formed adjacent to at least one side of the die for carrying conductive traces; and a conductive trace formed on upper surface of the slanting structure to offer path between the bonding pads and the via contact pad. | 07-18-2013 |
| 20130187277 | CRACK STOPPER ON UNDER-BUMP METALLIZATION LAYER - A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings. | 07-25-2013 |
| 20130193580 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises a mounting step of mounting a semiconductor element having an Au—Sn layer on a substrate, wherein the mounting step includes a paste supplying step of supplying an Ag paste having an Ag nanoparticle onto the substrate, a device mounting step of mounting a side of the Au—Sn layer of the semiconductor element on the Ag paste, and a bonding step of alloying the Au—Sn layer and the Ag paste to bond the semiconductor element to the substrate, wherein the Au—Sn layer has a content rate of Au of 50 at % to 85 at %. | 08-01-2013 |
| 20130207269 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a≦0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face. | 08-15-2013 |
| 20130214418 | Semiconductor Device Package with Slanting Structures - A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through hole through the substrate, wherein the conductive through hole electrically couples the via contact pad and the terminal pad on the substrate; a die having bonding pads thereon, wherein the die is formed on the top surface of the substrate; a slanting structure formed adjacent to at least one side of the die for carrying conductive traces; and a conductive trace formed on upper surface of the slanting structure to offer path between the bonding pads and the via contact pad. | 08-22-2013 |
| 20130221530 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction. | 08-29-2013 |
| 20130228929 | Protection Layers for Conductive Pads and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line. | 09-05-2013 |
| 20130228930 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 μm to 10 μm from the edge of the concave to the bottom of the concave. | 09-05-2013 |
| 20130241069 | SEMICONDUCTOR BONDING STRUCTURE BODY AND MANUFACTURING METHOD OF SEMICONDUCTOR BONDING STRUCTURE BODY - A bonding structure body in which a semiconductor element and an electrode are bonded via a solder material, wherein a part that allows bonding has a first intermetallic compound layer that has been formed on the electrode side, a second intermetallic compound layer that has been formed on the semiconductor element side, and a third layer that is constituted by a phase containing Sn and a sticks-like intermetallic compound part, which is sandwiched between the two layers of the first intermetallic compound layer and the second intermetallic compound layer, and the sticks-like intermetallic compound part is interlayer-bonded to both of the first intermetallic compound layer and the second intermetallic compound layer. | 09-19-2013 |
| 20130249098 | PROTECTIVE LAYER FOR PROTECTING TSV TIPS DURING THERMO-COMPRESSIVE BONDING - A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips. | 09-26-2013 |
| 20130256894 | Porous Metallic Film as Die Attach and Interconnect - One exemplary disclosed embodiment comprises a sintered porous metallic film as a die attach mechanically connecting a backside of a semiconductor die to a substrate of a package. Another exemplary disclosed embodiment comprises a sintered porous metallic film as an electrical connection between an electrode on an active surface of a semiconductor die and a substrate of a package. The porous metallic film may be integrated as a prefabricated film or may be created at the wafer or substrate level. By providing a conformal bond through the presence of pores in the metallic film, the sintered connection can provide a reliable mechanical connection with a lower effective elastic modulus. Thermal expansion stresses between die and substrate are thereby accommodated for robustness against thermal cycling, which is of particular relevance for high performance power modules and automotive applications. | 10-03-2013 |
| 20130264712 | WIREBONDED SEMICONDUCTOR PACKAGE - A semiconductor package including a substrate, a semiconductor device, a protection layer, a bonding wire, and a molding compound is provided. The substrate has a contact pad and a solder mask, and the contact pad is exposed from the solder mask. The semiconductor device is disposed on the substrate. The protection layer is disposed on the contact pad. The bonding wire connects the semiconductor device to the contact pad. An end of the bonding wire penetrates the protection layer and bonds with a portion of a surface of the contact pad to form a bonding region. The protection layer covers an entire surface of the contact pad except the bonding region. The molding compound covers the semiconductor device, the contact pad, and the bonding wire. | 10-10-2013 |
| 20130277845 | STRUCTURE OF BACKSIDE COPPER METALLIZATION FOR SEMICONDUCTOR DEVICES AND A FABRICATION METHOD THEREOF - An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, in which the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, at least one thermal expansion buffer layer, a backside metal layer, and at least one oxidation resistant layer, in which the backside metal seed layer is formed of Pd, and the thermal expansion coefficient of the thermal expansion buffer layer is in the range between the thermal expansion coefficients of the backside metal seed layer and of the backside metal layer. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations. | 10-24-2013 |
| 20130285248 | Package Structure and Substrate Bonding Method - A substrate bonding method comprises the following steps. Firstly, a first substrate and a second substrate are provided, wherein a surface of the first substrate is covered by a first Ag layer and a surface of the second substrate is covered by a second Ag layer and a metallic layer from bottom to top, wherein the metallic layer comprises a first Sn layer. Secondly, a bonding process is performed by aligning the first and second substrates followed by bringing the metallic layer into contact with the first Ag layer followed by applying a load while heating to a predetermined temperature in order to form Ag | 10-31-2013 |
| 20130307156 | Reliable Area Joints for Power Semiconductors - A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization. | 11-21-2013 |
| 20130307157 | SEMICONDUCTOR DEVICE PACKAGES WITH SOLDER JOINT ENHANCEMENT ELEMENT AND RELATED METHODS - Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements. | 11-21-2013 |
| 20130320545 | HYBRID COPPER INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME - A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. | 12-05-2013 |
| 20130328200 | DIRECT BONDED COPPER SUBSTRATE AND POWER SEMICONDUCTOR MODULE - Disclosed are a DBC substrate and a power semiconductor module having improved thermal reliability by directly forming a via in a substrate of a semiconductor device used mainly as a power device such as a silicon device, a silicon carbide (SiC) device, and a gallium nitride (GaN) device. The power semiconductor module includes: a DBC substrate including a ceramic base material defining a via, a lower copper layer connected to a bottom surface of the ceramic base material, and an upper copper layer connected to a top surface of the ceramic base material; a power semiconductor device stacked on the upper copper layer of the DBC substrate; and a heat dissipating device connected to the lower copper layer of the DBC substrate, and dissipating heat, generated by the operation of the power semiconductor device, through the via. | 12-12-2013 |
| 20130328201 | RELIABLE INTERCONNECT FOR SEMICONDUCTOR DEVICE - Semiconductor devices and methods of making thereof are disclosed. The semiconductor device includes a substrate prepared with a first dielectric layer formed thereon. The dielectric layer includes at least first, second and third contact regions. A second dielectric layer is disposed over the first dielectric layer. The device also includes at least first, second and third via contacts disposed in the second dielectric layer. The via contacts are coupled to the respective underlying contact regions and the via contacts do not extend beyond the underlying contact regions. | 12-12-2013 |
| 20140015140 | POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE - A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %. | 01-16-2014 |
| 20140021618 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view. | 01-23-2014 |
| 20140027914 | PROTECTION OF UNDER-LAYER CONDUCTIVE PATHWAY - Systems and methods are presented for preventing removal of material comprising a metal gate during removal of a mask layer in a semiconductor structure. Upon exposure of the metal line during formation of a via opening the exposed portion of the metal line undergoes chemical modification to form a passivation layer. The passivation layer is subsequently covered by an etch selectivity layer, wherein the etch selectivity layer prevents removal of at least one of a portion of the metal line or the passivation layer during removal of a hard mask layer comprising the semiconductor structure. In an alternate approach, the metal line is formed with a capping layer which, following exposure by a via opening formed in the semiconductor structure, is chemically modified to form a layer having etch selectivity to acts as a protective layer during removal of a hard mask layer comprising the semiconductor layer. | 01-30-2014 |
| 20140035147 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first interlayer dielectric layer having a conductive contact, forming a sacrifice layer having a conductive interconnection over the first interlayer dielectric layer such that the conductive interconnection is contacted with the conductive contact, removing the sacrifice layer, and forming a recess by removing a part of the conductive contact exposed by the conductive interconnection. | 02-06-2014 |
| 20140035148 | Bump on Pad (BOP) Bonding structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 02-06-2014 |
| 20140042631 | SEMICONDUCTOR COMPONENT COMPRISING COPPER METALLIZATIONS - A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy. | 02-13-2014 |
| 20140048941 | Contact Pads with Sidewall Spacers and Method of Making Contact Pads with Sidewall Spacers - A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls. | 02-20-2014 |
| 20140048942 | MOUNTED STRUCTURE - A mounted structure includes an electrode of a substrate, an electrode of a semiconductor element, and a mounted layers for bonding the electrode of the substrate and the electrode of the semiconductor element, and the mounted layers includes: a first intermetallic compound layer containing a CuSn-based intermetallic compound; a Bi layer; a second intermetallic compound layer containing a CuSn-based intermetallic compound; a Cu layer; and a third intermetallic compound layer containing a CuSn-based intermetallic compound, and the above layers are sequentially arranged from the electrode of the substrate toward the electrode of the semiconductor element to configure the mounted layers. | 02-20-2014 |
| 20140054780 | Method for Manufacturing an Electronic Module and an Electronic Module - A number of semiconductor chips each include a first main face and a second main face opposite from the first main face. The second main face includes at least one electrical contact element. The semiconductor chips are placed on a carrier. A material layer is applied into intermediate spaces between adjacent semiconductor chips. The carrier is removed and a first electrical contact layer is applied to the first main faces of the semiconductor chips so that the electrical contact layer is electrically connected with each one of the electrical contact elements. | 02-27-2014 |
| 20140054781 | Copper Ball Bond Features and Structure - An integrated circuit wire bond connection is provided having an aluminum bond pad ( | 02-27-2014 |
| 20140054782 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device according to an embodiment, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a high melting metal film on a side wall and a bottom surface of the opening; forming a seed film of copper (Cu) on the high melting metal film; performing nitriding process after the seed film is formed; and performing electroplating process, in which a Cu film is buried in the opening while energizing the seed film after performing nitriding process. | 02-27-2014 |
| 20140061927 | CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING - This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line. | 03-06-2014 |
| 20140061928 | INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR PACKAGE - An interconnection structure for being formed on bonding pads of a substrate in a semiconductor package is provided. The interconnection structure includes a nickel layer formed on each of the bonding pads, a metal layer formed on the nickel layer, and a solder material formed on the metal layer. The metal layer is made of one of gold, silver, lead and copper, and has a thickness in the range of 0.5 to 5 um. As such, when the solder material is reflowed to form solder bumps, no nickel-tin compound is formed between the solder bumps and the metal layer, thereby avoiding cracking or delamination of the solder bumps. | 03-06-2014 |
| 20140061929 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate. An interlayer dielectric film is provided on the lower-layer wiring and includes a four-layer stacked structure. A contact plug contains aluminum. The contact plug is filled in a contact hole formed in the interlayer dielectric film in such a manner that the contact plug reaches the lower-layer wiring. Two upper layers and two lower layers in the stacked structure respectively have tapers on an inner surface of the contact hole. The taper of two upper layers and the taper of two lower layers have different angles from each other. | 03-06-2014 |
| 20140077378 | LOW THERMAL STRESS PACKAGE FOR LARGE AREA SEMICONDUCTOR DIES - A low thermal stress package for large area semiconductor dies. The package may include a substrate and at least one pedestal extending from the substrate, wherein the pedestal may have a mounting surface that is smaller than a mounting surface of a semiconductor die that is mounted to the pedestal. The bonded area between the die and the pedestal is therefore reduced relative to conventional semiconductor package substrates, as is the amount of thermal stress sustained by the die during thermal cycling. | 03-20-2014 |
| 20140077379 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer. | 03-20-2014 |
| 20140091469 | METHODS OF PROVIDING DIELECTRIC TO CONDUCTOR ADHESION IN PACKAGE STRUCTURES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material. | 04-03-2014 |
| 20140097542 | FLIP PACKAGING DEVICE - Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal. | 04-10-2014 |
| 20140103531 | BONDED STRUCTURE - A bonded structure | 04-17-2014 |
| 20140110847 | BUMP-ON-TRACE INTERCONNECTION STRUCTURE FOR FLIP-CHIP PACKAGES - A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width W | 04-24-2014 |
| 20140117552 | X-LINE ROUTING FOR DENSE MULTI-CHIP-PACKAGE INTERCONNECTS - X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective. | 05-01-2014 |
| 20140117553 | PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING BODY HAVING SAME - A packaging substrate includes a base layer, a first wiring layer, a second wiring layer, a first solder mask layer, a second solder mask layer and copper portions. The first second wiring layers are arranged on opposite sides of the base layer. The first solder mask layer covers the first wiring layer, and defines plenty of first openings. The first wiring layer exposed through the first openings serves as first contact pads. The second solder mask layer covers the second wiring layer. The second solder mask layer defines plenty of second openings. The second wiring layer exposed through the second openings serves as second contact pads. The copper portions are formed on the second contact pads. The copper portions protrude beyond the second solder mask layer. This disclosure further relates to a method of manufacturing the packaging substrate and a chip packaging body. | 05-01-2014 |
| 20140124935 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have line widths of less than forty nanometers. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, performing a first sputter etch of the layer of conductive metal using a methanol plasma, and performing a second sputter etch of the layer of conductive metal using a second plasma, wherein a portion of the layer of conductive metal that remains after the second sputter etch forms the one or more conductive lines. | 05-08-2014 |
| 20140124936 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SAME - A power semiconductor module has an insulating layer; a copper base substrate having first and second copper blocks, either the first or the second copper block being fixed on one side and the other being fixed on the other side of the insulating layer; a plurality of power semiconductor elements using silicon carbide, and having one side fixed onto the first copper block with a conductive bond layer; a plurality of implant pins fixed to the other side of each of the plurality of power semiconductor elements with a conductive bond layer; a printed circuit board fixed to the implant pins and disposed to face the power semiconductor elements; a first sealing material containing no flame retardant, and disposed at least between the power semiconductor elements and the printed circuit board; and a second sealing material containing a flame retardant, and disposed to cover the first sealing material. | 05-08-2014 |
| 20140131875 | Z-CONNECTION USING ELECTROLESS PLATING - In one embodiment, an assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor. | 05-15-2014 |
| 20140131876 | METHOD FOR DICING A SEMICONDUCTOR WAFER HAVING THROUGH SILICON VIAS AND RESULTANT STRUCTURES - The present invention provides a semiconductor device, a semiconductor package and a semiconductor process. The semiconductor process includes the following steps: (a) providing a semiconductor wafer having a first surface, a second surface and a passivation layer; (b) applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; (c) applying a second laser, wherein the second laser passes through the exposed semiconductor wafer and focuses at an interior of the semiconductor wafer; and (d) applying a lateral force to the semiconductor wafer. Whereby, the cutting quality is ensured. | 05-15-2014 |
| 20140145338 | SEMICONDUCTOR DEVICE - A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction. | 05-29-2014 |
| 20140145339 | ENCAPSULANT FOR A SEMICONDUCTOR DEVICE - A mold compound is provided for encapsulating a semiconductor device ( | 05-29-2014 |
| 20140145340 | Flip Chip Interconnection Structure - A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock. | 05-29-2014 |
| 20140151888 | Air-Gap Formation in Interconnect Structures - A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps. | 06-05-2014 |
| 20140167269 | Methods and Apparatus of Packaging with Interposers - Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost. | 06-19-2014 |
| 20140175655 | CHIP BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip bonding structure at least includes a first substrate, a second substrate opposite to the first substrate, and a copper bonding structure sandwiched in between the first and the second substrates. A Cu—Cu bonding interface is within the copper bonding structure and is characterized with combinations of protrusions and recesses, and the copper crystallization orientation at one side of the Cu—Cu bonding interface is different from that at another side. | 06-26-2014 |
| 20140175656 | USE OF GRAPHENE TO LIMIT COPPER SURFACE OXIDATION, DIFFUSION AND ELECTROMIGRATION IN INTERCONNECT STRUCTURES - A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure. | 06-26-2014 |
| 20140183744 | PACKAGE SUBSTRATE WITH BONDABLE TRACES HAVING DIFFERENT LEAD FINISHES - A package substrate includes a workpiece having at least a top dielectric layer and a metal layer thereon which provides a plurality of metal traces on a surface of the top dielectric layer. A first solder resist layer provides covered trace portions of the plurality of metal traces. A second solder resist layer on the first solder resist layer defines an inner die attach region. The die attach region includes exposed trace portions of the metal traces. The exposed trace portions each include (i) a bonding area having a base metal and a metal or metal alloy surface finish thereon for bonding to bonding features of an integrated circuit (IC) die, and (ii) an interconnect trace portion on both sides of the bonding area including the base metal having a second surface finish thereon different from the metal or metal alloy surface finish. | 07-03-2014 |
| 20140197539 | Bonded System with Coated Copper Conductor - A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor. | 07-17-2014 |
| 20140210090 | Circuit module and method of manufacturing the same - Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact areas, the material of which contains a first metal. On the surface of the insulator layer are conductors, which comprise at least a first layer and a second layer, in such a way that at least the second layer contains a second metal. The circuit module comprises contact elements between the contact areas and the conductors for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area, an intermediate layer, which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (A | 07-31-2014 |
| 20140210091 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 μm to 10 μm from the edge of the concave to the bottom of the concave. | 07-31-2014 |
| 20140217593 | Electrical Connecting Element and Method for Manufacturing the Same - An electrical connecting element for connecting a first substrate and a second substrate and a method for manufacturing the same are disclosed. The method of the present invention comprises: (A) providing a first substrate and a second substrate, wherein a first copper film is formed on the first substrate, a first metal film is formed on the second substrate, a first connecting surface of the first copper film has a (111)-containing surface, and the first metal film has a second connecting surface; and (B) connecting the first copper film and the first metal film to form an interconnect, wherein the first connecting surface of the first copper film is faced to the second connecting surface of the first metal film. | 08-07-2014 |
| 20140232001 | Device Bond Pads Over Process Control Monitor Structures in a Semiconductor Die - A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region. The interlayer dielectric is passivated, and bond pads are provided over the interconnect wiring and electrically connected to the interconnect wiring through openings in the passivation over the active region. Additional bond pads are provided over the ancillary wiring and are electrically connected to the interconnect wiring through additional openings in the passivation over the active region. | 08-21-2014 |
| 20140232002 | SEMICONDUCTOR DEVICE, FABRICATION PROCESS, AND ELECTRONICDEVICE - A semiconductor device is provided, including a semiconductor substrate that includes a semiconductor; an electrode layer formed above a first surface side inside the semiconductor substrate; a conductor layer formed above the electrode layer and above the first surface of the semiconductor substrate; a hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate, the wiring layer being physically separated from the electrode layer by an insulating layer disposed therebetween. | 08-21-2014 |
| 20140232003 | Semiconductor Constructions, Semiconductor Processing Methods, Methods of Forming Contact Pads, and Methods of Forming Electrical Connections Between Metal-Containing Layers - Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component. | 08-21-2014 |
| 20140239502 | ELECTRONIC DEVICE COMPRISING AT LEAST A CHIP ENCLOSED IN A PACKAGE AND A CORRESPONDING ASSEMBLY PROCESS - An electronic device is described comprising at least one chip enclosed in a package, in turn provided with a metallic structure or leadframe having a plurality of connection pins, this chip having at least one first contact realized on a first face and at least one second contact realized on a second and opposite face of this chip. The chip comprises at least one through via crossing the whole section of the chip as well as a metallic layer extending from the second contact arranged on the first face, along walls of the at least one through via up to the second and opposite face in correspondence with an additional pad. The electronic device comprises at least one interconnection layer for the electrical and mechanical connection between the chip and the metallic structure having at least one portion realized in correspondence with the at least one through via so as to bring the second contact placed on the second face of the chip back on its first face. An assembly process of such an electronic device is also described. | 08-28-2014 |
| 20140264882 | Forming Fence Conductors Using Spacer Etched Trenches - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 09-18-2014 |
| 20140264883 | Interconnect Structure and Method of Forming Same - A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component. | 09-18-2014 |
| 20140264884 | WLCSP Interconnect Apparatus and Method - Disclosed herein is an interconnect apparatus comprising a substrate having a land disposed thereon and a passivation layer disposed over the substrate and over a portion of the land. An insulation layer is disposed over the substrate and has an opening disposed over at least a portion of the land. A conductive layer is disposed over a portion of the passivation layer and in electrical contact with the land. The conductive layer has a portion extending over at least a portion of the insulation layer. The conductive layer comprises a contact portion disposed over at least a portion of the land. The insulation layer avoids extending between the land and the contact portion. A protective layer may be disposed over at least a portion of the conductive layer and may optionally have a thickness of at least 7 μm. | 09-18-2014 |
| 20140284802 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another. | 09-25-2014 |
| 20140299995 | WIRING DEVICE FOR SEMICONDUCTOR DEVICE, COMPOSITE WIRING DEVICE FOR SEMICONDUCTOR DEVICE, AND RESIN-SEALED SEMICONDUCTOR DEVICE - A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal. | 10-09-2014 |
| 20140299996 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 10-09-2014 |
| 20140319688 | Protection Layers for Conductive Pads and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor device includes forming a metal line over a substrate and depositing an alloying material layer over a top surface of the metal line. The method further includes forming a protective layer by combining the alloying material layer with the metal line. | 10-30-2014 |
| 20140319689 | Contact Pads with Sidewall Spacers and Method of Making Contact Pads with Sidewall Spacers - A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls. | 10-30-2014 |
| 20140327143 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-06-2014 |
| 20140327144 | Complex Semiconductor Packages and Methods of Fabricating the Same - Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips. | 11-06-2014 |
| 20140332964 | INTERCONNECT STRUCTURES CONTAINING NITRIDED METALLIC RESIDUES - A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided. | 11-13-2014 |
| 20140339702 | METAL PVD-FREE CONDUCTING STRUCTURES - Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd). | 11-20-2014 |
| 20140339703 | STRUCTURE AND METHOD FOR MAKING CRACK STOP FOR 3D INTEGRATED CIRCUITS - A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed. | 11-20-2014 |
| 20140353831 | METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES - Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region. | 12-04-2014 |
| 20140353832 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of copper. | 12-04-2014 |
| 20140361436 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, STORAGE MEDIUM AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes forming a second conductive layer on an underlying layer which has an insulating layer in which a recess is formed and a first conductive layer exposed on a bottom surface of the recess; forming a third conductive layer on the second conductive layer; supplying, into the third conductive layer, a material solid-soluble in the third conductive layer; and heating the third conductive layer into which the solid-soluble material is supplied. | 12-11-2014 |
| 20140367858 | Thin Film Devices and Low Temperature Process To Make Thin Film Devices - A method for preparing a device having a film on a substrate is disclosed. In the method, a film is deposited on a substrate. The film includes a first and a second metal. The first and the second metals in the film are converted to an intermetallic compound using microwave radiation. One example device prepared by the method includes a silicon substrate and a film on the substrate, wherein the film includes semiconducting copper germanide as the intermetallic compound. | 12-18-2014 |
| 20140367859 | TIN-BASED WIREBOND STRUCTURES - Tin-based wirebond structures and wirebonds formed thereon. In some embodiments, an electronic package includes a semiconductor die located over a substrate and a wire configured to couple a terminal of the semiconductor die to a bond pad on the substrate. A wire bond between the wire and the bond pad may include an amount of tin originated from a layer of tin alloy formed on the bond pad. In other embodiments, a wirebond structure may include a conductive layer and a layer of tin alloy located over a portion of the conductive layer. The layer of tin alloy may provide a wirebonding contact surface configured to receive a bond wire. | 12-18-2014 |
| 20150021777 | MOUNTING STRUCTURE AND MOUNTING STRUCTURE MANUFACTURING METHOD - A mounting structure which reduces the mechanical stress added to a low-κ material due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting. This mounting structure includes: a low-κ layer formed on top a semiconductor substrate; an electrode layer formed on the low-κ layer; a protective layer formed the low-κ layer and the electrode layer and having an opening reaching the electrode layer; a first solder layer filling the opening and formed on the electrode layer inside; a second solder layer formed on the first solder layer and having an elastic modulus smaller than the first solder layer; and a support layer connected to the second solder layer and supporting the semiconductor substrate. The protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer. | 01-22-2015 |
| 20150021778 | CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING - This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line. | 01-22-2015 |
| 20150028483 | NOVEL METHOD FOR ELECTROMIGRATION AND ADHESION USING TWO SELECTIVE DEPOSITION - A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination. | 01-29-2015 |
| 20150035159 | SEMICONDUCTOR DEVICE HAVING BACKSIDE INTERCONNECT STRUCTURE ON THROUGH SUBSTRATE VIA AND METHOD OF FORMING THE SAME - A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. | 02-05-2015 |
| 20150048510 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive. | 02-19-2015 |
| 20150054159 | Semiconductor Module and a Method for Fabrication Thereof By Extended Embedding Technologies - The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips. | 02-26-2015 |
| 20150054160 | Semiconductor Constructions and Methods of Forming Electrically Conductive Contacts - Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A conductive plug is formed within a bottom region of the opening. A spacer is formed to line a lateral periphery of an upper region of the opening, and to leave an inner portion of an upper surface of the plug exposed. A conductive material is formed against the inner portion of the upper surface of the plug. Some embodiments include semiconductor constructions having a conductive plug within an insulative stack and against a copper-containing material. A spacer is over an outer portion of an upper surface of the plug and not directly above an inner portion of the upper surface. A conductive material is over the inner portion of the upper surface of the plug and against an inner lateral surface of the spacer. | 02-26-2015 |
| 20150069612 | RELIABLE SURFACE MOUNT INTEGRATED POWER MODULE - A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto. | 03-12-2015 |
| 20150076699 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal. | 03-19-2015 |
| 20150084198 | INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES - A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1. | 03-26-2015 |
| 20150084199 | Copper Ball Bond Features and Structure - An integrated circuit wire bond connection is provided having an aluminum bond pad ( | 03-26-2015 |
| 20150102492 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring. | 04-16-2015 |
| 20150108650 | EUTECTIC SOLDER STRUCTURE FOR CHIP - The present invention provides a eutectic solder structure for a chip including a substrate and a solder structure on the substrate. The solder structure includes an alternate lamination of a plurality of first metal layers and a plurality of second metal layers, wherein each second metal layer has a continuous region and a plurality of openings and the melting point of the plurality of second metal layers is higher than that of the plurality of first metal layers. The eutectic solder structure for a chip also includes a chip on the solder structure, wherein the chip is bonded to the substrate by a eutectic reaction of the solder structure. | 04-23-2015 |
| 20150115451 | METHOD AND APPARATUS FOR HIGH TEMPERATURE SEMICONDUCTOR DEVICE PACKAGES AND STRUCTURES USING A LOW TEMPERATURE PROCESS - A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver. | 04-30-2015 |
| 20150115452 | SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding layer between a substrate and a semiconductor chip, and the bonding layer may include an intermetallic compound. The intermetallic compound may be a compound of metal and solder material. The intermetallic compound may include Ag | 04-30-2015 |
| 20150145136 | VERTICALLY CONNECTED INTEGRATED CIRCUITS - In some examples, an integrated circuit (IC) includes a semiconductor substrate defining a perimeter of the integrated circuit and a castellation formed at the perimeter. The IC also may include a layer including an electrically conductive material formed on a surface of the castellation. In some examples, the layer including the electrically conductive material is not substantially parallel to adjacent portions of the perimeter of the IC. The integrated circuit may be used in a system, in which the metallized castellation may be used to electrically connect the IC to an external structure, such as another IC or a printed board. | 05-28-2015 |
| 20150318238 | DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS - Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. | 11-05-2015 |
| 20150318240 | ALUMINUM CLAD COPPER STRUCTURE OF AN ELECTRONIC COMPONENT PACKAGE - An electronic component package that includes a package substrate having an aluminum bond pad formed from an aluminum clad copper structure. The aluminum clad copper structure is attached to a dielectric layer. An electronic component is attached to the substrate and includes a conductive structure electrically coupled to the aluminum bond pad. The aluminum bond pad, the electronic component, and at least a portion of the substrate are encapsulated with an encapsulant. | 11-05-2015 |
| 20150318258 | DIE WARPAGE CONTROL FOR THIN DIE ASSEMBLY - Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate. | 11-05-2015 |
| 20150325511 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die. | 11-12-2015 |
| 20150332966 | WAFER FRONTSIDE-BACKSIDE THROUGH SILICON VIA - A wafer frontside-backside through silicon via and methods of manufacture are disclosed. The method includes forming a plurality of frontside metalized vias into a partial depth of a substrate. The method further includes forming a backside via in the substrate which exposes, from the backside, the plurality of frontside metalized vias. The method further includes forming a metal in the via in contact with the plurality of metalized frontside vias. | 11-19-2015 |
| 20150340283 | INTERCONNECT STRUCTURE AND METHODS OF MAKING SAME - A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy. | 11-26-2015 |
| 20150340328 | METHODS OF FORMING SEMICONDUCTOR DEVICE ASSEMBLIES AND INTERCONNECT STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE ASSEMBLIES AND INTERCONNECT STRUCTURES - A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. The solder-wetting material is contacted with the solder material. The first copper material, the solder-wetting material, the second copper material, and the solder material are converted into a substantially homogeneous intermetallic compound interconnect structure. Additional methods, semiconductor device assemblies, and interconnect structures are also described. | 11-26-2015 |
| 20150380273 | LIQUID COMPOSITION USED IN ETCHING MULTILAYER FILM CONTAINING COPPER AND MOLYBDENUM, MANUFACTURING METHOD OF SUBSTRATE USING SAID LIQUID COMPOSITION, AND SUBSTRATE MANUFACTURED BY SAID MANUFACTURING METHOD - The present invention provides a liquid composition used for etching a multilayer film containing copper and molybdenum, an etching method for etching a multilayer film containing copper and molybdenum, and a substrate. The present invention further provides a liquid composition for etching a multilayer-film wiring substrate which has an oxide layer (IGZO) including indium, gallium and zinc laminated on the substrate, and further a multilayer film including at least a layer containing molybdenum and a layer containing copper provided thereon, a method for etching a multilayer film containing copper and molybdenum from the substrate, and a substrate. According to the present invention, a liquid composition comprising (A) a maleic acid ion source, (B) a copper ion source, and (C) at least one type of amine compound selected from the group consisting of 1-amino-2-propanol, 2-(methylamino)ethanol, 2-(ethylamino)ethanol, 2-(butylamino)ethanol, 2-(dimethylamino)ethanol, 2-(diethylamino)ethanol, 2-methoxyethylamine, 3-methoxypropylamine, 3-amino-1-propanol, 2-amino-2-methyl-1-propanol, 1-dimethylamino-2-propanol, 2-(2-aminoethoxyl)ethanol, morpholine and 4-(2-hydroxyethyl)morpholine and having a pH value of 4-9 is used. | 12-31-2015 |
| 20160013143 | ELECTRONIC DEVICE | 01-14-2016 |
| 20160020378 | Metallization Having High Power Compatibility and High Electrical Conductivity - A metallization, for carrying current in an electrical component, includes a bottom layer overlying a substrate surface and includes titanium (Ti) or a titanium compound as main constituent. An upper layer overlies the bottom layer and includes copper (Cu) as main constituent. The bottom layer and the upper layer form a base layer. A top layer is in direct contact with the upper layer and includes aluminum (Al) as main constituent. The base layer further includes a middle layer, consisting of silver, that is arranged between the bottom layer and the upper layer. | 01-21-2016 |
| 20160027748 | METHOD OF FORMING A MEMORY DEVICE - A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. | 01-28-2016 |
| 20160056072 | MULTILAYERED CONTACT STRUCTURE HAVING NICKEL, COPPER, AND NICKEL-IRON LAYERS - A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer. | 02-25-2016 |
| 20160071765 | Through Via Structure and Method - A device comprises a via in a substrate comprising a lower via portion with a first width formed of a first conductive material and an upper via portion with a second width greater than the first width, wherein the upper via portion comprises a protection layer formed of the first conductive material and a via fill material portion formed of a second conductive material. | 03-10-2016 |
| 20160111368 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings. | 04-21-2016 |
| 20160126207 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a joined member that is joined to the semiconductor element and includes a nickel film; and a joining layer that is joined to the joined member and contains 2.0 wt % or higher of copper, in which the joining layer includes a solder portion and a Cu | 05-05-2016 |
| 20160126208 | COATED BONDING WIRE AND METHODS FOR BONDING USING SAME - A semiconductor device includes a bond formed on a bond pad. The bond is formed of a wire that includes a central core of conductive metal, a first coating over the central core of conductive metal that is more chemically active than the conductive metal, and a second coating over the central core of conductive metal that is less chemically active than the central core of conductive metal. | 05-05-2016 |
| 20160133537 | SEMICONDUCTOR PACKAGE WITH EMBEDDED COMPONENT AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes. | 05-12-2016 |
| 20160133572 | METHODS OF FORMING A PROTECTIVE LAYER ON AN INSULATING LAYER FOR PROTECTION DURING FORMATION OF CONDUCTIVE STRUCTURES - One illustrative method disclosed herein includes, among other things, performing at least one etching process through an overall masking layer to define an opening in a layer of insulating material, wherein the overall masking layer is comprised of a patterned metal-silicate masking layer that is positioned on and in contact with the layer of insulating material and a patterned masking layer positioned on and in contact with the patterned metal-silicate masking layer, over-filling the opening with a conductive material and performing at least one planarization process so as to remove excess materials positioned outside of the opening above the patterned metal-silicate masking layer and thereby define a conductive structure that is positioned in the opening. | 05-12-2016 |
| 20160133573 | MICROSTRUCTURE OF METAL INTERCONNECT LAYER - A metal interconnect layer, a method of forming the metal interconnect layer, a method of forming a device that includes the metal interconnect layer are described. The method of forming the metal interconnect layer includes forming an opening in a dielectric layer, forming a metal layer in the opening and over a top surface of the dielectric layer. The method also includes disposing a metal passivation layer on an overburden portion of the metal layer formed over the top surface of the dielectric layer. The metal passivation layer includes a metal selected from a group of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), any alloy thereof, nitrides of Co, Ru, Ti, Ni, or W, and any combination thereof. The method also includes performing an anneal at a temperature exceeding 100 degrees centigrade and below 300 degrees centigrade. | 05-12-2016 |
| 20160133584 | SEMICONDUCTOR DEVICE AND AN ELECTRONIC DEVICE - According to various embodiments, a semiconductor device may include: a contact pad; a metal clip disposed over the contact pad; and a porous metal layer disposed between the metal clip and the contact pad, the porous metal layer connecting the metal clip and the contact pad with each other. | 05-12-2016 |
| 20160148857 | Semicondutor Device and Method of Manufacture - A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die. | 05-26-2016 |
| 20160148896 | SEMICONDUCTOR DEVICE WITH A WIRE BONDING AND A SINTERED REGION, AND MANUFACTURING PROCESS THEREOF - An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the semiconductor body; and a conductive wire, electrically connected to the front metallization region. The top buffer region is at least partially sintered. | 05-26-2016 |
| 20160155685 | THROUGH-SUBSTRATE STRUCTURE AND MEHTOD FOR FABRICATING THE SAME | 06-02-2016 |
| 20160155714 | SEMICONDUCTOR DEVICE, A POWER SEMICONDUCTOR DEVICE, AND A METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE | 06-02-2016 |
| 20160163665 | CHIP STRUCTURE HAVING BONDING WIRE - A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy. | 06-09-2016 |
| 20160181202 | MICROELECTRONIC DEVICES WITH MULTI-LAYER PACKAGE SURFACE CONDUCTORS AND METHODS OF THEIR FABRICATION | 06-23-2016 |
| 20170236643 | ELECTRONIC COMPONENT HAVING A CONNECTION ELEMENT | 08-17-2017 |
| 20170236780 | INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME | 08-17-2017 |
