| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257760000 | Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride) | 28 |
| 20080272493 | Semiconductor device - A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer. | 11-06-2008 |
| 20080308941 | HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING - An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal. | 12-18-2008 |
| 20090008782 | INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF - An integrated circuit structure is provided. The integrated circuit structure includes a dielectric layer, a conductive structure, a low-k dielectric layer and a plug. The conductive structure is disposed in the dielectric layer, having a recess portion. The low-k dielectric layer is disposed on the dielectric layer. The plug is disposed in the low-k dielectric layer and has a protruding bonding portion on the bottom of the plug. The bonding portion is extended into the dielectric layer and connected to the recess portion of the conductive structure. | 01-08-2009 |
| 20090008783 | SEMICONDUCTOR DEVICE WITH PADS OF ENHANCED MOISTURE BLOCKING ABILITY - A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film. | 01-08-2009 |
| 20090026621 | Bond pad stacks for ESD under pad and active under pad bonding - A combination of layout improvements and inner layer dielectric (ILD) material improvements provides a bond pad stack that is robust for both gold (Au) and copper (Cu) wires in circuits with only one or two pad metal layers. The layout improvements involve removing all vias between the top metal layer and the metal layers below top metal in the area under the passivation opening (where probe tips and the bond wire are placed). This allows for a more homogenous material without via discontinuities, thereby reducing stress concentration points in the ILD. The ILD material improvement involves adding a layer of silicon nitride in addition to the silicon oxide layer. Traditionally, the ILD consists of either spun-on or high density plasma (HDP) oxides. The growth of the thin layer of silicon nitride over the oxide on the topmost ILD layer provides a composite of significantly increased toughness and prevents cracks or other damage from propagating into the underlying active circuits and routing. | 01-29-2009 |
| 20090057907 | INTERCONNECTION STRUCTURE - An interconnection structure includes an inter-layer dielectric; a topmost copper metal layer inlaid into the inter-layer dielectric; an insulating layer disposed on the inter-layer dielectric and the topmost copper metal layer; a via opening in the insulating layer for exposing a top surface of the topmost copper metal layer, wherein the via opening consists of an inwardly tapered upper via portion and a lower via portion having a substantially vertical sidewall profile; and an aluminum layer filling into the via opening. | 03-05-2009 |
| 20090160059 | Semiconductor Device Having Improved Adhesion and Reduced Blistering Between Etch Stop Layer and Dielectric Layer - One aspect of the invention provides a method of forming a semiconductor device ( | 06-25-2009 |
| 20090256261 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 10-15-2009 |
| 20090256262 | SEMICONDUCTOR DEVICES INCLUDING POROUS INSULATORS - Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties. | 10-15-2009 |
| 20090294969 | SEMICONDUCTOR CONTACT FORMATION SYSTEM AND METHOD - The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region. | 12-03-2009 |
| 20100276805 | INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP - An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion. | 11-04-2010 |
| 20110095430 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion. | 04-28-2011 |
| 20110304048 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential. | 12-15-2011 |
| 20120161325 | SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device package is provided. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of vias extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more vias; a patterned interconnect layer disposed on dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. The patterned interconnect layer comprises a top interconnect region and a via interconnect region, wherein the package interconnect region has a thickness greater than a thickness of the via interconnect region. | 06-28-2012 |
| 20120273953 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-01-2012 |
| 20120280396 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-08-2012 |
| 20130228928 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a stacked body, a second conductive layer, a second insulating layer, a tubular semiconductor pillar, an insulating film and an occlusion film. The second conductive layer is provided on the stacked body. The second insulating layer is provided on the second conductive layer. The tubular semiconductor pillar is provided in such a manner as to pass through the second insulating layer, the second conductive layer and the stacked body. The insulating film is provided between the semiconductor pillar, and the second insulating layer, the second conductive layer and the stacked body. The occlusion film occludes the tube in a lower portion of the portion passing through the second insulating layer in the semiconductor pillar. The tube below the occlusion film in the semiconductor pillar is an air gap. | 09-05-2013 |
| 20140035146 | METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer. | 02-06-2014 |
| 20140061926 | SEMICONDUCTOR DEVICES INCLUDING SUPPORTING PATTERNS IN GAP REGIONS BETWEEN CONDUCTIVE PATTERNS AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions. The adjacent ones of the conductive patterns extend away from the substrate surface beyond a surface of the supporting pattern therebetween. A capping layer is provided on respective surfaces of the conductive patterns and the surface of the supporting pattern. Related fabrication methods are also discussed. | 03-06-2014 |
| 20140145337 | Memory Device Interconnects and Method of Manufacture - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines extend through the first inter-level dielectric layer. Each of a plurality of source line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines. Each of the plurality of staggered bit line contacts extend through the first and second inter-level dielectric layes to respective bit lines. | 05-29-2014 |
| 20140151887 | Memory Device Interconnects and Method of Manufacture - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes. | 06-05-2014 |
| 20150035157 | SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE - After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed , and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer. | 02-05-2015 |
| 20150130065 | method to etch cu/Ta/TaN selectively using dilute aqueous Hf/h2so4 solution - Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H | 05-14-2015 |
| 20150294933 | PATTERN BETWEEN PATTERN FOR LOW PROFILE SUBSTRATE - An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer. | 10-15-2015 |
| 20150311158 | METHOD OF FORMING A HIGH DENSITY DIELECTRIC ETCH-STOP LAYER - Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged over the semiconductor substrate. An etch-stop layer is arranged over the inter-level dielectric layer. The etch-stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and has a density greater than or equal to 2.15 g/cm | 10-29-2015 |
| 20160172298 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | 06-16-2016 |
| 20160197011 | Subtractive Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects | 07-07-2016 |
| 20160379932 | INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER - An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact. | 12-29-2016 |
