Class / Patent application number | Description | Number of patent applications / Date published |
257739000 | With textured surface | 21 |
20090079075 | INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME - The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material. | 03-26-2009 |
20090079076 | PATTERNABLE DIELECTRIC FILM STRUCTURE WITH IMPROVED LITHOGRAPHY AND METHOD OF FABRICATING SAME - The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate, said inorganic antireflective coating is vapor deposited and comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La; forming at least one interconnect pattern within the at least one patternable low-k material; and curing the at least one patternable low-k material. The inventive method can be used to form dual-damascene interconnect structures as well as single-damascene interconnect structures. | 03-26-2009 |
20090273082 | METHODS AND DESIGNS FOR LOCALIZED WAFER THINNING - Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described. | 11-05-2009 |
20100270673 | METHOD FOR CONNECTING TWO JOINING SURFACES - The invention relates to a method for connecting two joining surfaces, particularly in the field of semiconductors, wherein at least one joining surface is produced by depositing a layer comprising 20 to 40% gold and 80 to 60% silver onto a substrate and selectively removing the silver from the deposited layer in order to produce a nanoporous gold layer as a joining surface. The joining surface with the nanoporous gold layer and an additional joining surface are disposed one above the other and pressed together. | 10-28-2010 |
20110018132 | OBJECT INCLUDING A GRAPHIC ELEMENT TRANSFERRED ON A SUPPORT AND METHOD FOR MAKING SUCH AN OBJECT - An object including at least one graphic element, including at least one layer including at least one metal and etched according to a pattern of the graphic element, a first face of the layer being positioned opposite a face of at least one at least partly transparent substrate, a second face, opposite to the first face, of the layer being covered with at least one passivation layer fixed to at least one face of at least one support by wafer bonding and forming with the support a monolithic structure, and the layer including at least at the second face, at least one area including the metal and at least one semiconductor. | 01-27-2011 |
20110018133 | ELECTRIC VIA WITH A ROUGH LATERAL SURFACE - A via connecting the front surface of a semiconductor substrate to its rear surface, this via having a rough lateral surface. | 01-27-2011 |
20110147932 | CONTACT-BASED ENCAPSULATION - An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip. | 06-23-2011 |
20110169164 | WIRING SUBSTRATE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE - A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess. | 07-14-2011 |
20120061835 | DIE STRUCTURE, DIE ARRANGEMENT AND METHOD OF PROCESSING A DIE - A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded. | 03-15-2012 |
20120153473 | LEAD PIN FOR PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE PRINTED CIRCUIT BOARD INCLUDING THE SAME - Disclosed herein is a lead pin for a package substrate including a connection pin, and a head part including a flange part formed at one end of the connection pin and having one surface bonded to the connection pin and a flat part formed at the other surface of the flange part and having at least one groove formed along an outer circumference thereof. According to the present invention, the grooves are formed along the outer circumference of the flat part of the head part of the lead pin to increase a bonding area, thereby making it possible to increase bonding strength of the lead pin. | 06-21-2012 |
20120319277 | THIN FILM TRANSISTOR PANEL AND MANUFACTURING METHOD THEREOF - Disclosed is a thin film transistor panel, comprising a substrate, an insulation layer and transparent conducting material. The insulation layer comprises projections at the back side not facing the substrate. A space between two adjacent projections is 1 μm-10 μm; the transparent conducting material is formed on the top surface and the lateral surface of the projections of the insulation layer. Otherwise, the transparent conducting material is formed on the top surface and the plane surface around the bottom of the projections or formed on the top surface, the lateral surface and the plane surface around the bottom of the projections. The present invention also discloses a manufacturing method of the thin film transistor panel. | 12-20-2012 |
20130105974 | SEMICONDUCTOR PACKAGE FEATURING FLIP-CHIP DIE SANDWICHED BETWEEN METAL LAYERS | 05-02-2013 |
20140021609 | WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A wiring substrate includes: a substrate; an insulator formed in the substrate and having a through hole; an electrode formed in the substrate and provided within the through hole; and a conductor bonded to the electrode and provided within the through hole, wherein the through hole has a shape that is widened toward a direction away from the substrate, and the conductor is configured to cover the entire top surface of the electrode and has a shape that is widened toward the direction away from the substrate. | 01-23-2014 |
20140110843 | Semiconductor Unit with Submount for Semiconductor Device - A semiconductor unit includes a submount and a chip coupled to the submount. The submount is configured with a base and a plurality of layers between the base and the chip. One of the layers, a heat-spreading electro-conducting sliver (“Ag”) layer, is deposited atop the base. The thickness of the Ag layer is selected so that a cumulative coefficient of thermal expansion of the submount substantially matches that one of the chip. Coupled to the active zone of the chip is a stress-dumping layer made from elastic malleable materials. | 04-24-2014 |
20140151882 | THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING STABILIZATION STRUCTURE FOR POWER SUPPLY VOLTAGE, AND METHOD FOR MANUFACTURING SAME - The three-dimensional integrated circuit has a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip is provided with a power supply wiring layer which has a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the semiconductor chip, and a ground wiring layer in succession, and one of the first semiconductor chip and the second semiconductor chip further includes a second ground wiring layer or a second power supply wiring layer on a surface facing to the other semiconductor chip. | 06-05-2014 |
20140191398 | Ultraviolet Reflective Rough Adhesive Contact - A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile. | 07-10-2014 |
20140374903 | METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS - The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility. | 12-25-2014 |
20150048505 | WIRING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface. | 02-19-2015 |
20160086914 | METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS - The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility. | 03-24-2016 |
20160086915 | METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS - The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility. | 03-24-2016 |
20160086916 | METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS - The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility. | 03-24-2016 |