| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257702000 | Of insulating material other than ceramic | 19 |
| 20080211086 | Mounting method of electronic components, manufacturing method of electronic component-embedded substrate, and electronic component-embedded substrate - There is disclosed a fixing method of an electronic component or the like in which when the electronic component and a resin layer are fixed, warp and bend of the electronic component can be inhibited. During manufacturing of a semiconductor-embedded substrate | 09-04-2008 |
| 20080224304 | Physical quantity sensor and semiconductor device having package and cover - A semiconductor device includes: a semiconductor chip; a package for accommodating the chip, wherein the package has a box shape with an opening and a bottom; and a cover for sealing the opening of the package. The semiconductor chip is disposed on the bottom of the package. The cover has a plate shape. The cover includes a protrusion, which is disposed at a center of the plate shape. The protrusion protrudes toward an outside of the package. | 09-18-2008 |
| 20080237838 | Semiconductor device - The semiconductor device includes a plurality of semiconductor chips, and a circuit substrate having a substantially rectangular outer shape. The semiconductor device is an MCM having an MCM packaging structure in which the plurality of semiconductor chips are juxtaposed on the semiconductor chip mounting surface of the circuit substrate, and the semiconductor chip mounting surface is covered by a sealing resin along an outer edge of the circuit substrate so that the plurality of semiconductor chips are sealed. The thickness of the semiconductor chip to be mounted so as to traverse a center line has a thicker thickness in a direction perpendicular to the semiconductor chip mounting surface than the thickness of any of the other semiconductor chips which is mounted on the semiconductor chip mounting surface, the center line being defined an intersection of (i) a longitudinal cross section which divides the semiconductor chip mounting surface into two in a longitudinal direction of the semiconductor chip mounting surface and (ii) a transverse cross section which divides the semiconductor chip mounting surface into two in a transverse direction of the semiconductor chip mounting surface. This enables to suppress the warpage generated in the semiconductor device, and to reduce inadequate connection occurred due to the warpage in the semiconductor device. | 10-02-2008 |
| 20080265402 | REWORK PROCESS AND METHOD FOR LEAD-FREE CAPPED MULTI-CORE MODULES WITH ORGANIC SUBSTRATES - A system and method for utilizing lead-free multi-core modules with organic substrates,including a base portion configured to attach a semiconductor chip;and a cap portion further comprising: a bottom portion configured to be sealed to the base portion;and a vacuum port;wherein when a vacuum is drawn at the vacuum port,a re-workable seal between the base portion and the cap portion is provided to enable rework. | 10-30-2008 |
| 20080284000 | Integrated Circuit Packages, Methods of Forming Integrated Circuit Packages, And Methods of Assembling Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages. | 11-20-2008 |
| 20090026604 | Semiconductor plastic package and fabricating method thereof - A semiconductor plastic package and a method of fabricating the semiconductor plastic package are disclosed. A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board. | 01-29-2009 |
| 20090057875 | Semiconductor device - A highly reliable semiconductor device which is not damaged by local pressing force from the outside and in which unevenness of a portion where an antenna and an element overlap with each other is reduced. The semiconductor device includes a chip and an antenna. The chip includes a semiconductor element layer including a thin film transistor; a conductive resin electrically connected to the semiconductor element layer; and a sealing layer. The sealing layer in which a fiber body is impregnated with an organic resin covers the semiconductor element layer and the conductive resin, and has a thickness of 10 to 100 μm. The antenna has a depressed portion and is electrically connected to the semiconductor element layer through the conductive resin. The chip is embedded inside the depressed portion. The thickness of the chip is equal to the depth of the depressed portion. | 03-05-2009 |
| 20090085193 | Heat-releasing printed circuit board and semiconductor chip package - A heat-releasing printed circuit board and semiconductor chip package are disclosed. The heat-releasing printed circuit board includes an insulation layer, on a surface of which a circuit pattern is formed, and a solder resist, which is stacked on the insulation layer, where the solder resist contains carbon nanotubes. The heat-releasing printed circuit board allows the heat generated in a semiconductor chip to be dispersed in several directions of the board or package, to improve heat-releasing property. | 04-02-2009 |
| 20090152711 | RECTIFICATION CHIP TERMINAL STRUCTURE - The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip surrounded by an insulation portion. The conductive element has a root portion to connect the rectification chip. The root portion is extended to form a buffer section. The coupling collar is located at one end of the base to hold the package. The installation pedestal and the inner rim of the base are interposed by a gap. At least one hook portion is formed between the installation pedestal and the bottom of the gap. Thus the base does not turn against the package. The coupling collar has two ends formed an area different from any cross section area of the inner wall thereof. | 06-18-2009 |
| 20090273076 | Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same - Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component. | 11-05-2009 |
| 20090278252 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To reduce defects of a semiconductor device, such as defects in shape and characteristic due to external stress and electrostatic discharge. To provide a highly reliable semiconductor device. In addition, to increase manufacturing yield of a semiconductor device by reducing the above defects in the manufacturing process. The semiconductor device includes a semiconductor integrated circuit sandwiched by impact resistance layers against external stress and an impact diffusion layer diffusing the impact and a conductive layer covering the semiconductor integrated circuit. With the use of the conductive layer covering the semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit can be prevented. | 11-12-2009 |
| 20090302457 | WIRING SUBSTRATE, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - A wiring substrate is provided, including an insulating resin layer which is provided on both surfaces of a sheet-like fibrous body and with which the sheet-like fibrous body is impregnated, and a through wiring provided in a region surrounded by the insulating resin layer. The through wiring is formed using a conductive material, the conductive material is exposed on both surfaces of the insulating resin layer, the sheet-like fibrous body is positioned in the conductive material, and the sheet-like fibrous body is impregnated with the conductive material. A manufacturing method of the wiring substrate is also provided. | 12-10-2009 |
| 20100072611 | Semiconductor Device and Method for Manufacturing the Same - An object is to provide a thin and small semiconductor device that has high reliability and high resistance to external stress and electrostatic discharge. Another object is to manufacture a semiconductor device with high yield while shape defects and defective characteristics which are caused by external stress or electrostatic discharge are prevented in the manufacturing process. A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown (malfunction of the circuit or damage to a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge. By providing an antenna on the external side of the conductive shield, a sufficient communication capability is secured. With the use of a pair of insulators which sandwich the semiconductor integrated circuit, a thin and small semiconductor device that has resistance properties and high reliability can be provided. Further, shape defects and defective characteristics which are caused by external stress or electrostatic discharge are prevented in the manufacturing process, so that a semiconductor device can be manufactured with high yield. | 03-25-2010 |
| 20100164092 | SEMICONDUCTOR PROCESS, AND SILICON SUBSTRATE AND CHIP PACKAGE STRUCTURE APPLYING THE SAME - A semiconductor process is provided. First, a silicon base is provided. Next, a surface of the silicon base is partially exposed and at least a stair structure is formed on the silicon base by etching the surface of the silicon base. The stair structure has a first notch with a first depth and a second notch with a second depth. The first depth is smaller than the second depth, and a diameter of the first notch is larger than a diameter of the second notch. A final insulating layer and a metal seed layer are sequentially formed on the stair structure. A patterned photoresist layer is formed on the metal seed layer. A circuit layer coving exposed portions of the metal seed layer located above the first notch is formed. The patterned photoresist layer and portions of the metal seed layer disposed below the patterned photoresist layer are then removed. | 07-01-2010 |
| 20100213606 | DIELECTRIC ENHANCEMENTS TO CHIP-TO-CHIP CAPACITIVE PROXIMITY COMMUNICATION - A method for improving signal levels between capacitively-coupled chips in proximity communication (PxC) includes depositing a high permittivity dielectric material layer over a signal pad of a first chip, and placing a second chip in close proximity to the first chip such that faces of the signal pads align to enable for capacitive signal coupling. The high permittivity dielectric material layer that fills at least a portion of a gap between the first chip and the second chip, and improves capacitive coupling between signal pads of the first chip and the second chip by providing for an increased permittivity in the gap between the first chip and the second chip. The increased permittivity ensures that electric fields are substantially confined to a space between the signal pad of the first chip and the signal pad of the second chip. | 08-26-2010 |
| 20110156243 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication. | 06-30-2011 |
| 20160079134 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip comprising a first and second terminal surfaces. An insulator surrounds an outer circumference of a side surface of the chip. A reinforcing-member is arranged between the side surface of the chip and an inner side surface of the insulator and surrounds the outer circumference of the side surface of the chip. A first and second holders hold the reinforcing-member therebetween at a top and bottom surfaces of the reinforcing-member. The first and second holders comprise protrusions facing an inner wall surface of the reinforcing-member, and the when φ1in represents an inner-diameter of parts of the reinforcing-member opposing to the protrusions, φ1out represents an outer-diameter of the reinforcing-member, φ2 represents an outer-diameter of the protrusion of either the first or the second holder, and φ3 represents an inner diameter of the insulator, the following Expression 1 is satisfied φ1in−φ2<φ3-φ1out. | 03-17-2016 |
| 20160141225 | LATENT HEAT STORAGE DEVICES - An apparatus including a composite structure including an expanded graphite matrix infiltrated with a phase change material having dimensions configured for association with an electronic device, the composite structure including a thermal conductivity greater than 5 Watts per meter Kelvin (W/mK). An apparatus including an integrated circuit package; a planar pad including an expanded graphite matrix; and a heat sink, wherein the pad is disposed between the integrated circuit package and the heat sink. A method including placing a structure including an expanded graphite matrix on an integrated circuit package; and coupling a passive heat exchanger to the structure. | 05-19-2016 |
| 20160172313 | SUBSTRATE WITH A SUPPORTING PLATE AND FABRICATION METHOD THEREOF | 06-16-2016 |
