| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257680000 | With window means | 68 |
| 20080211075 | IMAGE SENSOR CHIP SCALE PACKAGE HAVING INTER-ADHESION WITH GAP AND METHOD OF THE SAME - A structure of semiconductor device package having inter-adhesion with gap comprising: a chip with bonding pads and a sensor area embedded into a substrate with die window and inter-connecting through holes, wherein a RDL is formed over the substrate for coupling between the bonding pads and the inter-connecting through holes; a multiple rings (dam bar) formed over the substrate, the RDL, and the bonding pads area except the sensor area; an adhesive glues fill into the space of the multiple ring except the sensor area; and a transparency material bonded on the top of the multiple ring and the adhesive glues, wherein the adhesive glues adhesion between the transparency material and the multiple rings. | 09-04-2008 |
| 20080265388 | ULTRA THIN IMAGE SENSING CHIP PACKAGE - An ultra thin image sensing chip package includes an image sensing chip and a flexible and optically transparent film. The chip has an image sensor and a plurality of electrical conductive pads. The flexible and optically transparent film includes a transparent window, and a pattern of conductors formed on a surface thereof and around the transparent window. The film wraps the chip in such a way that the transparent window thereof corresponds to the image sensor of the chip, a sealed space is formed between the transparent window and the image sensor, one end of each of the conductors of the film bonds to each of the electrical conductive pads of the chip, and the other end of each of the conductors of the film is opened so as to electrically connect with other electrical elements. | 10-30-2008 |
| 20080272473 | OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides an optical device ( | 11-06-2008 |
| 20080272474 | APPARATUS FOR INTEGRATED CIRCUIT COOLING DURING TESTING AND IMAGE BASED ANALYSIS - An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die. | 11-06-2008 |
| 20080283988 | PACKAGE AND PACKAGING ASSEMBLY OF MICROELECTROMECHANICAL SYSYEM MICROPHONE - A package of microelectromechanical system (MEMS) microphone is suitable for being mounted on a printed circuit board. The package has a cover and at least one MEMS microphone. The cover has an inner surface and a conductive trace disposed thereon. The MEMS microphone is mounted on the inner surface of the cover and electrically connected to the conductive trace, and has an acoustic pressure receiving surface. When the cover is mounted on the printed circuit board, the cover and the printed circuit board construct an acoustic housing which has at least one acoustic hole passing through the cover or the printed circuit board, and the conductive trace on the inner surface of the cover is electrically connected to the printed circuit board. | 11-20-2008 |
| 20080290489 | Package structure and electronic device using the same - A package structure and an electronic device using the same are provided. The package structure includes a chip module and a cover. The chip module covered by the cover is used for receiving a first signal. The chip module includes a substrate, a heat sink and a first chip. The substrate has a first surface, a second surface and an opening. The first surface is opposite to the second surface. The opening penetrates the first surface and the second surface. The heat sink is disposed on the first surface of the substrate and covers the opening. The first chip is disposed on the heat sink and is positioned inside the opening. A bottom surface of the first chip flatly contacts the heat sink. The cover has a window element. The first signal passes through the window element to contact with the chip module. | 11-27-2008 |
| 20080303129 | Patterned contact sheet to protect critical surfaces in manufacturing processes - The invention is directed a patterned contact sheet and to a method of bonding a cover wafer to an interposer wafer using the patterned contact sheet having a waffle-like pattern of a plurality of ridges and plurality of wells to form a cover/interposer combination or unit that can be bonded to a substrate having a MEMs device thereon, the cover wafer, interposer wafer and substrate together forming a protective packaging for the MEMS. Use of the patterned contact sheet results fewer defects on the window area (the critical area) through which light is transmitted. Surprisingly, use of the patterned contact sheet also results in windows having improved flatness relative to windows made using an unpatterned contact sheet. | 12-11-2008 |
| 20090014856 | MICROBUMP SEAL - A sealable microelectronic device providing mechanical stress endurance which includes a semiconductor substrate. A substantially continuous sealing element is positioned adjacent an outer periphery and between a microelectronic component and the semiconductor substrate, or another microelectronic component. The sealing element seals the microelectronic component to the substrate or another microelectronic component, and provides structural support to the microelectronic device. | 01-15-2009 |
| 20090032924 | HERMETICALLY SEALED PACKAGE WITH WINDOW - A method for manufacturing a cover assembly including a transparent window portion and a frame of gas-impervious material that can be hermetically attached to a micro-device package base to form a hermetically sealed micro-device package. First a frame of gas-impervious material is provided the frame having a continuous sidewall defining a frame aperture there through. The sidewall includes a frame seal-ring area circumscribing the frame aperture. A sheet of a transparent material is also provided, the sheet having a window portion defined thereupon. The window portion has finished top and bottom surfaces. A sheet seal-ring area is prepared on the sheet, the sheet seal-ring area circumscribing the window portion. The frame is positioned against the sheet such that at least a portion of the frame seal-ring area and at least a portion of the sheet seal-ring area contact one another along a continuous junction region that circumscribes the window portion. The frame is pressed against the sheet with sufficient force to produce a predetermined contact pressure between the frame seal-ring area and the sheet seal-ring area along the junction region. The junction region is heated to produce a predetermined temperature along the junction region. The predetermined contact pressure and the predetermined temperature are maintained until a diffusion bond is formed between the frame and sheet all along the junction region. | 02-05-2009 |
| 20090032925 | PACKAGING WITH A CONNECTION STRUCTURE - In a package including an image sensor die with an interconnect extending therethrough, a cover allowing light to pass is coupled to the die using at least one solder ball and a corresponding number of pads on each of the cover and die. Such pads are added to the cover despite the die's interconnect allowing contact with external devices at a location distal from the cover. The solder balls help govern the parallel orientation (or an alternate orientation) between the die and the cover. In addition, connectors other than solder balls may be used; multi-layered covers with connectors between the layers may be used; and packages other than imagers may be assembled. | 02-05-2009 |
| 20090039489 | METHOD OF PRODUCING OPTICAL MEMS - A method and apparatus for constructing MEMS devices is provided which employs a low cost molded housing that simultaneously provides precise and accurate alignment, mechanical protection, electrical connections and structural integrity for mounting optical and MEMS components. The package includes a MEMS die mounting surface, an optical component mounting surface and an optical imaging window monolithically fabricated with the MEMS die mounting surface in a predetermined orientation for providing alignment between the MEMS die and optical components. A MEMS adaptor plate is provided to facilitate connections of a MEMS die to external components. | 02-12-2009 |
| 20090045495 | SEMICONDUCTOR DEVICE WITH SIDE TERMINALS - Side terminals | 02-19-2009 |
| 20090057859 | WINDOW-TYPE BALL GRID ARRAY PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A window-type ball grid array (WBGA) package structure includes a substrate, fingers, traces, a solder mask, a die, a window mold compound and solder balls. The substrate has a first surface and a second surface and a window passing there-through. The fingers are on the first surface near the window, and each trace is on the first surface and connected to each finger. Moreover, the traces and a part of the fingers connected thereto are covered by the solder mask. The die is on the second surface and covers the window, and the window is filled by the window mold compound extendedly covering a part of a top surface of the solder mask. Additionally, the solder balls are on the first surface. Due to the foregoing structure, the stress near the fingers may be reduced and thus the lifetime of WBGA package structure may be efficiently increased. | 03-05-2009 |
| 20090057860 | Semiconductor memory package - Disclosed is a semiconductor memory package having a thin-film decoupling capacitor that reduces radio frequency noise. The semiconductor memory package in accordance with an embodiment of the present invention includes a substrate, a memory chip being mounted on one side of the substrate and a decoupling capacitor formed in the vicinity one the side of the substrate where the memory chip is mounted. | 03-05-2009 |
| 20090108426 | OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME - An optical device includes a semiconductor substrate ( | 04-30-2009 |
| 20090134504 | Semiconductor package and packaging method for balancing top and bottom mold flows from window - A window-type semiconductor package to balance top and bottom moldflows and its method are revealed. The package primarily comprises a substrate having a slot, a chip, and an encapsulant. After die attaching, an input opening and an output opening are formed and exposed from both ends of the slot. The slot is off-center designed so that the dimension of the input opening is smaller than the one of the output opening. The encapsulant has a top molding portion formed on the top surface of the substrate and a smaller bottom molding portion formed on the bottom surface of the substrate. The mold-flowing speeds between the top molding portion and the bottom molding portion are balanced to eliminate trapped air bubbles in the top mold and to avoid the flooding of the molding compound in the bottom mold. | 05-28-2009 |
| 20090134505 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to the present invention, protrusions | 05-28-2009 |
| 20090140405 | SEMICONDUCTOR DEVICE AND RESIN ADHESIVE USED TO MANUFACTURE THE SAME - A semiconductor device includes: a semiconductor element; a package body having the semiconductor element bonded inside thereof and electrically connected to the semiconductor element; a lid-like member covering the semiconductor element, and bonded to the package body to form a hollow structure; and a bonding member for bonding the package body and the lid-like member to each other. The bonding member is a resin adhesive containing an epoxy resin, a polymerization initiator, and a filling material, and a content of the filling material in the bonding member is 30 wt % to 60 wt %. | 06-04-2009 |
| 20090140406 | Semiconductor Mount - A mount for a semiconductor device has a first surface with at least one contact region and a second surface. The mount has a substrate to receive the second surface of the semiconductor device and a planar element. The planar element has an aperture sized to surround the semiconductor. A first surface of the planar element is mounted to the substrate and is located to surround the semiconductor device such that the semiconductor device is aligned by the aperture. The mount further has means for mounting the semiconductor device to the substrate in an aligned position. Some embodiments include a method of making and/or using such a mount. | 06-04-2009 |
| 20090152699 | PACKAGING APPARATUS OF TERAHERTZ DEVICE - There is provided a packaging apparatus of a terahertz device, the apparatus including: a terahertz device having an active region at which terahertz wave is radiated or detected; a device substrate mounting the terahertz device whose active region is positioned at an opening region formed at the center of the device substrate, and electrically connecting the terahertz device and an external terminal to each other; a ball lens block arranged and fixed to an upper part of the terahertz device; and upper and lower cases receiving the device substrate mounted with the terahertz device therein and opening region vertical upper and lower portions of the active region of the terahertz device. | 06-18-2009 |
| 20090160041 | Substrate package structure - A substrate package structure is disclosed herein. The substrate package structure includes a packaging substrate provided with a plurality of chip carriers set at one surface of the packaging substrate, wherein those chip carriers are formed by intersecting a plurality of cutting streets; a plurality of through holes set at those cutting streets and set around those chip carriers; and a plurality of molding areas set on another surface of the packaging substrate and opposite to those chip carriers, wherein those molding areas are adjacent to those through holes. Hence, those through holes may be flowed by the molding compound to form a plurality of molding bumps around those chip carriers so as to improve the crack problem of the chip and/or the substrate. | 06-25-2009 |
| 20090166831 | SENSOR SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - This invention provides a sensor semiconductor package and a method for fabricating the same. The method includes: mounting on a substrate a sensor chip having a sensor area; electrically connecting the sensor chip and the substrate by means of bonding wires; forming on a transparent member an adhesive layer with an opening corresponding in position to the sensor area; and mounting the transparent member on the substrate via the adhesive layer while heating the substrate, such that the adhesive layer melts, to thereby encapsulate the periphery of the sensor chip and the bonding wires while exposing the sensor area from the adhesive layer. Thus, the sensor area is sealed by the transparent member cooperative with the adhesive layer, making the sensor semiconductor package thus-obtained dam-free, light, thin, and compact, and incurs low process costs. Also, the product reliability is enhanced since the bonding wires are encapsulated by the adhesive layer without severing concern. | 07-02-2009 |
| 20090166832 | STACKED FLIP-ASSEMBLED SEMICONDUCTOR CHIPS EMBEDDED IN THIN HYBRID SUBSTRATE - A semiconductor system having a substrate ( | 07-02-2009 |
| 20090184408 | Semiconductor device for fingerprint recognition - A semiconductor device is disclosed that performs fingerprint recognition on the electrostatic-capacity principle. A finger sweeping across a fingerprint recognition area of a semiconductor chip provides positive fingerprint recognition operations with improved reliability. | 07-23-2009 |
| 20090218668 | Double-side mountable MEMS package - The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate. | 09-03-2009 |
| 20090243064 | Method and Apparatus For a Package Having Multiple Stacked Die - A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device is mounted to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. A wirebond or other electrical interconnect is formed between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond or other electrical interconnect passes through the window of the substrate. An encapsulant is deposited over the first, second, and third semiconductor devices. | 10-01-2009 |
| 20090283887 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device of the present invention includes a semiconductor chip ( | 11-19-2009 |
| 20090294940 | SEMICONDUCTOR LIGHT EMITTING DEVICE - The semiconductor device includes a support substrate | 12-03-2009 |
| 20090302446 | SEMICONDUCTOR PACKAGE FABRICATED BY CUTTING AND MOLDING IN SMALL WINDOWS - A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced. Additionally, the encapsulant on the window molding areas is cut when singulating the substrate units so that the adhesion area of the encapsulant to the substrate strip is increased to prevent the delamination of traces and solder mask of the substrate units. | 12-10-2009 |
| 20090309202 | PACKAGE SUBSTRATE HAVING EMBEDDED SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF - A packaging substrate having a semiconductor chip embedded and a fabrication method thereof are provided. The method includes forming a semiconductor chip in a through cavity of a core board and exposing a photosensitive portion of the semiconductor chip from the through cavity; sequentially forming a first dielectric layer and a first circuit layer on the core board, the first circuit layer being electrically connected to the electrode pads of the semiconductor chip; forming a light-permeable window on the first dielectric layer to expose the photosensitive portion of the semiconductor chip and adhering a light-permeable layer onto the light-permeable window, thereby permitting light to penetrate through the light-permeable layer to reach the photosensitive portion. Therefore, when fabricated with the method, the packaging substrate dispenses with conductive wires and dams and thus can be downsized. | 12-17-2009 |
| 20090315164 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULATION - An integrated circuit package system includes: connecting a carrier and an integrated circuit mounted thereover; preforming a wire-in-film encapsulation having a cavity; pressing the wire-in-film encapsulation over the carrier and the integrated circuit with the cavity exposing a portion of the integrated circuit; and curing the wire-in-film encapsulation. | 12-24-2009 |
| 20100038764 | Package on Package Design a Combination of Laminate and Tape Substrate with Back-to-Back Die Combination - In a method and system for fabricating a semiconductor device ( | 02-18-2010 |
| 20100155917 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor element having a light receiving region or a light emitting region on which a transparent member is attached, and a plurality of electrode pads; a substrate on which the semiconductor element is provided; and a resin covering the semiconductor element and side surfaces of the transparent member. The first area corresponding to part of an upper surface of the semiconductor element, which part is covered with the resin is smaller than the second area corresponding to parts of a lower surface of the semiconductor element and a lower surface of the substrate, which parts are covered with the resin. | 06-24-2010 |
| 20100164081 | Micro-Optical Device Packaging System - According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate. | 07-01-2010 |
| 20100164082 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE - The reliability of a photosensor-type semiconductor device is enhanced. The sealing step in a manufacturing process for the semiconductor device is carried out as described below. A molding die having an upper die and a lower die is prepared and a film is arranged between the upper die and the lower die. A lead frame in which first adhesive, a semiconductor chip, second adhesive | 07-01-2010 |
| 20100219521 | WINDOW TYPE SEMICONDUCTOR PACKAGE - A window-type semiconductor package is revealed, primarily comprising a substrate with an interconnection channel, a chip on the substrate, a die-attach adhesive between the chip and the substrate, and an encapsulant filling the interconnection channel. A first solder mask formed on the top surface of the substrate has a specific pattern. The die-attach adhesive bonds the active surface of the chip to the first solder mask with the bonding pads of the chip aligned inside the interconnection channel. The first solder mask has an opening to expose the interconnection channel and further to form an indentation from the interconnection channel to expose the top surface to prevent damaging of the active surface of the chip adjacent to the edges of the interconnection channel to ensure the integrity and yield of the final products. | 09-02-2010 |
| 20100264532 | ELECTRONIC DEVICE PACKAGE - Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover. | 10-21-2010 |
| 20100283139 | Semiconductor Device Package Having Chip With Conductive Layer - The present invention relates to a semiconductor device package having a chip with a conductive layer. The semiconductor device package includes a substrate, a chip, at least one first electrical connecting element and at least one second electrical connecting element. The substrate has a first surface and a first circuit layer. The first circuit layer is disposed adjacent to the first surface. The chip is attached to the substrate and has a surface, at least one first pad, a plurality of second pads and a conductive layer. The first pad, the second pads and the conductive layer are disposed adjacent to the surface, and the conductive layer connects the second pads. | 11-11-2010 |
| 20110012248 | Method for producing a capping wafer for a sensor - A method for producing a capping wafer for a sensor having at least one cap includes: production of a contacting via extending through the wafer, and, temporally subsequent thereto, filling of the contacting via with an electrically conductive material. | 01-20-2011 |
| 20110062571 | OPTICAL DEVICE, INTEGRATED CIRCUIT DEVICE AND SYSTEM - An optical device for an integrated circuit device, includes a laminated substrate having a through-passage and a tubular frame in which an optical lens is mounted, the tubular frame having an end part inserted or integrated in the through-passage of the laminated substrate. A integrated circuit device includes an optical device and an integrated circuit die carried by the laminated substrate and having an active optical area placed in front of the optical lens. | 03-17-2011 |
| 20110062572 | SELF-ALIGNED SILICON CARRIER FOR OPTICAL DEVICE SUPPORTING WAFER SCALE METHODS - Disclosed is a carrier assembly for and a method of manufacturing an optical device. The method comprises providing a silicon substrate; attaching a number of optical dies on the silicon substrate to form an optical device carrier assembly; providing a corresponding number of through holes in the silicon substrate to permit the passage of light therethrough and further providing guide holes in the silicon substrate to present means for passive alignment of an external optical connection; and dicing the optical device carrier assembly to form individual optical devices. Preferably, the step of attaching a number of optical dies comprises using self-alignment of solder bumps using gaseous flux, the through holes are dry etched into the silicon substrate, and/or the volume between the optical die and silicon substrate is filled with a transparent polymer. Preferably, the transparent polymer is silicone rubber or epoxy. Preferably, the optical dies have a polymer mass to assist the heat transfer to the silicon substrate. | 03-17-2011 |
| 20110062573 | Double-side mountable MEMS package - The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate. | 03-17-2011 |
| 20110147904 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS USING THE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - This invention provides a semiconductor device with increased moisture resistance. The semiconductor device includes: a semiconductor substrate; an optical element provided in a front surface of the semiconductor substrate; a light-transmissive substrate provided above the front surface of the semiconductor substrate; an adhesive layer provided between the front surface of the semiconductor substrate and a front surface of the light-transmissive substrate, and fixing the light-transmissive substrate to the semiconductor substrate; and an insulating film covering a lateral surface of said adhesive layer which is not in contact with the light-transmissive substrate and the semiconductor substrate. | 06-23-2011 |
| 20110147905 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor element, upper through-hole conductor portions and lower through-hole conductor portions are formed such that pore size A of the joint surface of the upper through-hole conductor portion and the lower through-hole conductor portion is smaller than pore size B of the upper through-hole conductor portion on the major surface of the semiconductor element and pore size C of the lower through-hole conductor portion on the other surface of the semiconductor element. Further, electrode portions are formed respectively on the top surfaces of the upper through-hole conductor portions and protrusions | 06-23-2011 |
| 20110272795 | SEMICONDUCTOR DEVICE PACKAGING STRUCTURE AND PACKAGING METHOD - Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained. | 11-10-2011 |
| 20110285003 | OPTICAL DEVICE AND METHOD FOR MANUFACTURING OPTICAL DEVICE, AND CAMERA MODULE AND ENDOSCOPE MODULE EQUIPPED WITH OPTICAL DEVICE - An optical device is equipped with a light receiving region | 11-24-2011 |
| 20110291255 | CARRIER FOR CHIP PACKAGES - A carrier for holding a plurality of chip packages and a carrier assembly are provided, wherein the chip package has a central area without solder balls and a peripheral area with solder balls formed thereon. The carrier includes a tray component and a plurality of supports disposed on the tray component, wherein each support holds the central area of a respective chip package. The carrier assembly is formed by stacking a plurality of the carriers through a plurality of peripheral projections disposed at a periphery of each tray component, wherein each peripheral projection has a pin formed thereon and a hole formed thereunder. | 12-01-2011 |
| 20110304034 | SEMICONDUCTOR WAFER BONDING PRODUCT, METHOD OF MANUFACTURING SEMICONDUCTOR WAFER BONDING PRODUCT AND SEMICONDUCTOR DEVICE - A semiconductor wafer bonding product according to the present invention includes: a semiconductor wafer; a transparent substrate provided at a side of a functional surface of the semiconductor wafer; a spacer provided between the semiconductor wafer and the transparent substrate; and a bonded portion continuously provided along a periphery of the semiconductor wafer, the transparent substrate being bonded to the semiconductor wafer through the bonded portion. It is preferred that a minimum width of the bonded portion is 50 μm or more. | 12-15-2011 |
| 20120007226 | SYSTEM-IN-A-PACKAGE BASED FLASH MEMORY CARD - A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package. | 01-12-2012 |
| 20120012994 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE - A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer. | 01-19-2012 |
| 20120025362 | Reinforced Wafer-Level Molding to Reduce Warpage - A method for forming an electrical package to reduce warpage. The method includes providing a wafer and coupling a die thereto. A mold compound material is applied to the wafer such that the mold compound material surrounds the die. The method further includes applying a reinforcing material to the mold compound material. The mold compound material is thereby disposed between the wafer and the reinforcing material. | 02-02-2012 |
| 20120025363 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component. | 02-02-2012 |
| 20120068324 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least two or more groups of external connection terminals to which a substrate that drives a bare chip by inputting a signal from an external apparatus to the bare chip is electrically connected, the at least two or more groups of external connection terminals being formed outside an image area of the bare chip, wherein at least one group of terminals constitutes a first group of terminals, another group of terminals constitutes a second group of terminals, the first group of terminals doubles as the second group of terminals, and a substrate for inspection doubling as a substrate for mounting is electrically connected to the first group of terminals. | 03-22-2012 |
| 20120126386 | ELECTRONIC DEVICES - Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover. | 05-24-2012 |
| 20120187553 | METHOD OF MANUFACTURING SEMICONDUCTOR WAFER BONDING PRODUCT, SEMICONDUCTOR WAFER BONDING PRODUCT AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor wafer bonding product according to the present invention includes: a step of preparing a spacer formation film including a support base having a sheet-like shape and a spacer formation layer provided on the support base and having photosensitivity; a step of attaching the spacer formation layer to a semiconductor wafer having one surface from a side of the one surface; a step of forming a spacer by subjecting the spacer formation layer to exposure and development to be patterned and removing the support base; and a step of bonding a transparent substrate to a region of the spacer where the removed support base was provided so that transparent substrate is included within the region. This makes it possible to manufacture a semiconductor wafer bonding product in which the semiconductor wafer and the transparent substrate are bonded together through the spacer uniformly and reliably. | 07-26-2012 |
| 20120280381 | Window Interposed Die Packaging - A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die, a window substrate being an inorganic substrate comprising at least one window-shaped cavity for mounting the at least one semiconductor die, the window substrate having interconnect structures. Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device. The invention also relates to a method of manufacturing such a semiconductor device. | 11-08-2012 |
| 20120292756 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A semiconductor device has a semiconductor die attached to a second side of a heat spreader plate. The second side of the heat spreader plate is attached to a first side of a substrate with thermal balls. The substrate includes a window within which the semiconductor die is arranged and there is a gap between an edge of the die and an edge of the window. The die is electrically connected to a second side of the substrate such as with wires. The die, electrical connections to the substrate, and thermal balls are then encapsulated with a mold compound. Connection bumps may be attached to the second side of the substrate for device I/Os. Heat generated by the die during operation dissipates along the thermal path from the backside of the semiconductor die through the heat spreader plate. | 11-22-2012 |
| 20120326290 | SILICON CARRIER OPTOELECTRONIC PACKAGING - An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board. | 12-27-2012 |
| 20130134570 | Sealed Body, Light-Emitting Module and Method of Manufacturing Sealed Body - A sealed body in which sealing is uniformly performed is provided. A light-emitting module in which sealing is uniformly performed is provided. A method of manufacturing the sealed body in which sealing is uniformly performed is provided. The sealed body comprises a first substrate alternately provided with a high-reflectivity region with respect to the energy ray and a low-reflectivity region with respect to the energy ray so as to overlap with a sealant surrounding a sealed object, and a second substrate capable of transmitting the energy ray. The sealed object is sealed between the first substrate and the second substrate by heating the sealant with irradiation with the energy ray through the second substrate. | 05-30-2013 |
| 20140042606 | Low Loss Nano-aperture - Low loss optical apertures are provided. A silicon intermediate layer sandwiched between a metal aperture layer and a dielectric layer has been found to offer a good combination of low optical loss combined with superior mechanical properties. | 02-13-2014 |
| 20140197528 | OPTICAL SEMICONDUCTOR APPARATUS - An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded. The upper surface of the first portion is positioned lower than an upper surface of the third portion. The second portion has a thin-walled portion positioned to surround the first portion, the thin-walled portion having a thickness thinner than that of the first portion as well as thinner than that of the third portion. | 07-17-2014 |
| 20140264809 | BACKPLATE INTERCONNECT WITH INTEGRATED PASSIVES - This disclosure provides systems, methods and apparatus for manufacturing display devices having electronic components mounted within a display device package. In one aspect, the electronic component connects to the exterior of the display device through pads that run below a seal that holds a substrate and a backplate of the display device together. In another aspect the electronic components also connect to an electromechanical device within the display device, as well as connecting to pads that are external to the display device. | 09-18-2014 |
| 20140291829 | ADHESIVE BONDING TECHNIQUE FOR USE WITH CAPACITIVE MICRO-SENSORS - A micro-sensor device that includes a passivation-protected ASIC module and a micro-sensor module bonded to a patterned cap provides protection for signal conditioning circuitry while allowing one or more sensing elements in the micro-sensor module to be exposed to an ambient environment. According to a method of fabricating the micro-sensor device, the patterned cap can be bonded to the micro-sensor module using a planarizing adhesive that is chemically compatible with the sensing elements. In one embodiment, the adhesive material is the same material used for the dielectric active elements, for example, a photo-sensitive polyimide film. | 10-02-2014 |
| 20150048492 | PCB Based RF-Power Package Window Frame - A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate. | 02-19-2015 |
| 20150102478 | SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING SEMICONDUCTOR PACKAGE - Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package. | 04-16-2015 |
| 20150380330 | PACKAGE SUBSTRATE, PACKAGE, AND ELECTRONIC DEVICE - A package substrate includes a recessed part and a step part disposed at a periphery thereof, and a lid body is bonded to the step part to cover the recessed part via a bonding layer containing a glass and an electromagnetic wave absorbent material. A ratio (w | 12-31-2015 |
| 20160093544 | Packaging of Semiconductor Devices - A packaged semiconductor device comprising a stack including a die comprising a functional circuit, and a cap which is wafer bonded to the die for protecting the functional circuit as well as a mold component for packaging the stack. At least the cap and/or the die comprises at least one groove at least partially in contact with the mold component, for increasing adhesion of the mold component to the stack. A corresponding method for manufacturing such a packaged device also is described. | 03-31-2016 |
| 20170236761 | HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING | 08-17-2017 |
