Entries |
Document | Title | Date |
20080197462 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided with a package main body including a base portion configured by joining thin plates integrally, and a semiconductor device accommodating portion provided on one surface of the base portion, electric terminals electrically connected to a semiconductor device in the accommodating portion and exposed to an outer surface of the accommodating portion, and a heat high-transfer element including at least one layer-like member provided in the base portion. The layer-like member is configured independent of the base portion by a material having a thermal conductivity higher than that of the base portion, and extends from a position corresponding to a heat-generation site of the semiconductor device to a position in an outside of the heat-generation site corresponding position. | 08-21-2008 |
20080203550 | Component, Power Component, Apparatus, Method Of Manufacturing A Component, And Method Of Manufacturing A Power Semiconductor Component - A component has a device applied to a device carrier, a first conducting layer grown onto the device and onto the device carrier, and an insulating material applied to the first conducting layer such that only a portion of the first conducting layer is covered. | 08-28-2008 |
20080224285 | Power module having stacked flip-chip and method of fabricating the power module - Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. | 09-18-2008 |
20080224286 | Vertically mountable semiconductor device package - A semiconductor package that includes a die with electrodes on opposite surfaces thereof and respective conductive clip electrically and mechanically coupled to the electrode and configured for vertical mounting of the package. | 09-18-2008 |
20080230880 | Leadframe Array with Riveted Heat Sinks - The invention provides improved rivet and heat sink arrangements in leadframes and IC packages. The invention discloses a semiconductor device leadframe array with numerous leadframes having integrated circuit sites provided for receiving individual integrated circuit chips. Support strips are arranged adjacent to and supporting the integrated circuit sites in an array of one or more rows. Package areas provided each include one or integrated circuit site for ultimate encapsulation in an integrated circuit package. Rivet points are located on the support strips outside of the package areas. An array of heat sinks having corresponding rivet points is riveted to the leadframe array to complete the assembly. Alternative embodiments of the invention provide apparatus and methods for the assembly of an integrated circuit package with a leadframe having an operably coupled integrated circuit chip. One or more support strips supporting the leadframe include rivet points adjacent to the integrated circuit mounting site. A heat sink is secured in coplanar contact with the leadframe using rivets secured in the rivet points of the leadframe and corresponding rivet points in the heat sink. Individual package assemblies made using the invention provide heat sinks secured in contact with the leadframe, integrated circuit, or both, without the necessity for the inclusion of glues, thermal compounds, welds, tapes, or rivets within the package assembly. | 09-25-2008 |
20080237817 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK SPACER STRUCTURES - An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit die over the package substrate wherein the integrated circuit die has a mount height; attaching an attachment structure having a height substantially the same as the mount height and planar dimensions predetermined to fit adjacent the integrated circuit die and over the package substrate; and attaching a heat dissipation device over the integrated circuit die and the attachment structure. | 10-02-2008 |
20080246130 | Semiconductor Package Structure Having Enhanced Thermal Dissipation Characteristics - In an exemplary embodiment, a packaged device having enhanced thermal dissipation characteristics includes a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged device further includes a conductive clip for coupling the major current carrying electrode to a next level of assembly, and a heat spreader device formed on or integral with the conductive clip. A portion of the heat spreader device may be optionally exposed. | 10-09-2008 |
20080246131 | CHIP PACKAGE STRUCTURE - A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components. | 10-09-2008 |
20080258275 | CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES - Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. | 10-23-2008 |
20080283983 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A portion of a frame body is fixed on a surface of a heat-radiating plate, and on frame body, a semiconductor chip is die-bonded. Next, a prescribed electrode of semiconductor chip and corresponding lead terminal and the like are electrically connected by a prescribed wire. Next, the lead frame is set in a metal mold such that the semiconductor chip is covered with resin from above the semiconductor chip. Thermoplastic resin is introduced into the metal mold, and semiconductor chip and the like are sealed. By taking out the resulting body from the metal mold, a semiconductor is formed. Thus, a semiconductor device can be provided with reduced manufacturing cost. | 11-20-2008 |
20080283984 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a leadframe, a die, a solder layer and several connecting components. The leadframe includes a heat dissipation pad and several leads. The heat dissipation pad is disposed in a substantial center of the leadframe. The leads are surrounding the heat dissipation pad. The die having an active surface is disposed on the leadframe. The solder layer is disposed between the active surface and the heat dissipation pad. The connecting components are disposed between the active surface and the leads. The die is electrically connected to the leadframe through the solder layer and the connecting components. | 11-20-2008 |
20080290484 | Leadframe Strip and Mold Apparatus for an Electronic Component and Method of Encapsulating an Electronic Component - A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are molded at essentially the same time to produce a plastic housing for a package in each component position. The central portion of the first support bars remains outside of the plastic housing of the two packages. | 11-27-2008 |
20080303124 | Lead frame-BGA package with enhanced thermal performance and I/O counts - Methods and apparatus for integrated circuit (IC) packages with improved thermal performance and input/output capabilities are described. An integrated circuit (IC) package includes a leadframe, an IC die, a substrate having opposing first and second surfaces, a first wirebond, and a second wirebond. The leadframe includes a die attach pad having opposing first and second surfaces and a plurality of leads that emanate in an outward direction from the die attach pad. The IC die is coupled to the first surface of the die attach pad. The substrate is coupled to the die attach pad. Contact pads on the first surface of the substrate are electrically connected to bond fingers on the second surface of the substrate. The first wirebond couples a first bond pad on a first surface of the IC die to a bond finger on the second surface of the substrate. The second wirebond couples a second bond pad on the first surface of the IC die to a lead of the plurality of leads. | 12-11-2008 |
20080315379 | Semiconductor packages including thermal stress buffers and methods of manufacturing the same - Provided is a semiconductor package and method of manufacturing the same. The semiconductor package may include a semiconductor chip, an encapsulant encapsulating the semiconductor chip, a lead unit, and a partially encapsulated by the encapsulating thermal stress buffer which absorbs thermal stress of the semiconductor chip or the encapsulant. | 12-25-2008 |
20090001532 | Plastic-Encapsulated Semiconductor Device with an Exposed Radiator at the Top and Manufacture Thereof - A plastic-encapsulated semiconductor device is provided which comprises a plastic-encapsulant | 01-01-2009 |
20090008754 | RESIN-SEALED SEMICONDUCTOR DEVICE, LEADFRAME WITH DIE PADS, AND MANUFACTURING METHOD FOR LEADFRAME WITH DIE PADS - A resin-sealed semiconductor device with built-in heat sink prevents internal bulging and cracking caused by exfoliation of a semiconductor element from the heat sink when the vapor pressure of moisture absorbed into a gap between the semiconductor element and the heat sink rises during mounting of the semiconductor device to a printed circuit board using lead-free solder. By providing a plurality of separated die pads ( | 01-08-2009 |
20090039482 | Package Including a Microprocessor & Fourth Level Cache - A method, apparatus and system with a package including an integrated circuit disposed between die including a microprocessor and a die including a fourth level cache. | 02-12-2009 |
20090039483 | HEAT SLUG AND SEMICONDUCTOR PACKAGE - A heat slug includes a heat spreading member and a supporting member. The supporting member extends outwardly from the edge of the heat spreading member. The tips of the supporting member are formed with a plurality of contact portions, wherein each said contact portion has a bottom face inclined to the surface of the chip carrier at an angle of more than 5 degrees. The present invention further provides a semiconductor package. | 02-12-2009 |
20090045492 | LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE LEAD FRAME, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A lead frame is provided which can prevent a short circuit between wires and the ends of adjacent leads, the short circuit being caused by wire sweep during the injection of molding resin, in a configuration where the electrodes of a semiconductor chip and the leads disposed around the semiconductor chip. The lead having sides substantially perpendicular to the direction of a resin flow has an end whose upstream side relative to the resin flow is constricted. | 02-19-2009 |
20090051018 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second terminal on the top surface of the die, and a third terminal on the bottom surface of the die. The method includes attaching a first portion of a leadframe structure to the first terminal of the semiconductor die. The method further includes attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink. Other embodiments are described and claimed. | 02-26-2009 |
20090057853 | Semiconductor power module with flexible circuit leadframe - A semiconductor power module includes a semiconductor chip thermally interfaced to a ceramic substrate and a leadframe defined by a flexible circuit disposed intermediate the chip and the ceramic substrate. The flexible circuit includes a conductor layer that is selectively encased in an insulated jacket to ensure adequate electrical insulation between the conductor layer and adjacent conductive surfaces. Preferably, the module is constructed for double side cooling by sandwiching the chip between a pair of ceramic substrates and providing intermediate flexible circuit leadframes on both sides of the chip for electrically accessing the chip terminals. | 03-05-2009 |
20090072362 | THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE - A semiconductor package includes a semiconductor device | 03-19-2009 |
20090085180 | Packaging carrier with high heat dissipation and method for manufacturing the same - The present invention relates a packaging carrier with high heat dissipation for packaging a chip, comprising: a carrier body, an interfacial metal layer, at least one diamond-like carbon thin film, a plated layer, and an electrode layer. Herein, the packaging carrier further comprises through holes. The present invention further discloses a method for manufacturing the aforementioned packaging carrier, comprising: providing a carrier body; forming an interfacial metal layer on the upper surface of the carrier body; forming a diamond-like carbon thin film on the interfacial metal layer; forming a plated layer on the diamond-like carbon thin film; forming an electrode layer on the lower surface of the carrier body; and forming through holes extending through all or part of the aforementioned elements. The present invention uses a diamond-like carbon thin film and through holes for heat dissipation in three dimensions to improve heat dissipation of an electronic device. | 04-02-2009 |
20090091010 | WIRELESS SEMICONDUCTOR PACKAGE FOR EFFICIENT HEAT DISSIPATION - Disclosed in this specification is a wireless semiconductor package with multiple dies, at least two of which are attached to a thermally and electrically conductive heat sink. The package provides an efficient means for dissipating heat. | 04-09-2009 |
20090091011 | SEMICONDUCTOR DEVICE HAVING INTERCONNECTED CONTACT GROUPS - The present invention is related to a method of producing a semiconductor device and the resulting device. The method is suitable in the first place for producing high power devices, such as High Electron Mobility Transistors (HEMT), in particular HEMT-devices with multiples source-gate-drain groups or multiple base bipolar transistors. According to the method, the interconnect between the source contacts is not produced by air bridge structures, but by etching vias through the semiconductor layer directly to the ohmic contacts and applying a contact layer on the backside of the device. | 04-09-2009 |
20090102030 | INTEGRATED CIRCUIT PACKAGE WITH ETCHED LEADFRAME FOR PACKAGE-ON-PACKAGE INTERCONNECTS - Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package. | 04-23-2009 |
20090108423 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing hydrocarbon coating disposed over at least the lead ends of the leadframe, where the hydrocarbon coating is free of metal particles. | 04-30-2009 |
20090115037 | INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SINK - An IC package and methods for making the same are described. The IC package includes a die and a heat sink that is attached to the back surface of the die with a thermal interface material layer. The heat sink includes a base and a partition. The partition extends around the periphery of the base and is offset from the outer edge of the base such that a ledge region is formed that surrounds the periphery of the base. The inner surfaces of the partition define an inner region that includes heat dissipation structures. A molding material encapsulates at least portions of the die and the ledge region around the periphery of the heat sink while leaving the inner region of the heat sink unencapsulated by molding material and exposed. The molding material covering the ledge region provides a locking feature that secures the heat sink in the package. | 05-07-2009 |
20090115038 | Semiconductor Packages and Methods of Fabricating the Same - Provided are semiconductor packages and methods of fabricating the same. An exemplary semiconductor package includes a die pad including a dimple filled with an insulating material in an upper surface or a lower surface thereof. A semiconductor chip is mounted on the upper surface of the first die pad. A package body encapsulates the first die pad and the first semiconductor chip and includes a pinhole. A bottom surface of the pinhole terminates at the insulating material. | 05-07-2009 |
20090127680 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT - A multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die. | 05-21-2009 |
20090127681 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first die-pad on which a semiconductor chip is mounted on a bottom surface of the first die-pad, a support plate disposed adjacent to a lateral surface of the first die-pad, a support prop protruding from the support plate, and supporting the first die-pad, and a package body that encapsulates the first die-pad, the semiconductor chip, and the support plate. | 05-21-2009 |
20090140402 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method includes: mounting a plurality of semiconductor elements on a substrate having wirings; connecting electrically electrodes of the semiconductor elements and the wirings; sealing the semiconductor elements with a resin, which is carried out by bringing a thermal conductor having a concavity and the substrate to be in contact with each other so that the semiconductor elements are positioned within the concavity and by filling the concavity with the resin; and separating respective semiconductor elements | 06-04-2009 |
20090152695 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor chip and a leadframe assembly. The heatsink also has a back surface from which a plurality of fins extend. The leadframe assembly includes a leadframe having leadframe leads extending from opposing sides of the leadframe to a central area of the leadframe. A liquid crystal polymer is disposed in a ring-shaped pattern on the leadframe leads. The liquid-crystal polymer is partially cured. The leadframe assembly is mounted on the front surface of the heatsink and the liquid crystal polymer is further cured to form a packaging assembly, which is then singulated into packaging substrates. | 06-18-2009 |
20090174044 | Multi-chip package - A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead frame or a heat sink and the semiconductor chips disposed thereon. | 07-09-2009 |
20090194856 | MOLDED PACKAGE ASSEMBLY - A semiconductor die package is disclosed. The semiconductor die package is suitable for mounting on a circuit substrate such as a circuit board. The semiconductor die package comprises a leadframe structure and a semiconductor die coupled to the leadframe structure. A plurality of first conductive structures is attached to the semiconductor die, and a plurality of second conductive structures is attached to the plurality of first conductive structures. The semiconductor die package also comprises a molding material that covers at least portions of plurality of first conductive structures, the leadframe structure, and the semiconductor die. | 08-06-2009 |
20090236705 | APPARATUS AND METHOD FOR SERIES CONNECTION OF TWO DIE OR CHIPS IN SINGLE ELECTRONICS PACKAGE - An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions. Alternatively, it can be by adding an electrically isolating coating on the non-active area of the P-side of a semiconductor device to allow it to be mounted P side down on an electrically conductive substrate or mounting location without modification to the substrate or lead frame. | 09-24-2009 |
20090236706 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively. | 09-24-2009 |
20090236707 | ELECTRONIC DEVICES WITH ENHANCED HEAT SPREADING - An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer. | 09-24-2009 |
20090236708 | SEMICONDUCTOR PACKAGE HAVING A BRIDGED PLATE INTERCONNECTION - A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metallized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metallized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions. | 09-24-2009 |
20090283879 | SEMICONDUCTOR DEVICE AND METHOD - A chip carrier includes first, second and third layers with the second layer situated between the first and third layers. The first and third layers are formed of a first material and the second layer is formed of a second material. The second layer has a plurality of holes extending therethrough and the first material fills the holes. | 11-19-2009 |
20090283880 | Semiconductor Chip Package Assembly with Deflection- Resistant Leadfingers - The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the invention includes a semiconductor package leadframe with a chip mounting surface for receiving a semiconductor chip and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebond, and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion at its proximal end for increasing the clearance between the leadfinger and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface. Preferred embodiments of the invention further include a semiconductor chip affixed to the mounting surface and a plurality of bondwires operably coupling bond pads of the chip to the offset portions of the proximal ends of individual leadfingers. | 11-19-2009 |
20090294936 | FOUR MOSFET FULL BRIDGE MODULE - A molded, leadless packaged semiconductor multichip module includes | 12-03-2009 |
20090294937 | TWO-WAY HEAT EXTRACTION FROM PACKAGED SEMICONDUCTOR CHIPS - One embodiment of the invention is a semiconductor device ( | 12-03-2009 |
20090302444 | RESIN SEALED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A resin sealed semiconductor device includes a first semiconductor switching device having a first emitter terminal and a first collector terminal bonded to its top and bottom surfaces respectively, a second semiconductor switching device having a second emitter terminal and a second collector terminal bonded to its top and bottom surfaces respectively, a first heat sink directly or indirectly bonded to the first collector terminal, a second heat sink directly or indirectly bonded to the second collector terminal, and a molding resin integrally covering the first and second semiconductor switching devices. The first and second heat sinks are exposed from the molding resin. The first emitter terminal faces and is spaced apart from the second emitter terminal. | 12-10-2009 |
20090321901 | THERMALLY BALANCED HEAT SINKS - According to example embodiments, a device configured to dissipate heat from a first chip and a second chip on a multi-chip package includes a primary heat sink configured to contact an upper surface of the first chip, a secondary heat sink configured to contact an upper surface of the second chip, the secondary heat sink disposed within the primary heat sink and movable in relation to the primary heat sink, and a thermally conductive substance disposed in contact with the primary heat sink and the secondary heat sink. | 12-31-2009 |
20100019360 | INTEGRATED CIRCUIT PACKAGE WITH ETCHED LEADFRAME FOR PACKAGE-ON-PACKAGE INTERCONNECTS - Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package. | 01-28-2010 |
20100019361 | Multi Lead Frame Power Package - According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates thermal energy. The first lead frame is disposed at least partially within the mold compound and is operable to facilitate transmission of a signal. The second lead frame is disposed at least partially within the compound, at least partially separated from the first lead frame, and is operable to facilitate a dissipation of thermal energy. | 01-28-2010 |
20100038758 | SEMICONDUCTOR MODULE WITH TWO COOLING SURFACES AND METHOD - A semiconductor module with two cooling surfaces and method. One embodiment includes a first carrier with a first cooling surface and a second carrier with a second cooling surface. The first cooling surface is arranged in a first plane, the second cooling surface is arranged in a second plane, at an angle different from 0° relative to the first plane. | 02-18-2010 |
20100044841 | SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a chip attached to the carrier, a sealant vapor deposited over the chip and the carrier, and encapsulation material deposited over the sealed chip and the sealed carrier. | 02-25-2010 |
20100059870 | CHIP PACKAGE STRUCTURE - A chip package structure including a substrate, at least one chip, a plurality of leads, a heat dissipation device, a molding compound, and at least one insulating sheet is provided. The chip is disposed on the substrate. The leads are electrically connected to the substrate. The molding compound having a top surface encapsulates the chip, the substrate, and a portion of the leads. The heat dissipation device is disposed on the top surface of the molding compound. The insulating sheet disposed between the heat dissipation device and at least one of the leads has a bending line dividing the insulating sheet into a main body disposed on the molding compound and a bending portion extending from the main body. | 03-11-2010 |
20100065950 | Leaded semiconductor power module with direct bonding and double sided cooling - A leaded semiconductor power module includes a first heatsink, an electrically insulated substrate thermally coupled to the first heatsink, one or more semiconductor chips, a leadframe substrate, and a second heatsink thermally coupled to the leadframe substrate, the assembly being overmolded with an encapsulant to expose the first heatsink, the second heatsink and peripheral terminals of the leadframe substrate. The semiconductor chips are electrically and structurally coupled to both the insulated substrate and the leadframe substrate, and conductive spacers electrically and structurally couple the insulated substrate to the leadframe substrate. | 03-18-2010 |
20100072586 | QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed. | 03-25-2010 |
20100072587 | IC SOCKET HAVING HEAT DISSIPATION FUNCTION - It is an object of the present invention to provide an IC socket that has a configuration to promote heat dissipation from an IC device in a simple configuration, and prevent overheating of the IC device under test. Contact pins | 03-25-2010 |
20100123227 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, includes having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface. | 05-20-2010 |
20100127364 | SEMICONDUCTOR DEVICE AND HEAT RADIATION MEMBER - A semiconductor device includes a semiconductor element mounted on a substrate; at least one electronic part arranged around the semiconductor element; and a heat radiation member bonded to a backside of the semiconductor element by a bonding material. The heat radiation member has an isolation part extending between an outer circumference of the semiconductor element and the electronic part. | 05-27-2010 |
20100133670 | Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method - A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang. | 06-03-2010 |
20100148328 | POWER QUAD FLAT NO-LEAD SEMICONDUCTOR DIE PACKAGES WITH ISOLATED HEAT SINK FOR HIGH-VOLTAGE, HIGH-POWER APPLICATIONS, SYSTEMS USING THE SAME, AND METHODS OF MAKING THE SAME - Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the molding material of the package. The heat sink member has an electrically insulating substrate with a high breakdown voltage, and one or more conductive layers disposed on a first surface of the substrate that electrically interconnect the semiconductor to one or more leads of the leadframe. | 06-17-2010 |
20100148329 | QUAD FLAT NO LEAD (QFN) INTEGRATED CIRCUIT (IC) PACKAGE HAVING A MODIFIED PADDLE AND METHOD FOR DESIGNING THE PACKAGE - A QFN IC package is provided that has all of the advantages of the typical QFN IC package, but in addition, has a paddle that is configured to facilitate trace routing and/or via placement on the PWB or PCB on which the IC package is mounted. By configuring the paddle as necessary or desired in order to facilitate routing and/or via placement, the overall size of the PWB or PCB can be reduced without sacrificing the thermal or electrical performance advantages that the paddle provides. In addition, the reduction in the overall size of the PWB or PCB results in reduced cost. | 06-17-2010 |
20100155914 | Power Module Having Stacked Flip-Chip and Method of Fabricating the Power Module - Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. | 06-24-2010 |
20100164078 | PACKAGE ASSEMBLY FOR SEMICONDUCTOR DEVICES - Semiconductor packages and methods for making and using such semiconductor packages are described. The semiconductor packages contain a dual gauge heat sink exposed on an upper part of the package, a leadframe containing a gate lead and an exposed drain pad on a lower part of the package, and a semiconductor die containing an IC device located between the heat sink and the leadframe. The gate of the IC device is connected to the gate lead of the leadframe using a bond interconnect wire or a gate interconnect clip located and placed under the heat sink and in between the heat sink and main leadframe. Such a configuration provides both a simple design for the semiconductor package and a simple method of manufacturing. Other embodiments are described. | 07-01-2010 |
20100176498 | POWER MODULE PACKAGE HAVING EXCELLENT HEAT SINK EMISSION CAPABILITY AND METHOD FOR MANUFACTURING THE SAME - A power module package includes a power circuit element, a control circuit element, a lead frame, an aluminum oxide substrate having a heat sink and an insulation layer, and a sealing resin. The control circuit element is electrically connected with the power circuit element to control chips within the power circuit element. The lead frame has external connection terminal leads in its edge and has a first surface to which the power circuit element and the control circuit element are attached and a second surface which is used as a heat transmission path. The heat sink is a plate made of metal such as aluminum and the electrical insulation layer is formed at least on an upper surface of the heat sink and made of aluminum oxide. The electrical insulation layer may be formed over an entire surface of the heat sink. Here, the insulation layer is attached to the second surface by an adhesive, on a region below where the power circuit element is attached, to the first surface of the lead frame. In addition, the sealing resin encloses the power circuit element and the control circuit element, the lead frame, and the metal oxide substrate and exposes the external connection terminals of the lead frame. | 07-15-2010 |
20100200971 | High current capacity inner leads for semiconductor device - The invention can be used for improving performance of laser diodes, solar cells, microprocessors and other devices. The invention enables to create semiconductor devices having a great area of die, a great number of leads, a high operating current and a high heat dissipation. This is achieved by the following manner: offered leads are made of copper foil; the rigidity of the foil is decreased by means of disposing of alternating parallel narrow trenches on both sides of the foil; the offered leads are microspring; additional decreasing of rigidity can be achieved by the bending of foil along wide trenches that are created for this aim. Offered leads can be directly connected to the die. | 08-12-2010 |
20100219516 | Power management integrated circuit - An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout. | 09-02-2010 |
20100230791 | LEADFRAME PACKAGE FOR LIGHT EMITTING DIODE DEVICE - An LED leadframe package with surface tension function to enable the production of LED package with convex lens shape by using dispensing method is disclosed. The LED leadframe package of the invention is a PPA supported package house for LED packaging with metal base, four identical metal electrodes, and PPA plastic to fix the metal electrodes and the heat dissipation base together, four ring-alike structures with a sharp edge and with a tilted inner surface, and three ring-alike grooves formed between sharp edge ring-alike structures. | 09-16-2010 |
20100237479 | Lead Frame Based, Over-Molded Semiconductor Package with Integrated Through Hole Technology (THT) Heat Spreader Pin(s) and Associated Method of Manufacturing - A method and apparatus are provided for manufacturing a lead frame based, over-molded semiconductor package ( | 09-23-2010 |
20100244211 | MULTICHIP DISCRETE PACKAGE - A multichip discrete package with a leadframe having a plurality of leads and a first die attach pad (DAP), the first DAP having side portions that extend above the first DAP, a first discrete die bonded to the first DAP, at least a first wirebond which forms an electrical connections between the first discrete die and a first selected one of the plurality of leads, a metal plate attached to tops of the side portions forming a second DAP, a second discrete die bonded to the second DAP, at least a second wirebond which forms an electrical connections between the second discrete die and a second selected one of the leads; and encapsulating material formed around the first and second die and the first and second DAPs. | 09-30-2010 |
20100252918 | MULTI-DIE PACKAGE WITH IMPROVED HEAT DISSIPATION - The present invention discloses a multi-die package which facilitates heat dissipation for a high power consumption die. In the package, part of the lead frame is bent so as to be exposed at the surface of the package. On the opposite side of the exposed surface, a high power consumption die is attached. The other die with lower power consumption is not at the surface of the multi-die package. | 10-07-2010 |
20100264528 | QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed. | 10-21-2010 |
20100283134 | High Power Ceramic on Copper Package - According to an embodiment of a high power package, the package includes a copper heat sink, a ceramic lead frame and a semiconductor chip. The copper heat sink has a thermal conductivity of at least 350 W/m K. The ceramic lead frame is attached to the copper heat sink with an epoxy. The semiconductor chip is attached to the copper heat sink on the same side as the lead frame with an electrically conductive material having a melting point of about 280° C. or greater. | 11-11-2010 |
20100295160 | QUAD FLAT PACKAGE STRUCTURE HAVING EXPOSED HEAT SINK, ELECTRONIC ASSEMBLY AND MANUFACTURING METHODS THEREOF - A quad flat package (QDP) structure having an exposed heat sink is provided. The QDP structure includes a leadframe, a chip, a heat sink, an insulating layer and a molding compound. The leadframe includes a die pad and multiple leads surrounding the die pad. The chip is disposed on the die pad and electrically connected to the die pad and the leads. The heat sink has a top surface, a bottom surface opposite thereto, and a side surface connected to the top and the bottom surfaces. The die pad is disposed in a central area of the top surface of the heat sink and electrically connected to the heat sink. The molding compound encapsulates the chip, the die pad, an inner lead portion of each lead and heat sink, and exposes the bottom surface of the heat sink and an outer lead portion of each lead. | 11-25-2010 |
20100327418 | INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG - An integrated circuit package system includes a substrate having an integrated circuit die thereon; a heat slug having a tie bar, the tie bar having characteristics of singulation from an adjacent heat slug; and an encapsulant molded on the substrate, the heat slug, and the integrated circuit die includes the encapsulant which fills all of the space between the integrated circuit die and the heat slug. | 12-30-2010 |
20110001225 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method includes: mounting a plurality of semiconductor elements on a substrate having wirings; connecting electrically electrodes of the semiconductor elements and the wirings; sealing the semiconductor elements with a resin, which is carried out by bringing a thermal conductor having a concavity and the substrate to be in contact with each other so that the semiconductor elements are positioned within the concavity and by filling the concavity with the resin; and separating respective semiconductor elements | 01-06-2011 |
20110012241 | Semiconductor Chip Package - A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively. | 01-20-2011 |
20110049689 | SEMICONDUCTOR DEVICE WITH ACENE HEAT SPREADER - A semiconductor device in which an adhesion between a lead and a sealing body (mold sealing body) is improved to prevent the peering is provided. In a semiconductor device having a semiconductor chip, a plurality of leads electrically connected to the semiconductor chip and mainly made of metal and a sealing body for sealing the semiconductor chip, in order to improve the adhesion between the lead and the sealing body (mold sealing body), a material combination with good lattice matching is used as a combination of a surface material of the lead and a material of the sealing body, and the sealing body mainly made of acene is used. | 03-03-2011 |
20110068445 | CHIP PACKAGE AND PROCESS THEREOF - A chip package and a process thereof are provided. The chip package includes a lead frame, a heat sink, a chip and a molding compound. The lead frame includes a chip pad and a plurality of leads, wherein the chip pad has a first surface and a second surface opposite thereto. The heat sink has a third surface and a fourth surface opposite thereto, wherein the lead frame is disposed on the third surface of the heat sink through the second surface of the chip pad, and the fourth surface of the heat sink is exposed. The chip is disposed on the first surface of the chip pad and electrically connected to each of the chip pad and the leads. The molding compound encapsulates the chip, the chip pad, the heat sink and a portion of each of the leads. | 03-24-2011 |
20110073999 | MIXED ALLOY LEAD FRAME FOR PACKAGING POWER SEMICONDUCTOR DEVICES AND ITS FABRICATION METHOD - This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication. | 03-31-2011 |
20110084371 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A protective modular package cover has first and second fastening sections located at opposing first and second ends with one or more subassembly receiving sections disposed thereto and is configured to fasten the protective modular package cover to a core. Each fastening section has a foot surface located on a bottom surface of a fastening section and configured to make contact with the core, a mounting hole configured to receive a fastener, and a torque element. Each subassembly receiving section is configured to receive a subassembly and has a cross member formed along the underside of the protective modular package cover. Activation of the first torque element transfers a downward clamping force generated at the fastening element to a top surface of one or more subassemblies disposed in the one or more subassembly receiving sections via the cross member of each of the one or more subassembly receiving sections. | 04-14-2011 |
20110108964 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A portion of a frame body is fixed on a surface of a heat-radiating plate, and on frame body, a semiconductor chip is die-bonded. Next, a prescribed electrode of semiconductor chip and corresponding lead terminal and the like are electrically connected by a prescribed wire. Next, the lead frame is set in a metal mold such that the semiconductor chip is covered with resin from above the semiconductor chip. Thermoplastic resin is introduced into the metal mold, and semiconductor chip and the like are sealed. By taking out the resulting body from the metal mold, a semiconductor is formed. Thus, a semiconductor device can be provided with reduced manufacturing cost. | 05-12-2011 |
20110121440 | SEMICONDUCTOR DEVICE AND LEAD FRAME THEREOF - A semiconductor device includes a semiconductor element and a lead frame. The lead frame includes a first lead, a second lead, a third lead, a fourth lead, and a fifth lead placed parallel to one another. The first and second leads are placed adjoining to each other and constitute a first lead group, and the third and fourth leads are placed adjoining to each other and constitute a second lead group. The spacing between the first lead group and the fifth lead, the spacing between the second lead group and the fifth lead, and the spacing between the first lead group and the second lead group are larger than the spacing between the first lead and the second lead and the spacing between the third lead and the fourth lead. | 05-26-2011 |
20110127658 | Muti Thickness Lead Frame - A lead frame includes a lead frame | 06-02-2011 |
20110133320 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a metal plate, a power element, a lead frame having a die pad, a resin sheet having insulation properties, a control circuit that controls the power element, and a mold resin. The power element is mounted on the die pad, and the die pad is mounted on the metal plate via the resin sheet. The resin sheet is expanded including at least a lower surface of the die pad while the lower surface of the resin sheet is smaller than an surface of the metal plate, and the control circuit is arranged in a region on the metal plate, which region is other than the region where the power element is arranged. | 06-09-2011 |
20110156226 | INTERPOSER AND SEMICONDUCTOR DEVICE - An interposer and a semiconductor device including the interposer are provided, which can prevent thermal warpage of an insulative substrate thereof. The interposer is provided with a semiconductor chip in a semiconductor device andmay be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad. | 06-30-2011 |
20110163428 | SEMICONDUCTOR PACKAGES WITH EMBEDDED HEAT SINK - Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a leadframe having an array of holes with a layout corresponding to the land pad array of the package, wherein the holes contain a thermally-conductive dielectric material with a via therein containing an electrically conductive material. The electrically conductive materials can extend past the bottom of the leadframe to form the land pad array of the packages. With such a configuration, the leadframe can act as an embedded heat sink in the package and there is no need to mount an additional heat sink to the package for thermal dissipation, allowing a thinner package to be manufactured. With such a configuration, the semiconductor packages have a full land pad array, providing a smaller footprint and a higher I/O capacity. Other embodiments are also described. | 07-07-2011 |
20110163429 | Semiconductor Chip Package Assembly with Deflection-Resistant Leadfingers - The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the invention includes a semiconductor package leadframe with a chip mounting surface for receiving a semiconductor chip and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebond, and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion at its proximal end for increasing the clearance between the leadfinger and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface. Preferred embodiments of the invention further include a semiconductor chip affixed to the mounting surface and a plurality of bondwires operably coupling bond pads of the chip to the offset portions of the proximal ends of individual leadfingers. | 07-07-2011 |
20110169150 | Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof - A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity. | 07-14-2011 |
20110175212 | DUAL DIE SEMICONDUCTOR PACKAGE - A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die. The electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections. Also, at least part of a base surface of the lead frame flag directly under the second semiconductor die is left exposed by the package body and provides a heat sink. | 07-21-2011 |
20110175213 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate. | 07-21-2011 |
20110180915 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device includes a heat sink, a substrate mounted on the heat sink, a coating layer formed on the substrate, a lead frame fixed to the heat sink, and a mold resin sealing the substrate and the lead frame. The coating layer is made of one of a polyimide-based resin and a polyamideimide-based resin. The lead frame has a fixing terminal fixed to the heat sink through an adhesive layer. The adhesive layer is made of the same material as the coating layer. | 07-28-2011 |
20110198741 | Integrated Circuit Package with Enlarged Die Paddle - An integrated circuit package system having a body with a top surface, a bottom surface, and a plurality of side surfaces has a leadframe and encapsulating material that encapsulates at least a portion of the leadframe. The leadframe and encapsulating material are part of the body. The leadframe has a die paddle for supporting a die, and a plurality of leads spaced from the die paddle. The encapsulating material thus also separates the die paddle from the plurality of leads. At least a first portion of the die paddle is exposed to the top surface, while at least a second portion of the die paddle is exposed to the bottom surface. | 08-18-2011 |
20110204500 | POWER DEVICE PACKAGES HAVING THERMAL ELECTRIC MODULES USING PELTIER EFFECT AND METHODS OF FABRICATING THE SAME - Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module. | 08-25-2011 |
20110221048 | Package Having Spaced Apart Heat Sink - An integrated circuit (IC) package that includes a lead frame, and a die affixed to a first surface of a pad of the lead frame. The die is wire bonded to the lead frame. The package includes a heat sink spaced apart from a second surface of the pad, where the second surface opposes the first surface. Molding compound encapsulates the lead frame and the die. The molding compound is disposed between the heat sink and the second surface of the pad and is enabled access between the heat sink and the second surface through protruding features disposed on the heat sink, the second surface, and/or some combination of the two. | 09-15-2011 |
20110227206 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed; and attaching a base substrate connector to the base substrate directly below the leadframe pillar. | 09-22-2011 |
20110278706 | Power Electronic Device Package - A power electronic device package comprising a base member, a device layer, multiple leads, and an encapsulant is provided. The base member is thermally conductive for heat dissipation. The device layer comprises one or more power electronic devices mounted on the base member. The power electronic devices are selectively electrically connected to each other and to the base member to form an internal electronic circuit. The leads extend outwardly from the base member and are electrically connected to the internal electronic circuit. The encapsulant encases the internal electronic circuit, a portion of the base member, and a portion of the leads. The power electronic device package is configured as a transfer molded power module with multiple leads and increased power handling capability. In an embodiment, the base member is electrically conductive to operate as an electrical terminal. The base member may also be isolatably connected to the internal electronic circuit. | 11-17-2011 |
20110291249 | Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe - A semiconductor device has a prefabricated multi-die leadframe with a base and integrated raised die paddle and a plurality of bodies extending from the base. A thermal interface layer is formed over a back surface of a semiconductor die or top surface of the raised die paddle. The semiconductor die is mounted over the raised die paddle between the bodies of the leadframe with the TIM disposed between the die and raised die paddle. An encapsulant is deposited over the leadframe and semiconductor die. Vias can be formed in the encapsulant. An interconnect structure is formed over the leadframe, semiconductor die, and encapsulant, including into the vias. The base is removed to separate the bodies from the raised die paddle. The raised die paddle provides heat dissipation for the semiconductor die. The bodies are electrically connected to the interconnect structure. The bodies operate as conductive posts for electrical interconnect. | 12-01-2011 |
20110291250 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is provided. The semiconductor chip package includes a lead frame having a chip carrier. A semiconductor chip is mounted on the chip carrier, having a plurality of bonding pads thereon. A package substrate has a cavity therein to accommodate the chip carrier and the semiconductor chip, wherein at least one of the bonding pads of the semiconductor chip is electrically coupled to the package substrate. | 12-01-2011 |
20110298112 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE - A semiconductor module includes a semiconductor chip, a semiconductor frame, a circuit board, and a screw. The semiconductor frame has a main surface having a concave portion in which the semiconductor chip is mounted. The semiconductor frame is thermally and electrically connected with the semiconductor chip through a die bonding material. The circuit board has a grounding pattern and is arranged above the main surface of the semiconductor frame. The screw electrically connects the main surface of the semiconductor frame and the outer peripheral portion of the concave portion to the grounding pattern of the circuit board and mechanically connects the semiconductor frame to the circuit board. | 12-08-2011 |
20110298113 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, including having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface. | 12-08-2011 |
20110304032 | NO LEAD PACKAGE WITH HEAT SPREADER - A no-lead electronic package including a heat spreader and method of manufacturing the same. This method includes the steps of selecting a matrix or mapped no-lead lead frame with die receiving area and leads for interconnect; positioning an integrated circuit device within the central aperture and electrically interconnecting the integrated circuit device to the leads; positioning a heat spreader in non-contact proximity to the integrated circuit device such that the integrated circuit device is disposed between the leads and the heat spreader; and encapsulating the integrated device and at least a portion of the heat spreader and leads in a molding resin. | 12-15-2011 |
20120001308 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor module, a first heat sink is disposed on a rear surface of a first semiconductor chip constituting an upper arm, and a second heat sink is disposed on a front surface of the first semiconductor chip through a first terminal. A third heat sink is disposed on a rear surface of a second semiconductor chip constituting a lower arm, and a fourth heat sink is disposed on a front surface of the second semiconductor chip through a second terminal. A connecting part for connecting between the upper arm and the lower arm is integral with the first terminal, and is connected to the third heat sink while being inclined relative to the first terminal. | 01-05-2012 |
20120001309 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus according to aspects of the invention can include a metal base; resin case having a bonding plane facing metal base; a coating groove formed in bonding plane and holding adhesive for bonding resin case to metal base at a predetermined position, with the top plane of the wall that forms coating groove being spaced apart from the plane which contains bonding plane such that an escape space is formed between the metal base and the resin case; the escape space receiving the excess amount of adhesive which has flowed out from the coating groove; and a receiver groove communicating to the escape space and receiving securely the excess amount of adhesive which the escape space has failed to receive. If an excess amount of adhesive too much for the receiver groove to receive is coated, the excess amount of adhesive can be received in a stopper groove. | 01-05-2012 |
20120025358 | SEMICONDUCTOR ELEMENT WITH SEMICONDUCTOR DIE AND LEAD FRAMES - A semiconductor element to be mounted on a circuit carrier includes a semiconductor die and at least one lead frame. In order to reduce the size required for mounting a semiconductor die on a circuit carrier, a semiconductor element includes a semiconductor die and at least one lead frame. The at least one lead frame is directly attached to the semiconductor die at a connection region of the semiconductor die, and the connection region provides an electrical connection to and mechanical support for the semiconductor die. | 02-02-2012 |
20120025359 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A conventional semiconductor device has a problem that a frame constituting a heat sink is expensive and the heat sink is highly likely to come off a resin package. A semiconductor device of the present invention reduces the frame price because a heat sink is formed by subjecting a frame with a uniform thickness to pressing or something similar. Furthermore, the heat sink is less likely to come off a resin package because step regions of the heat sink are pressed as connection regions to be connected to the other frame in which leads are arranged, and thereby, resin constituting the resin package goes around the step regions and reaches up to back surfaces of the respective step regions. Moreover, a structure which makes the heat sink much less likely to come off is realized because recessed portions are arranged in the step regions of the heat sink. | 02-02-2012 |
20120074545 | THIN FLIP CHIP PACKAGE STRUCTURE - A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess. | 03-29-2012 |
20120098111 | High current capacity inner leads for semiconductor devices, interposer and leadframe - The invention can be used for improving performance of laser diodes, solar cells, microprocessors and other devices. The invention enables to create semiconductor devices and systems comprising several electronic components and having a great area of die, a great number of leads, high operating current and high heat dissipation. This is achieved by the following manner: offered leads are made of copper foil; the rigidity of the foil is decreased by means of creating of alternating narrow trenches and narrow through splits; the offered leads are microspring; additional improvement of performance can be achieved by the bending of inner leads along wide trenches. Offered leads can be directly connected to the dice. | 04-26-2012 |
20120104581 | Semiconductor package device with a heat dissipation structure and the packaging method thereof - The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism. | 05-03-2012 |
20120104582 | High Power Ceramic on Copper Package - According to an embodiment of a high power package, the package includes a heat sink containing enough copper to have a thermal conductivity of at least 350 W/mK, an electrically insulating attached to the heat sink with an epoxy and a semiconductor chip attached to the heat sink on the same side as the lead frame with an electrically conductive material having a melting point of 280° C. or greater. | 05-03-2012 |
20120112332 | RESIN-SEALED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A resin-sealed semiconductor device includes a power element ( | 05-10-2012 |
20120119341 | Semiconductor packages with reduced solder voiding - An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels. | 05-17-2012 |
20120153448 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor. | 06-21-2012 |
20120161302 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present disclosure includes: a plate ( | 06-28-2012 |
20120161303 | POWER SEMICONDUCTOR MODULE - A driver IC which is operated by a power supply system insulated from a control IC is mounted in the vicinity of a switching element on a first conductor pattern. A second conductor pattern connected to a source terminal or an emitter terminal of the switching element is electrically connected to a third conductor pattern on which the driver IC is mounted. A ground terminal of the driver IC is electrically connected to the third conductor pattern, and a drive terminal of the driver IC is electrically connected to a gate terminal or a base terminal of the switching element. | 06-28-2012 |
20120168919 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member. | 07-05-2012 |
20120175755 | SEMICONDUCTOR DEVICE INCLUDING A HEAT SPREADER - A semiconductor device includes a semiconductor chip including back side metal, a substrate, and an electrically conductive heat spreader directly contacting the back side metal. The semiconductor chip includes a sintered joint directly contacting the heat spreader and electrically coupling the heat spreader to the substrate. | 07-12-2012 |
20120181676 | POWER SEMICONDUCTOR DEVICE PACKAGING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 07-19-2012 |
20120181677 | SEMICONDUCTOR DEVICE PACKAGE WITH TWO COMPONENT LEAD FRAME - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 07-19-2012 |
20120241930 | FOLDED LEADFRAME MULTIPLE DIE PACKAGE - A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices. | 09-27-2012 |
20120273930 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect. | 11-01-2012 |
20120280376 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a central lead adjacent to the peripheral lead; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge; and attaching a heatsink to the central lead under the integrated circuit. | 11-08-2012 |
20120292752 | Thermally Enhanced Semiconductor Package with Exposed Parallel Conductive Clip - One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation. | 11-22-2012 |
20120306064 | CHIP PACKAGE - A chip package including a lead frame, a heat sink, a chip and a molding compound is provided. The lead frame includes a chip pad and a plurality of leads, wherein the chip pad has a first surface and a second surface opposite thereto. The heat sink has a third surface and a fourth surface opposite thereto, wherein the lead frame is disposed on the third surface of the heat sink through the second surface of the chip pad, and the fourth surface of the heat sink is exposed. The chip is disposed on the first surface of the chip pad and electrically connected to each of the chip pad and the leads. The molding compound encapsulates the chip, the chip pad, the heat sink and a portion of each of the leads. | 12-06-2012 |
20120313229 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound. | 12-13-2012 |
20120326284 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL EMISSION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead. | 12-27-2012 |
20130001757 | FLIP-CHIP QFN STRUCTURE USING ETCHED LEAD FRAME - A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess. | 01-03-2013 |
20130001758 | Power Semiconductor Package - The present invention provides a power semiconductor package. The power semiconductor package comprises a dual lead frame assembly comprising a bottom lead frame having a first heat sink pad at its bottom surface and a top lead frame having a second heat sink pad at its bottom surface. The top lead frame is coupled to the bottom lead frame by an isolation layer, wherein the isolation layer is a thermal conductive, but electrical isolative, material. The power semiconductor package further comprises a power semiconductor device coupled to the top lead frame of the dual lead frame assembly and an encapsulation member encapsulating the dual lead frame assembly and the power semiconductor device, while exposing the first heat sink pad at the bottom surface of the bottom lead frame. | 01-03-2013 |
20130001759 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package including: first power device; second power device formed in an upper portion of the first power device; a first lead frame formed in a lower portion of the first power device; a second lead frame formed in the upper portion of the first power device and a lower portion of the second power device; a third lead frame formed in an upper portion of the second power device; a fourth lead frame electrically connected to at least one of the power device and the second power device; and a sealing substance exposing a part of the first through fourth lead frames and sealing the other parts thereof. | 01-03-2013 |
20130026615 | DOUBLE-SIDE EXPOSED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device. | 01-31-2013 |
20130026616 | POWER DEVICE PACKAGE MODULE AND MANUFACTURING METHOD THEREOF - The present invention relates to a power device package module and a manufacturing method thereof. In one aspect of the present invention, a power device package module includes: a control unit a first lead frame, a control chip and a first coupling portion that are mounted on a first substrate, wherein the first lead frame and the first coupling portion are electrically connected to the control chip, and individually molded; and a power unit including a second lead frame, a power chip and a second coupling portion that are mounted on a second substrate, wherein the second lead frame and the second coupling portion are electrically connected to the power chip, and individually molded, wherein the individually molded control unit and power unit are coupled by the first coupling portion and the second coupling portion. | 01-31-2013 |
20130043572 | Bump-On-Leadframe Semiconductor Package With Low Thermal Resistance - In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump | 02-21-2013 |
20130056861 | SEMICONDUCTOR DEVICES AND METHODS OF ASSEMBLING SAME - A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element. | 03-07-2013 |
20130062743 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: a heat dissipation plate including a first heat dissipation plate and a second heat dissipation plate disposed to be spaced apart from each other; insulating layers formed on the heat dissipation plate; metal layers formed on the insulating layers, semiconductor devices mounted on the metal layers; and lead spacers formed to connect the metal layer of the first heat dissipation plate side or the metal layer of the second heat dissipation plate side with the semiconductor layers, wherein the semiconductor devices formed on the metal layers of the first heat dissipation plate side and the semiconductor devices formed on the metal layer of the second heat dissipation plate side are disposed in a multi-layered type. | 03-14-2013 |
20130062744 | POWER MODULE PACKAGE - Disclosed herein is a power module package, including: a first substrate having one surface and the other surface; first vias formed to penetrate from one surface of the first substrate to the other surface thereof; a metal layer formed on one surface of the first substrate; semiconductor devices formed on the metal layer; and a metal plate formed on the other surface of the first substrate. | 03-14-2013 |
20130062745 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND POWER SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer. | 03-14-2013 |
20130075882 | PACKAGE STRUCTURE - A package structure including a first leadframe, a second leadframe, a power pin, a ground pin, a first pin, several first wires, several second wires, and a package body is disclosed. The first leadframe is used for electrically coupling to the drains of a first power transistor and the second power transistor. The ground pin is electrically coupled to the first leadframe. The first pin is connected with the first leadframe through a conductive region used for increasing the amount of current which can be loaded by the first pin. The first wires are used for electrically coupling between the first leadframe and the source of the second power transistor, for reducing the internal resistance of the second power transistor. The second wires are used for electrically coupling between the ground pin and the source of the first power transistor, for reducing the internal resistance of the first power transistor. | 03-28-2013 |
20130087899 | DIODE CELL MODULES - Diode cell modules for use within photovoltaic systems, including lead frames including first leads extending from the first outlet terminal, second leads spaced from the first leads, second outlet terminals extending from the second leads, and diodes. In some examples, first leads define base portions connected to the first outlet terminal and diode portions extending from the base portions transverse to the first outlet terminal. In some examples, second leads may define a base portion and diode portions extending from the base portion substantially parallel to the diode portion of the first lead. In some examples, diodes may be in electrical contact with the diode portion of the first lead and with the diode portion of the second lead. In some examples, the first leads and second leads may be thermally conductive. In some examples, diodes may define die interfaces that are substantially fully engaged with diode portions of leads. | 04-11-2013 |
20130087900 | Thermally Enhanced Low Parasitic Power Semiconductor Package - A semiconductor device includes a source region, a gate region and a drain region. A first leadframe subassembly is coupled to the drain region. on a second side of the die are attached to a second leadframe subassembly. A second leadframe subassembly has a first portion electrically coupled with the source region and a second portion electrically coupled with the gate region. The first leadframe subassembly is attached to a third leadframe subassembly. A die is interposed between the first leadframe subassembly and the second leadframe subassembly. The height of the third leadframe subassembly provides a standoff for a distance between the first leadframe subassembly and the second leadframe subassembly. | 04-11-2013 |
20130099364 | Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method - A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang. | 04-25-2013 |
20130105954 | SEMICONDUCTOR PACKAGE | 05-02-2013 |
20130119525 | Power Semiconductor Unit, Power Module, Power Semiconductor Unit Manufacturing Method, and Power Module Manufacturing Method - Heat radiation surfaces | 05-16-2013 |
20130127029 | TWO LEVEL LEADFRAME WITH UPSET BALL BONDING SURFACE AND DEVICE PACKAGE - A leadframe, device package, and mode of construction configured to attain a thin profile and improved thermal performance. Leadframes of this invention include a raised die attachment pad arrange above distal ends of leadframe leads. A package will further include a die electrically coupled with an underside surface of the raised die attachment pad, in one example, using ball bonds, the whole sealed in an encapsulant that exposed a bottom portion of the die and a portion of a lead. Two leadframe stacks of such packages are also disclosed as are methods of manufacture. | 05-23-2013 |
20130154068 | PACKAGED LEADLESS SEMICONDUCTOR DEVICE - A packaged leadless semiconductor device ( | 06-20-2013 |
20130154069 | SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package, including: a first heat dissipation substrate; a first lead frame that is formed on the first heat dissipation substrate by patterning; a first semiconductor device formed on the first lead frame; a second semiconductor device that is stacked on the first semiconductor device; a second lead frame that is patterned and bonded to the second semiconductor device; and a second heat dissipation substrate formed on the first lead frame. | 06-20-2013 |
20130154070 | SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package. The semiconductor package includes: semiconductor elements, a first heat dissipation substrate formed under the semiconductor elements, a first lead frame electrically connecting the lower portions of the semiconductor elements to an upper portion of the first heat dissipation substrate, a second heat dissipation substrate formed over the semiconductor elements, and a second lead frame having a protrusion formed to be protruded from a lower surface thereof and electrically connecting the upper portions of the semiconductor elements to a lower portion of the second heat dissipation substrate. | 06-20-2013 |
20130161803 | Semiconductor Package with Conductive Heat Spreader - A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. | 06-27-2013 |
20130175678 | Power Semiconductor Module and Manufacturing Method Thereof - A power semiconductor module includes a power semiconductor element formed with a plurality of control electrodes on one main surface, a first conductor plate bonded by way of a first solder material to one of the main surfaces of the power semiconductor element, and a second conductor plate bonded by way of a second solder material on the other main surface of the power semiconductor element. A first protrusion section protruding from the base section of the applicable first conductor plate and including a first protrusion surface formed over the upper side, is formed over the first conductor plate. A second protrusion section including a second protrusion surface formed facing opposite one of the main surfaces of the power semiconductor element. The first solder material is interposed between the power semiconductor element and the first conductor plate while avoiding the plural control electrodes. If there is an projection from a perpendicular direction by one of the main surfaces of the power semiconductor element, the second protrusion section is formed so that the projecting section on a specified side of the second protrusion surface overlaps the projecting section of the step section formed between the base section of the first conductor plate and the first protrusion section. The plural control electrodes on the power semiconductor element are formed along the specified side of the second protrusion surface. | 07-11-2013 |
20130207249 | ASSEMBLY HAVING STACKED DIE MOUNTED ON SUBSTRATE - Metal rerouting interconnects at one or more sides of a die or multiple die segments can form edge bonding pads for electrical connection. Insulation can be applied to surfaces of the die or multiple die segments after optional thinning and singulation, and openings can be made in the insulation to the electrical connection pads. After being placed atop one another in a stack, vertically adjacent die or die segments can be electrically interconnected using a flexible bond wire or bond ribbon attached to an electrical connection pad exposed within such opening, the bond wire or ribbon protruding horizontally, and an electrically conductive polymer, or epoxy, filaments or lines can be applied to the stack. | 08-15-2013 |
20130256854 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING LEAD FRAME - A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer. | 10-03-2013 |
20130270684 | POWER MODULE AND LEAD FRAME FOR POWER MODULE - The present invention aims at providing a power module and a lead frame for the power module which can enhance adhesion between a heat sink and an insulating resin sheet while maintaining heat radiation properties. The power module includes: the lead frame including a conductor plate formed from Cu or a Cu alloy, and an Al film formed at least on the other side, opposite to one side on which to mount a semiconductor device, of the conductor plate; the semiconductor device mounted on the one side of the conductor plate; a sealing resin which seals at least the semiconductor device and the conductor plate; and an insulating resin sheet adhered to the conductor plate through the Al film therebetween. | 10-17-2013 |
20130285220 | VERTICALLY PACKAGED INTEGRATED CIRCUIT - A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate. | 10-31-2013 |
20130285221 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device has a heat dissipating base; a patterned insulating substrate attached to the heat dissipating base with a solder therebetween; a semiconductor chip attached to a conductive pattern of the patterned insulating substrate with a solder therebetween; a first conductor attached to the semiconductor chip with a solder therebetween; a resin case attached to the heat dissipating base with an adhesive; and a second conductor attached to the first conductor by laser welding. The second conductor formed by rolling has stripe-shaped rolling traces formed on a surface thereof in a rolling direction and is disposed on the first conductor such that the rolling traces are arranged in a same direction. | 10-31-2013 |
20130299955 | FILM BASED IC PACKAGING METHOD AND A PACKAGED IC DEVICE - Film-on-wire (FOW) based IC devices and FOW based methods for IC packaging are described. In an embodiment, a method for packaging an IC dies involves applying a film layer to IC dies and bond wires that are attached to a substrate or a leadframe to form a film-on-wire layer, where the IC dies and the bond wires are enclosed by the film-on-wire layer, and cutting the substrate or the leadframe into IC devices. Other embodiments are also described. The FOW based method for IC packaging can eliminate the need for molding in the IC packaging process and consequently, can reduce the cost of IC packaging and the dimensions of packaged IC devices. | 11-14-2013 |
20130313696 | POWER SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A power semiconductor package and a method of method of manufacturing the same are disclosed, where the power semiconductor package includes a lead frame, a first die, a second die and a single connecting strip. The lead frame includes a voltage plate, a grounding plate, an output plate, a first gate plate and a second gate plate. The first die is disposed on the voltage plate, and a high side transistor within the first die is connected to the first gate plate. The second die is disposed on the grounding plate, and a low side transistor within the second die is connected to the second gate plate. The connecting strip is disposed on the first and second dies and the output plate and electrically connects to a source of the high side transistor and a drain of the low side transistor. | 11-28-2013 |
20130320514 | Package-in-Package for High Heat Dissipation Having Leadframes and Wire Bonds - A semiconductor system ( | 12-05-2013 |
20130328180 | PACKAGED SEMICONDUCTOR DEVICE WITH AN EXPOSED METAL TOP SURFACE - In a manufacturing technique for packaged semiconductor devices, a pre-form of a packaged semiconductor device is formed by a molding process which encapsulates the semiconductor device and its associated heat transfer component in a passivating material presenting a surface. The surface is then processed to at least remove excess passivating material and expose the heat transfer component. The processing may further remove a portion of the heat transfer component. The removal process may, for example, utilize a grinding and/or polishing process. The process may be controlled so as to expose or form a heat transfer surface of desired shape and size. | 12-12-2013 |
20130334673 | FLEXIBLE POWER MODULE SEMICONDUCTOR PACKAGES - Power module semiconductor packages that contain a flexible circuit board and methods for making such packages are described. The semiconductor package contain a flexible circuit board, a conductive film on a first portion of the upper surface of the flexible circuit board, a land pad on a second portion of the upper surface of the flexible circuit board, a heat sink on a portion of the bottom surface of the flexible circuit board, a passive component, a discrete device, or an IC device connected to a portion of the conductive film, and a lead of a lead frame connected to the land pad. These packages can have a high degree of design flexibility of the layout of the package and simpler routing designs, reducing the time to design the packages and reducing the costs of the packages. Other embodiments are also described. | 12-19-2013 |
20130341776 | Semiconductor Device Apparatus and Assembly with Opposite Die Orientations - An electronic apparatus includes a base substrate, the base substrate including an interconnect. The electronic apparatus further includes a first die including a first semiconductor device, the first semiconductor device being coupled to the interconnect, and further includes a second die including a second semiconductor device, the second semiconductor device being coupled to the interconnect. The first and second die are attached to the base substrate in opposite orientations. | 12-26-2013 |
20130341777 | Electro-Thermal Cooling Devices and Methods of Fabrication Thereof - In one embodiment, a semiconductor module includes a leadframe having a first side and an opposite second side. A semiconductor chip is disposed over the first side of the leadframe. A switching element is disposed under the second side of the leadframe. In another embodiment, a method of forming a semiconductor module includes providing a semiconductor device having a leadframe. A semiconductor chip is disposed over a first side of the leadframe. A switching element is attached at an opposite second side of the leadframe. | 12-26-2013 |
20140001613 | SEMICONDUCTOR PACKAGE | 01-02-2014 |
20140001614 | Thermally Enhanced Semiconductor Package | 01-02-2014 |
20140008776 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip. | 01-09-2014 |
20140027891 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed | 01-30-2014 |
20140048918 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a connection structure in which a power semiconductor chip is mounted on an insulating substrate having conductor patterns bonded to front and rear surfaces thereof, and the insulating substrate is connected to a heat-dissipating base member to dissipate heat generated from the power semiconductor chip to outside. The conductor pattern on the rear surface bonded to the heat-dissipating base member has a bonding portion having a rectangular shape and a predetermined curvature radius in vicinity of corners. | 02-20-2014 |
20140070387 | COUPLING ASSEMBLY OF POWER SEMICONDUCTOR DEVICE AND PCB AND METHOD FOR MANUFACTURING THE SAME - Provided is a coupling assembly of a power semiconductor device and a printed circuit board (PCB). The coupling assembly of the power semiconductor device and the printed circuit board (PCB) includes a PCB, a power semiconductor device comprising a plurality of legs electrically connected to a circuit pattern disposed on the PCB, a connection member disposed above the power semiconductor device, the connection member being formed of an electrically conductive material, a main fixing unit fixing the power semiconductor device to the PCB, and a housing disposed outside the PCB. Thus, a coupling force between the power semiconductor device and the PCB and electric efficiency may be improved to a heat generation amount. In addition, heat may be more quickly dissipated through the connection member to improve a cooling effect. | 03-13-2014 |
20140084431 | Semiconductor Package with Heat Spreader - A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. | 03-27-2014 |
20140091445 | BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER - An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface. | 04-03-2014 |
20140091446 | SEMICONDUCTOR DEVICE EMPLOYING ALUMINUM ALLOY LEAD-FRAME WITH ANODIZED ALUMINUM - A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices. | 04-03-2014 |
20140103505 | DIE DOWN INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SPREADER AND LEADS - Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package, such as a quad flat no-lead (QFN) package, includes a plurality of peripherally positioned leads, a heat spreader, an integrated circuit die, and an encapsulating material. The peripherally positioned leads are attached to a first surface of the heat spreader, and the die is attached to the first surface of the heat spreader within a ring formed by the leads. The encapsulating material encapsulates the die on the heat spreader, encapsulates bond wires, and fills a space between the leads. A second surface of the heat spreader is exposed from the package. End portions of the leads have surfaces that are flush with a surface of the package opposite the second surface of the heat spreader, and that are used as lands for the package. | 04-17-2014 |
20140103506 | SEMICONDUCTOR CHIP DEVICE WITH POLYMERIC FILLER TRENCH - A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench. | 04-17-2014 |
20140110828 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink. | 04-24-2014 |
20140117521 | SEMICONDUCTOR DEVICE WITH THERMAL DISSIPATION LEAD FRAME - A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot. | 05-01-2014 |
20140117522 | SEMICONDUCTOR PACKAGE - There is provided a semiconductor package including: a lead frame having an electronic component mounted on one surface thereof; a heat dissipation substrate disposed downwardly of the lead frame; an insulating member disposed upwardly of the electronic component such that the electronic components are electrically connected to one another; a conductive member disposed between the insulating member and the lead frame and electrically connecting the electronic component to the lead frame; and a molded portion hermetically sealing the insulating member and the heat dissipation substrate. | 05-01-2014 |
20140131847 | THERMAL PERFORMANCE OF LOGIC CHIP IN A PACKAGE-ON-PACKAGE STRUCTURE - Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink. | 05-15-2014 |
20140151864 | ATOMIC LEVEL BONDING FOR ELECTRONICS PACKAGING - An electronic device assembly that includes a die and a substrate, and optionally a lead frame and a heat spreader. The die is characterized as an electronic device in die form, and has a polished die region. The substrate has a polished substrate region in direct contact with the polished die region. The polished die region and the polished substrate region have surface finishes effective to attach the die to the substrate by way of an atomic bond. The lead-frame has a polished lead-frame region, and the heat spreader has a polished heat spreader region. These polished regions may also be attached to the polished die region or the polished substrate region by way of an atomic bond. | 06-05-2014 |
20140159215 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically connected to the plurality of external terminals on a front surface, a semiconductor chip mounted on the front surface of the substrate, a surface of the chip including a plurality of bonding pads, a plurality of bonding wires connecting between the plurality of bonding pads or between the plurality of bonding terminals and the plurality of bonding wires respectively, a first sealing layer sealing the front surface of the substrate, the plurality of bonding wires and the semiconductor chip, and a second sealing layer comprised of the same material as the first sealing, the second sealing layer being formed above the first sealing layer. | 06-12-2014 |
20140159216 | SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MODULE, AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE - A semiconductor module is configured such that heat radiation substrates are connected to lead frames and semiconductor chips are directly connected to the lead frames so that the semiconductor chips are not connected to the lead frames through conductive portions of the heat radiation substrates. Therefore, the conductive portion can have a solid shape without being divided. As such, an occurrence of curving of the heat radiation substrates is suppressed when a temperature is reduced from a high temperature to a room temperature after resin-sealing at the high temperature or the like. Therefore, connection between the semiconductor chip and the lead frames and connection between the lead frames and the heat radiation substrates enhance. | 06-12-2014 |
20140183712 | BALL GRID ARRAY PACKAGE WITH IMPROVED THERMAL CHARACTERISTICS - An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die mounted on the first surface of the substrate. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulant encapsulates the wirebonds and the semiconductor die. A heat spreader has a cap, at least a portion of the cap extending inwardly toward and being spaced from the semiconductor die. The encapsulant fills the space between the portion of the cap and the semiconductor die. The heat spreader further has at least one sidewall extending from the cap, the at least one sidewall disposed on the substrate. A ball grid array is disposed on the second surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces. | 07-03-2014 |
20140203420 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE PRODUCED USING PRODUCTION METHOD - A method for producing a semiconductor device includes laser welding to bond an upper terminal and a lower terminal as internal wiring members of the semiconductor device. When the upper terminal is fixed to the lower terminal by the laser welding, a gap between an upper surface of the lower terminal and a lower surface of the upper terminal is equal to or more than 20 μm and equal to or less than 400 μm. | 07-24-2014 |
20140231976 | METHOD FOR PRODUCING A SOLDER JOINT - The invention relates to a method for producing a solder joint between at least one base part ( | 08-21-2014 |
20140239470 | RESIN PACKAGE - A resin package includes: a die pad having a main surface on which a semiconductor substrate and a matching circuit substrate is mounted; at least one lead terminal electrically connected to the semiconductor substrate and the matching circuit substrate; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and molding resin which covers the semiconductor substrate, the matching circuit substrate, and the thin plate. | 08-28-2014 |
20140264798 | Packaged Device Comprising Non-Integer Lead Pitches and Method of Manufacturing the Same - Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches. | 09-18-2014 |
20140264799 | POWER OVERLAY STRUCTURE AND METHOD OF MAKING SAME - A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface. | 09-18-2014 |
20140264800 | POWER OVERLAY STRUCTURE AND METHOD OF MAKING SAME - A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader. | 09-18-2014 |
20140264801 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package. | 09-18-2014 |
20140291823 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip. | 10-02-2014 |
20140299979 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. A semiconductor device has a first metal plate and a second metal plate electrically isolated from the first metal plate. Over the first metal plate, a first semiconductor chip including a transistor element formed thereover is mounted. Whereas, over the second metal plate, a second semiconductor chip including a diode element formed thereover is mounted. Further, the semiconductor device has a lead group including a plurality of leads electrically coupled with the first semiconductor chip or the second semiconductor chip. The first and second metal plates are arranged along the X direction in which the leads are arrayed. Herein, the area of the peripheral region of the first semiconductor chip in the first metal plate is set larger than the area of the peripheral region of the second semiconductor chip in the second metal plate. | 10-09-2014 |
20140306330 | Low Profile Leaded Semiconductor Package - In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed. | 10-16-2014 |
20140312480 | DOUBLE-SIDE EXPOSED SEMICONDUCTOR DEVICE - A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device. | 10-23-2014 |
20140332941 | SYSTEM, METHOD AND APPARATUS FOR LEADLESS SURFACE MOUNTED SEMICONDUCTOR PACKAGE - A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body. | 11-13-2014 |
20140374891 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER AND THERMAL SHEET - A semiconductor device includes a die pad and a semiconductor die having a mounting surface attached to the die pad and an opposite, active surface with die external terminals. The device has package external connectors, each having a bond region selectively electrically coupled to the die external terminals with a bond wire. A heat spreader has a first region that encloses an inner recessed region. A thermally conductive sheet is sandwiched between the inner recessed region of the heat spreader and the active surface of the die. At least the die, die external terminals, and the bond region are covered with an encapsulant. | 12-25-2014 |
20150014832 | Semiconductor Device Having Three Terminal Miniature Package - A semiconductor device ( | 01-15-2015 |
20150028462 | SEMICONDUCTOR MODULE - A semiconductor module includes: a metal block; an insulation layer for heat radiation formed by directly depositing a ceramic material on at least a first surface of the metal block; an insulation layer for a relay electrode formed by directly depositing a ceramic material on a part of a second surface | 01-29-2015 |
20150035129 | STACKED MULTI - CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip. | 02-05-2015 |
20150061095 | PACKAGE-ON-PACKAGE DEVICES, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGES - In a package-on-package (PoP) device according to the inventive concepts, an anisotropic conductive film is disposed between a lower semiconductor package and an upper semiconductor package to remove an air gap between the lower and upper semiconductor packages. Thus, heat generated from a lower semiconductor chip may be rapidly and smoothly transmitted toward the upper semiconductor package, thereby increasing or maximizing a heat exhaust effect of the PoP device. | 03-05-2015 |
20150076674 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes: a semiconductor chip; a resin which covers the semiconductor chip, and includes first and second surfaces opposite to each other, first and second side surfaces opposite to each other, and third and fourth side surfaces opposite to each other; a first conductive member which is formed on the semiconductor chip on a first surface side, and includes an end portion projecting from the first or second side surface; a second conductive member including an end portion projecting from the first or second side surface; and a metal which is formed on a second surface side of the semiconductor chip, is exposed from the resin body on the second surface side, and includes an end portion thereof exposed from the third and fourth side surfaces on the same plane as the third and fourth side surfaces. | 03-19-2015 |
20150084170 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate. | 03-26-2015 |
20150091146 | POWER SEMICONDUCTOR PACKAGE - Disclosed herein is a power semiconductor package. The power semiconductor package according to a preferred embodiment of the present invention includes: a semiconductor device; a circuit pattern formed on the semiconductor device; a molding member burying the semiconductor device and the circuit pattern and formed so as to expose one surface of the circuit pattern; and a heat radiating member adhered to the circuit pattern exposed by the molding member and formed of a non-conductive material. | 04-02-2015 |
20150102474 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND POWER SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer. | 04-16-2015 |
20150102475 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound. | 04-16-2015 |
20150108625 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A semiconductor device includes a package body, a semiconductor die embedded in the package body and a heat spreader attached to a top surface of the package body and spaced from semiconductor die. The heat spreader may be formed of solder that is melted within a recess in the top surface of the package body. | 04-23-2015 |
20150115423 | SEMICONDUCTOR MODULE FOR ELECTRIC POWER - Included are: the third frame which is electrically connected to the first intermediate frame and is arranged above the first frame; the fourth frame which is electrically connected to the second intermediate frame and is arranged above the second frame; the electric source terminal part which is provided on an extension of the first frame; the ground terminal part which is provided on an extension of the fourth frame; and the output terminal part which is provided on an extension to which the second frame and the third frame are electrically joined, wherein the third frame and the fourth frame are arranged in parallel with each other, and the electric source terminal part, the ground terminal part and the output terminal part are arranged in a manner such that induced electric voltages, which are generated in the third frame and the fourth frame, become in reverse directions with each other. | 04-30-2015 |
20150115424 | ELECTRONIC SYSTEM COMPRISING STACKED ELECTRONIC DEVICES PROVIDED WITH INTEGRATED-CIRCUIT CHIPS - An electronic system includes a first electronic device (with a first integrated-circuit chip) and a second electronic device (with a second integrated-circuit chip). The second electronic device is stacked above the first electronic device on a same side as the first integrated-circuit chip. Electrical connection elements located around the first integrated-circuit chip electrically connected to the second electronic device to the first electronic device. A metal plate configured for heat capture and transfer extends between the first and second electronic devices. The metal plate includes through-passages aligned to permit the electrical connection elements to pass at a distance. | 04-30-2015 |
20150130036 | Semiconductor Package with Low Profile Switch Node Integrated Heat Spreader - In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier. | 05-14-2015 |
20150145111 | Electronic component with electronic chip between redistribution structure and mounting structure - An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the electronic chip, and a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting the electronic component to an electronic periphery, wherein at least one of the electrically conductive mounting structure and the electrically conductive redistribution structure comprises electrically conductive inserts in an electrically insulating matrix. | 05-28-2015 |
20150294928 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding. | 10-15-2015 |
20150303125 | SEMICONDUCTOR APPARATUS INCLUDING A HEAT DISSIPATING MEMBER - A semiconductor apparatus is provided. The semiconductor apparatus includes: a base having a main surface on which a terminal is disposed; a first semiconductor device retained on the main surface of the base and having a top surface on which an electrode is disposed and a bottom surface facing the main surface of the base; a connection member connecting the terminal and the electrode; an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member; and a heat dissipating member disposed on the encapsulant and having a space that opens in a direction extending perpendicular to the main surface of the base. The encapsulant is disposed in the space and, in a side view of the base, a peak of the connection member is located inside the space. | 10-22-2015 |
20150303132 | POWER MANAGEMENT APPLICATIONS OF INTERCONNECT SUBSTRATES - Various applications of interconnect substrates in power management systems are described. | 10-22-2015 |
20150311144 | Low-Profile Footed Power Package - A power package includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with an electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed. | 10-29-2015 |
20150318227 | ADHESIVE COMPOSITION AND ADHESIVE SHEET, AND HARDENED ARTICLE AND SEMICONDUCTOR DEVICE USING SAME - The purpose of the present invention is to provide an adhesive composition having high heat conductivity and excellent adhesion, in which the dispersibility of a heat-conductive filler is controlled, and in which thermal stress during cooling/heating cycle testing can be alleviated. An adhesive composition containing a soluble polyimide (A), an epoxy resin (B), and a heat-conductive filler (C), the adhesive composition characterized by containing three types of diamine residues having a specific structure, and in that the content of the epoxy resin (B) is 30-100 parts by weight with respect to 100 parts by weight of the soluble polyimide (A). | 11-05-2015 |
20150318232 | METHOD AND APPARATUS FOR MOUNTING SOLDER BALLS TO AN EXPOSED PAD OR TERMINAL OF A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a package comprising a die attach pad, a die disposed on the die attach pad and a leadframe. The leadframe includes an opening defined therein that exposes a bottom surface of the die attach pad. The leadframe comprises a plurality of bond pads that are exposed at a bottom surface of the leadframe and a plurality of traces that are exposed at the bottom surface of the leadframe. Each trace of the plurality of traces is coupled to a corresponding bond pad of the plurality of bond pads. At least some of the traces are coupled to the die at top surfaces of the at least some of the traces. The leadframe also comprises a plurality of first insulated barriers. Each first insulated barrier is located between (i) a corresponding trace and (ii) a corresponding bond pad coupled to the corresponding trace. | 11-05-2015 |
20150325559 | EMBEDDED PACKAGE AND METHOD THEREOF - The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design. | 11-12-2015 |
20150348884 | Power Semiconductor Package with Multi-Section Conductive Carrier - In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed. The power semiconductor package according to the present disclosure results in effective thermal protection, current carrying capability, and a relatively small size. | 12-03-2015 |
20150348888 | Semiconductor Package with Integrated Heat Spreader - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier. | 12-03-2015 |
20150348890 | CONVERTER HAVING PARTIALLY THINNED LEADFRAME WITH STACKED CHIPS AND INTERPOSER, FREE OF WIRES AND CLIPS - Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad has a portion recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip. | 12-03-2015 |
20150357269 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip, bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk, and an upper package on the lead frame and electrically connected to the lead frame. | 12-10-2015 |
20150371934 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture. | 12-24-2015 |
20160002445 | THERMALLY CONDUCTIVE SHEET, CURED PRODUCT THEREOF, AND SEMICONDUCTOR DEVICE - A thermally conductive sheet includes a thermosetting resin and an inorganic filler material dispersed in the thermosetting resin. Measuring a pore diameter distribution through mercury intrusion technique for the inorganic filler material included in an incineration residue after a cured product of the thermally conductive sheet is heated and incinerated at 700° C. for four hours, a porosity of the inorganic filler material represented as 100×b/a is greater than or equal to 40% and less than or equal to 65% given that a is the volume of particles of the inorganic filler material included in the incineration residue, and b is the volume of voids in the particles of the inorganic filler material included in the incineration residue. An average pore diameter of the inorganic filler material included in the incineration residue is greater than or equal to 0.20 μm and less than or equal to 1.35 μm. | 01-07-2016 |
20160005674 | INTEGRATED CIRCUIT ASSEMBLY AND INTEGRATED CIRCUIT PACKAGING STRUCTURE - An integrated circuit packaging structure includes a chip, an electrical bump, a heat dissipation bump, a lead frame, and a sealant. The chip includes an active surface and an electronic component that is formed by using a semiconductor process. The electrical bump is electrically connected to the electronic component through the active surface. The heat dissipation bump is connected to the active surface. The lead frame is electrically connected to the electrical bump. The sealant covers the chip, the lead frame, and the electrical bump, wherein the heat dissipation bump and a part of the lead frame are exposed without being covered. The height of the heat dissipation bump relative to the active surface is unequal to that of the electrical bump relative to the active surface. | 01-07-2016 |
20160005675 | Double sided cooling chip package and method of manufacturing the same - A double sided cooling chip package is provided, wherein the package comprises a first heat sink; a second heat sink; a stacked chip arrangement comprising a first electronic chip, a second electronic chip and an interfacing substrate arranged between the first electronic chip and the second electronic chip and comprising electric circuitry on at least one main surface, wherein one of the first electronic chip and the second electronic chip is electrically connected to the electric circuitry of the interfacing substrate; and wherein the first electronic chip is attached to the first heat sink and the second electronic chip is attached to the second heat sink. | 01-07-2016 |
20160005680 | Exposed-Heatsink Quad Flat No-Leads (QFN) Package - Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a heat sink array having a top-side surface and an under-side surface; the heat sink array has die placement areas on the top-side surface. A plurality of active device die are die bonded onto the die placement areas on the heat sink array. The plurality of active device die are singulated into an individual heat sink device die having a heat sink portion attached to its underside. | 01-07-2016 |
20160005682 | Matrix Lid Heatspreader for Flip Chip Package - A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array ( | 01-07-2016 |
20160035645 | EXPOSED, SOLDERABLE HEAT SPREADER FOR FLIPCHIP PACKAGES - A flipchip package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the flipchip package. | 02-04-2016 |
20160056094 | BALL GRID ARRAY PACKAGE WITH MORE SIGNAL ROUTING STRUCTURES - A semiconductor package includes a substrate, a die mounted on a first side of the substrate, an array of solder balls mounted on a second, opposite side of the substrate, and a signal-routing structure mounted on the first side of the substrate and adjacent to the die. The substrate and the signal-routing structure provide electrical connections between die pads on the die and some of the solder balls. | 02-25-2016 |
20160056098 | SEMICONDUCTOR DEVICE EMPLOYING ALUMINUM ALLOY LEAD-FRAME WITH ANODIZED ALUMINUM - A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices. | 02-25-2016 |
20160079147 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package part having a semiconductor element sealed in resin, a plurality of first leads each having an outer portion extending from a first side of the package part, and a plurality of second leads each having an outer portion extending from a second side of the package part. A combined bottom surface area of the outer portions of the plurality of first leads is greater than a combined bottom surface area of the outer portions of the plurality of second leads. The semiconductor device also includes a heat dissipation plate provided on the bottom surface of the package part and connected to at least one of the plurality of second leads. | 03-17-2016 |
20160079156 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - The present disclosure describes a power electronics module comprising a lead frame in which a chip of a first semiconductor device is embedded, a first PCB mounted on top of the lead frame and the chip of the first semiconductor device, and a support frame mounted on top of the PCB, the support frame comprising a cavity in which the chip of a second semiconductor device is embedded, wherein the chips of the first semiconductor device and the second semiconductor device are positioned on top of each other, and the first PCB comprises a first electrically conducting path between the chips of the first semiconductor device and the second semiconductor device. | 03-17-2016 |
20160079221 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included. | 03-17-2016 |
20160111354 | ELECTRONIC DEVICE WITH FIRST AND SECOND CONTACT PADS AND RELATED METHODS - An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads. | 04-21-2016 |
20160163623 | SYSTEM, METHOD AND APPARATUS FOR LEADLESS SURFACE MOUNTED SEMICONDUCTOR PACKAGE - A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body. | 06-09-2016 |
20160172278 | ASSEMBLY OF AN INTEGRATED CIRCUIT CHIP AND OF A PLATE | 06-16-2016 |
20160172281 | PACKAGING STRUCTURE | 06-16-2016 |
20160172285 | POWER MODULE | 06-16-2016 |
20160190045 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A semiconductor device includes: a semiconductor element having a functional surface formed with a functional circuit and a reverse surface opposite to the functional surface; an electroconductive support member supporting the semiconductor element and electrically connected to the semiconductor element; and a resin package covering the semiconductor element and at least a part of the electroconductive support member. The semiconductor element is provided with an electrode including a projection on the functional surface and with a reinforcing layer formed on the functional surface. The semiconductor device further includes a solid-state welded portion formed by solid state welding of at least a part of the projection of the electrode and at least a part of the electroconductive support member. | 06-30-2016 |
20160190086 | PACKAGED SEMICONDUCTOR DEVICES HAVING RIBBON WIRES - A packaged semiconductor device, such as a power QFN device, has (rectangular) ribbon wires, instead of circular bond wires. A proximal end of each ribbon wire is connected to a pad on an IC die, and a distal end of each ribbon wire forms a device lead. The die and the ribbon wires are encapsulated in a molding compound with a side of each device lead exposed. Such devices can be assembled without using lead frames. The omission of lead frames and the use of ribbon wires enable assembly of smaller devices having enhanced thermal dissipation capabilities. | 06-30-2016 |
20160204080 | SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME | 07-14-2016 |
20160254217 | PACKAGE MODULE OF POWER CONVERSION CIRCUIT AND MANUFACTURING METHOD THEREOF | 09-01-2016 |
20160379919 | Electronic device and method of manufacturing the same - Various embodiments provide an electronic device, wherein the electronic device comprises a carrier body; a plurality of pins, a die comprising a switched terminal; wherein the switched terminal is attached onto and electrically connected to one of the plurality of pins; and wherein the die is configured in such a way that the switched terminal is electrically connected to a high electrical potential. | 12-29-2016 |
20170236774 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR DRIVING DEVICE | 08-17-2017 |