Entries |
Document | Title | Date |
20080197460 | PACKAGED IC DEVICE COMPRISING AN EMBEDDED FLEX CIRCUIT, AND METHODS OF MAKING SAME - A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material. | 08-21-2008 |
20080237816 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATING FEATURES - An integrated circuit package system is provided including forming a lead frame includes forming a mold gate, providing a first surface, and providing a second surface opposite the first surface; and forming angled gate sides facing each other in the mold gate between the first surface and the second surface. | 10-02-2008 |
20080251899 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which a plurality of chips are packaged without increasing the thickness of the package. A plurality of semiconductor elements (a first and a second semiconductor elements) that are packaged in the semiconductor device are overlaid with each other. Specifically, the first semiconductor element is fixed on the top surface of the first island while the second semiconductor element is fixed on the bottom surface of the second island. Furthermore, each of the islands (a first and a second islands) on which the semiconductor elements are respectively mounted in the present invention provides a structure has an irregular shape, and the islands are overlaid with each other along the sides of the semiconductor element to be mounted. | 10-16-2008 |
20080265384 | Integrated Circuit Package Device With Improved Bond Pad Connections, a Lead-Frame and an Electronic Device - A semiconductor device package ( | 10-30-2008 |
20080283978 | Leadframe For a Semiconductor Device - A leadframe ( | 11-20-2008 |
20080283979 | Semiconductor Package Having Reduced Thickness - A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads. | 11-20-2008 |
20080283980 | LEAD FRAME FOR SEMICONDUCTOR PACKAGE - A lead frame ( | 11-20-2008 |
20080283981 | Chip-On-Lead and Lead-On-Chip Stacked Structure - A chip-stacked package structure comprises a lead frame, a first chip, and a second chip. The led frame is composed of a plurality of inner leads and a plurality of outer leads. The plurality of inner leads comprises a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, wherein the ends of first inner leads and the ends of second inner leads are arranged in rows facing each other at a distance. The active surface of first chip is fixedly connected to the lower surface of first inner leads and second inner leads via a first adhesive layer. A plurality of metal pads is provided near the central area of the active surface of first chip and is exposed. A second adhesive layer is formed on the back surface of second chip for fixedly connecting the back surface of second chip and the upper surface of first inner leads and second inner leads. The gap formed by the thickness of second adhesive layer prevents the bonding wires connecting the first chip from contacting the back surface of second chip. | 11-20-2008 |
20080290481 | Semiconductor Device Package Leadframe - The invention provides semiconductor device packages, leadframes, and methods for their manufacture, with improved characteristics for the formation of metallurgical joints. In a disclosed preferred embodiment of a semiconductor device leadframe according to the invention, a generally rectangular sheet metal body has a semiconductor device mounting site for receiving a semiconductor device. Leadfingers extend from the proximity of the device mounting site the outer edges of the leadframe. An anchor pad is included at each corner of the leadframe body, each anchor pad having a patterned surface. According disclosed aspects of the invention, the patterned surfaces of the anchor pads may include indented, embossed, or cut-out portions. According to other aspects of the invention, patterned anchor pad surfaces are plated with a low-melting point alloy and remain exposed at the corners of an encapsulated package. | 11-27-2008 |
20080290482 | METHOD OF PACKAGING INTEGRATED CIRCUITS - A method of packaging integrated circuit dice into exposed die packages is described. The method includes depositing a metallic layer onto the back surface of an integrated circuit wafer such that it covers the back surface. The method additionally includes applying a protective layer over the metallic layer such that the protective layer covers the metallic layer. The method further includes singulating the wafer to produce individual dice. Each die may then be electrically connected to a lead frame. The die and portions of the lead frame may then be encapsulated with a molding compound. The protective layer inhibits the molding compound from contacting the metallic layer on the back surface of the die. The protective layer is then removed from the metallic layer. As a result, an individual IC package is produced that includes a die having a metallic layer exposed on the back surface of the die. | 11-27-2008 |
20080290483 | SEMICONDUCTOR DEVICE, LEADFRAME AND STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE - A structure of a semiconductor device is provided, where intervals can be narrowed between leads arranged around a semiconductor element to increase the number of leads, and electrical interference is prevented or reduced between the leads to cause no crosstalk between the leads. The semiconductor device of the present invention includes a semiconductor element and a plurality of leads arranged around the semiconductor element. The plurality of leads include a plurality of first leads and a plurality of second leads. The plurality of first leads are connected to electrode terminals of the semiconductor element through connection members. The plurality of second leads are arranged between the first leads and are not connected to the electrode terminals of the semiconductor element. | 11-27-2008 |
20080303123 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFINGER - An integrated circuit package system includes: providing a lead terminal; forming a dummy lead near the lead terminal; positioning a base integrated circuit adjacent the lead terminal and the dummy lead; connecting a die connector to the base integrated circuit and the dummy lead; mounting a stackable integrated circuit over the base integrated circuit; and connecting another of the die connector to the stackable integrated circuit and the dummy lead. | 12-11-2008 |
20090001530 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame including inner lead portion having inner leads connected to outer leads and relay inner leads not connected to the outer leads. A semiconductor element is mounted on a lower surface of the lead frame. Electrode pads of the semiconductor element are connected to the inner lead portion via metal wire. One end of the relay inner lead is connected to the electrode pad via the metal wire, and the other end is connected to the outer lead via a relay metal wire disposed to step over the inner lead. | 01-01-2009 |
20090020859 | QUAD FLAT PACKAGE WITH EXPOSED COMMON ELECTRODE BARS - An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. An electronic device with the electronic package is also disclosed. | 01-22-2009 |
20090020860 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads. | 01-22-2009 |
20090026590 | LEADFRAME PANEL - An improved leadframe panel suitable for use in packaging IC dice is described. The described leadframe panel is configured such that the amount of leadframe material that is removed during singulation of the leadframe panel is reduced. | 01-29-2009 |
20090032917 | Lead frame package apparatus and method - The present disclosure relates to a lead frame package comprising a die attach pad and two or more electrical interconnections, wherein at least one of the two or more interconnections is affixed to the die attach pad for electrically grounding the lead frame package. The present disclosure further relates to a method for providing a lead frame package. The lead frame package comprises two or more electrical interconnections and a die attach pad. At least one electrical interconnection is affixed to the die attach pad to ground the lead frame package and at least one of the electrical interconnections is an RF signal interconnection. At least one of the die attach pad and the at least one grounding electrical interconnection is connected to a grounding contact of a circuit-board. The at least one RF signal electrical interconnection is connected to an RF signal contact on the circuit-board, thereby forming a mounted semi-conductor circuit. | 02-05-2009 |
20090045490 | POWER SEMICONDUCTOR MODULE - Included are a semiconductor package, a first bus bar, a second bus bar and a soldering control unit. The semiconductor package includes a power semiconductor element, a first electrode plate and a second electrode plate. The first bus bar is a conductive member which is soldered onto the main surface of the first electrode plate through a first solder member. The second bus bar is a conductive member which is soldered onto the main surface of the second electrode plate through a second solder member. The soldering control unit is provided on each of the main surface of the first bus bar to which the first electrode plate is soldered and the main surface of the second bus bar to which the second electrode plate is soldered, and controls the solder joint thickness. | 02-19-2009 |
20090057852 | THERMALLY ENHANCED THIN SEMICONDUCTOR PACKAGE - A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package. | 03-05-2009 |
20090065913 | CHIP PACKAGE WITH ASYMMETRIC MOLDING - A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate. | 03-12-2009 |
20090072361 | Multi-Chip Stacked Package Structure - A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chip; and a package body encapsulated the first chip, the plurality of metal wires the second chip, the plurality of pads, the first inner leads and the second inner leads and to expose the outer leads. | 03-19-2009 |
20090079048 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDER PADDLE LEADFINGERS - An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle. | 03-26-2009 |
20090085179 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a first and second die pads arranged side by side; a plurality of inner leads arranged around the first and second die pads; first and second chips mounted on the first and second die pads; a bar provided between the first and second chips and the plurality of inner leads, extending in an array direction of the first chip and the second chip; a plurality of wires that connect the first and second chips and the plurality of inner leads and connect the first chip and the second chip; and resin that seals the first and second die pads, the plurality of inner leads, the first and second chips, the plurality of wires and the bar, wherein the bar comprises a mark provided at a position corresponding to an area between the first chip and the second chip in an array direction of the first chip and the second chip. | 04-02-2009 |
20090091009 | STACKABLE INTEGRATED CIRCUIT PACKAGE - A packaged integrated circuit device is disclosed which includes a leadframe comprising a die paddle and a plurality of lead fingers, a plurality of integrated circuit die positioned above the paddle in a stacked arrangement, a plurality of conductive structures for coupling each of the plurality of die to the lead fingers and a body of encapsulant material positioned around the plurality of die and the plurality of conductive structures, wherein the plurality of lead fingers are folded such that a portion of the lead fingers is positioned above the top surface of the body of encapsulant material. A method is also disclosed which includes attaching a first die to a paddle of a leadframe comprising a plurality of lead fingers, positioning at least one additional die above the first die, the first and the at least one additional die being electrically coupled to the plurality of lead fingers, forming a body of encapsulant material around the first die and the at least one additional die and folding the plurality of lead fingers such that a portion of the lead fingers is positioned above a top surface of the body of encapsulant material. | 04-09-2009 |
20090096072 | Package for a power semiconductor device - A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second general plane offset with respect to the first general plane. A molding compound encapsulates the semiconductor die in a form having first, second, third and fourth lateral sides, a top and a bottom. The tie bars are exposed substantially coincident with at least one of the lateral sides. The form includes a discontinuity that extends along the at least one of the lateral sides, the discontinuity increasing a creepage distance measured from the tie bars to the bottom of the package. | 04-16-2009 |
20090108422 | SEMICONDUCTOR DEVICE - The present invention can supply power for each circuit section by separating and connecting bus-bar ( | 04-30-2009 |
20090121329 | LEAD FRAME STRUCTURE AND APPLICATIONS THEREOF - A lead frame structure comprises a side rail, a first paddle, a second paddle, a plurality of leads, and an downset anchor bar. The first paddle is connected to the side rail via at least one first tie bar, and the second paddle is connected to the side rail via at least one-second tie bar. The first paddle and the second paddle separated from each other are used to define an area to support a chip. These leads set on the side rail expends toward to the chip supporting area. One end of the downset anchor bar is connected to the side rail, and the other end of the downset anchor bar has a protrusion portion which is between the first paddle and the second paddle and is downset from the side rail. | 05-14-2009 |
20090152694 | Electronic device - Embodiments provide an electronic device. The electronic device includes a leadframe having a first face that defines an island and multiple leads configured to communicate with a chip attached to the island, a first structure element separate from and coupled to a first face of the leadframe, at least one electrical connector coupled between the chip and the first structure element, and at least one electrical connector coupled between the first structure element and one of the multiple leads. | 06-18-2009 |
20090160038 | Semiconductor package with leads on a chip having multi-row of bonding pads - A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package. | 06-25-2009 |
20090166822 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELDING - An integrated circuit package system comprising: providing an elevated tiebar; forming a die paddle connected to the elevated tiebar; attaching an integrated circuit die over the die paddle adjacent the elevated tiebar; attaching a shield over the elevated tiebar and the integrated circuit die; and forming an encapsulant over a portion of the elevated tiebar, the die paddle, and the integrated circuit die. | 07-02-2009 |
20090212405 | STACKED DIE MOLDED LEADLESS PACKAGE - A stacked die molded leadless package (MLP) stacks two dice and uses leads formed integrally with top and central clips and a leadframe to avoid wire bonding. The central clip leads are source and gate leads leading to source and gate portions of the central clip common to source and gate regions of both dice. The top clip and leadframe are thus connected to the drain regions of the upper and lower dice, the leads of the top clip being drain leads connected to the leadframe leads. The central clip and leadframe leads provide source, gate, and drain terminals in the finished MLP. A method of making the MLP includes flip-chip assembly of the clips, dice, and leadframes in pairs or greater simultaneous quantities. Spacers can be employed between connected components to ensure proper alignment and distribution of bonding material. | 08-27-2009 |
20090236704 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ISOLATED LEADS - An integrated circuit package system comprising: forming a finger; forming a die pad adjacent the finger; applying a fill material around the finger and the die pad; forming a cavity in the finger and fill material; and attaching an integrated circuit die over the die pad adjacent the finger with the fill material. | 09-24-2009 |
20090243057 | Semiconductor Chip Package Assembly Method and Apparatus for Countering Leadfinger Deformation - The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed are improved heat blocks and methods for their use in ensuring adequate clearance between leadfingers and adjacent heat spreaders, as well as semiconductor chip package assemblies wherein a selected clearance between leadfingers and parallel surfaces may be assured. Methods of the invention include steps for supporting the proximal ends of the leadfingers using the wirebonding cavity of a heat block. Thus supported, a plurality of bondwires are attached to couple bond pads of the semiconductor chip to the proximal ends of leadfingers. Thereafter, the clearance between the wirebonded proximal ends of the leadfingers and the adjacent parallel surface of the heat spreader is adjusted using a spacing cavity of the heat block. In preferred embodiments of the invention, a plurality of bondwires couple a plurality of bond pads of the semiconductor chip to the proximal end of a single leadfinger, with assured clearance between the proximal end of the leadfinger and an underlying surface. | 10-01-2009 |
20090243058 | Lead frame and package of semiconductor device - A lead frame including a shield plate, a main frame, interconnection arms, support arms, and terminals is sealed with a resin mold including a base portion for embedding the shield plate and a peripheral wall for embedding the interconnection arms and support arms, thus forming a package base. The interconnection arms and support arms are subjected to bending so as to depress the shield plate in position compared with the main frame. At least one semiconductor chip (e.g. a microphone chip) is mounted on the base portion just above the shield plate. A cover having conductivity is attached onto the main frame exposed on the upper end of the peripheral wall, thus completely producing a semiconductor device encapsulated in a package. A sound hole is formed in the cover or the package base so as to allow the internal space of the package to communicate with the external space. | 10-01-2009 |
20090267202 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip, a number of pads, a number of lead bars and an encapsulation material. The semiconductor chip has an upper surface and an opposite bottom surface. Area of the upper surface exceeds that of the bottom surface. The pads are mounted on the upper surface of the semiconductor chip. The lead bars are located around the semiconductor chip and electrically connected with corresponding pads. The encapsulation material covers the semiconductor chip, the pads, the lead bars and the bonding wires. | 10-29-2009 |
20090283878 | LEAD-ON-CHIP SEMICONDUCTOR PACKAGE AND LEADFRAME FOR THE PACKAGE - A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads. | 11-19-2009 |
20090294934 | CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE - A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers. | 12-03-2009 |
20090294935 | SEMICONDUCTOR PACKAGE SYSTEM WITH CUT MULTIPLE LEAD PADS - A semiconductor package system includes: providing a leadframe having inner frame bars, outer frame bars, a die pad, tiebars, and rows of leads, the inner frame bars being coplanar with outer frame bars; attaching a semiconductor chip to the die pad; attaching bond wires between the semiconductor chip and the rows of leads; encapsulating the semiconductor chip, the bond wires, the inner frame bars, the outer frame bars, the die pad, the tiebars, and the rows of leads in an encapsulant; cutting a groove to remove the inner frame bars; and singulating the leadframe and the encapsulant to remove the outer frame bars. | 12-03-2009 |
20090302443 | LEADFRAME-BASED SEMICONDUCTOR PACKAGE HAVING ARCHED BEND IN A SUPPORTING BAR AND LEADFRAME FOR THE PACKAGE - A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die- bonding plane under the chip is desirably prevented. | 12-10-2009 |
20100001383 | INTEGRATED CIRCUIT PACKAGE WITH MOLDED INSULATION - A variety of improved arrangements and processes for packaging integrated circuits are described. More particularly, methods of encapsulating dice in lead frame based IC packages are described that facilitate covering some portions of the bottom surface of the lead frame while leaving other portions of the bottom surface of the lead frame exposed. In some embodiments, a method of encapsulating integrated circuits mounted on a lead frame panel is described. The lead frame panel includes a plurality of leads having associated contacts and supports. A shim having a plurality of cavities is positioned under the lead frame such that the cavities are adjacent to the supports and not adjacent to the contacts. During the encapsulation process, encapsulant material flows under the supports such that the bottom surfaces of the supports are electrically insulated by the encapsulant while the bottom surfaces of the contacts remain exposed. | 01-07-2010 |
20100109134 | PRE-MOLDED, CLIP-BONDED MULTI-DIE SEMICONDUCTOR PACKAGE - Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDS | 05-06-2010 |
20100117205 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes forming a paddle having a paddle top surface, the paddle top surface having a depression provided therein, forming an external interconnect having a lead tip and a lead body with the lead body having a first recess segment along a length-wise dimension of the lead body, connecting a device over the paddle top surface and the external interconnect, and filling a substantially electrically nonconductive material in the depression. | 05-13-2010 |
20100123226 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane between the leads and the die pad; a plurality of downset tie bars connecting the ground bar with the die pad; a plurality of ground wires bonding to both of the ground bar and the die pad; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound. | 05-20-2010 |
20100148327 | SEMICONDUCTOR DIE PACKAGE WITH CLIP INTERCONNECTION - A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on the die attach pad of the leadframe structure. The first surface is proximate the die attach pad. The semiconductor die package further includes a clip structure comprising a first interconnect structure and a second interconnect structure, the first interconnect structure comprising a planar portion and a protruding portion, the protruding portion including an exterior surface and side surfaces defining the exterior surface. The protruding portion extends from the planar portion of the first interconnect structure. The second surface of the semiconductor die is proximate to the clip structure, and a molding material covers at least the semiconductor die and at least a portion of the side surfaces of the protruding portion. | 06-17-2010 |
20100207260 | QUAD FLAT PACKAGE WITH EXPOSED COMMON ELECTRODE BARS - An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed. | 08-19-2010 |
20100213587 | ELECTRONIC DEVICE - One embodiment provides a semiconductor assembly including a printed circuit board and a semiconductor package. The semiconductor package includes a lead frame having a die pad and a plurality of leads spaced from the die pad, a chip attached to the die pad on a front face of the lead frame, at least one electrically conductive structure element mechanically coupled to but electrically isolated from the front face of the lead frame, at least one connector electrically connecting the chip to the structure element, at least one connector electrically connecting the structure element to at least one of the leads, and a mold material encasing the semiconductor package except for an end portion of the leads which are electrically connected to the printed circuit board. | 08-26-2010 |
20100237478 | Lead frame and semiconductor package having the same - Provided is a lead frame that may include a frame, a lead structure, and a dam bar. The frame may include a plurality of openings configured to receive semiconductor chips. The lead structure may be in the openings. The lead structure may also include inner leads and outer leads. The inner leads may be configured to electrically connect to the semiconductor chips and the outer leads may extend from the inner leads. In example embodiments, the lead structure may extend in a first direction. The dam bar may be arranged between the inner leads and the outer leads. In accordance with example embodiments, the dam bar may extend along a second direction which is substantially perpendicular to the first direction. In example embodiments, the dam bar may have a first strength-reinforcing portion extending along the second direction. Also provided is a semiconductor package having the lead frame. | 09-23-2010 |
20100244210 | LEAD FRAME AND METHOD FOR MANUFACTURING CIRCUIT DEVICE USING THE SAME - Provided are: a lead frame enabling efficient manufacturing of multiple circuit devices; and a method for manufacturing a circuit device using the same. In the lead frame of the present invention, units are arranged and frame-shaped first and second supporters are provided around the units to mechanically support the units. Moreover, a half groove is provided in the first supporter at a portion on an extended line of a dividing line defined at a boundary between each adjacent two of the units. Furthermore, a penetration groove penetrating a part of the second supporter at a portion on an extended line of another dividing line is provided. | 09-30-2010 |
20100264527 | Stacked Chip Package Structure with Leadframe Having Bus Bar - The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad. | 10-21-2010 |
20100289128 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND TRANSPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: conductively bonding a first surface of a transposer to an inner end of a lead separate from the transposer; conductively bonding a die to the first surface of the transposer; and encapsulating the inner end with a mold compound having a bottom mold surface that is exposed and is coplanar with a surface of the transposer opposite the first surface. | 11-18-2010 |
20100314729 | Stacked Chip Package Structure with Leadframe Having Inner Leads with Transfer Pad - The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offest chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer. | 12-16-2010 |
20110062567 | LEADFRAME AND CHIP PACKAGE - A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation. | 03-17-2011 |
20110108963 | Package for a power semiconductor device - A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second general plane offset with respect to the first general plane. A molding compound encapsulates the semiconductor die in a form having first, second, third and fourth lateral sides, a top and a bottom. The tie bars are exposed substantially coincident with at least one of the lateral sides. The form includes a discontinuity that extends along the at least one of the lateral sides, the discontinuity increasing a creepage distance measured from the tie bars to the bottom of the package. | 05-12-2011 |
20110140249 | TIE BAR AND MOLD CAVITY BAR ARRANGEMENTS FOR MULTIPLE LEADFRAME STACK PACKAGE - A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes. | 06-16-2011 |
20110140250 | LEADFRAME FOR SEMICONDUCTOR PACKAGE - A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness. | 06-16-2011 |
20110163427 | METHOD AND APPARATUS FOR DIRECTING MOLDING COMPOUND FLOW AND RESULTING SEMICONDUCTOR DEVICE PACKAGES - Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice. | 07-07-2011 |
20110204498 | LEAD FRAME AND SEMICONDUCTOR PACKAGE MANUFACTURED THEREWITH - A lead frame for a semiconductor package has a flag to which a semiconductor die is mounted. Tie bars are coupled to the flag. There is a first set of leads and each first set lead in the first set of leads has a first set lead parallel length and a first set lead tapered length. The first set lead parallel length of each first set lead has a constant width and edges that are parallel to edges of all other first set lead parallel lengths. A free end region of the first set lead tapered length of each first set lead provides a first set lead bond target region. There is a second set of leads disposed between a first one of the tie bars and the first set of leads. Each second set lead, in the second set of leads, has a second set lead parallel length and a second set lead tapered length. The second set lead parallel length of each second set lead has a constant width and edges that are parallel to edges of all other second set lead parallel lengths in the second set of leads and also parallel to the edges of first set lead parallel lengths. At least one second set lead has an extension length extending inwardly from the second set lead tapered length, the extension length has a constant width and provides a second set lead bond target region. Wire bond leads electrically couple both the first set lead bond target region and second set lead bond target region to respective die external electrical connection pads on a surface of the die and a package body encloses the die. | 08-25-2011 |
20110227205 | MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION - The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume. | 09-22-2011 |
20110241189 | APPARATUS FOR AND METHODS OF ATTACHING HEAT SLUGS TO PACKAGE TOPS - A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more passes across the frame, wherein the one or more passes are parallel. A method of attaching heat slug pads to packages includes gathering a plurality of packages, preparing a heat slug frame including a N×M matrix of heat slug pads, dispensing thermally conductive material onto surfaces of the heat slug pads, attaching the plurality of packages onto the heat slug pads, and singulating the heat slug pads, wherein the singulating step consists of one or more parallel passes across the N×M matrix. A method of attaching heat slug foil to packages includes preparing a plurality of packages, laminating the heat slug foil to one side of the plurality of packages using thermally conductive material, and singulating the plurality of packages. | 10-06-2011 |
20110260305 | Power Semiconductor Device Packaging - A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity. | 10-27-2011 |
20110266661 | LEAD FRAME AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor device is manufactured using a lead frame for a mold array package (MAP) where multiple mount parts are arranged in the shape of an array, each configured to have a semiconductor chip mounted thereon. Multiple leads for coupling to the semiconductor chip are formed in each of the mount parts of the lead frame. The tips of the leads are mutually coupled by tie bars thinner than the leads. A dummy lead having a slot coupling to the tie bar is formed on a portion corresponding to a portion further outside the tie bar and corresponding to a portion where the lead is formed in the mount parts at predetermined locations among the mount parts. Once the resin is supplied, air in a tie bar part is pushed out into the slot of the dummy lead; therefore, generation of void in the tie bar part can be controlled. | 11-03-2011 |
20120018862 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane between the leads and the die pad; a plurality of downset tie bars connecting the ground bar with the die pad; a plurality of ground wires bonding to both of the ground bar and the die pad; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound. | 01-26-2012 |
20120104579 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK - An integrated circuit package system includes an external interconnect having a lead tip and a lead body, including a recess in the lead body including a first recess segment, having an orientation substantially parallel to the lengthwise dimension of the lead body, and a second recess segment intersecting and perpendicular to the first recess segment along a lead body top surface of the lead body, the first recess segment at a bottom portion of the second recess segment; an internal interconnect between an integrated circuit die and the external interconnect; and an encapsulation to cover the external interconnect with the recess filled. | 05-03-2012 |
20120112331 | Dual Lead Frame Semiconductor Package and Method of Manufacture - A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time. | 05-10-2012 |
20120126384 | PACKAGE STRUCTURE - The present invention employs tie bar(s) of a lead frame as contact(s) so as to increase the number of contacts in a package structure. Therefore, a die can be packaged in a package structure with a smaller dimension to lower packaging cost of an integrated circuit. | 05-24-2012 |
20120146200 | PRE-BONDED SUBSTRATE FOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING THE SAME - A substrate and a method of making thereof are disclosed. The substrate comprises an electrically conductive leadframe, the leadframe having a plurality of lands on a first side of the leadframe with a first recessed portion between the lands, and a plurality of routing leads on an opposing second side of the leadframe with a second recessed portion between the routing leads. The substrate also comprises a first bonding compound filling the first recessed portion. In one embodiment, the substrate also comprises a support material attached to the first bonding compound for holding the leadframe together. In another embodiment, the substrate comprises a second bonding compound filling the second recessed portion. | 06-14-2012 |
20120241929 | LEADFRAME-BASED MOLD ARRAY PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR - A heat spreader frame is provided including: heat spreaders having upper surfaces; a peripheral frame surrounding the heat spreaders; spreaders, the peripheral frame having stand-off legs; tie bars having upper surfaces and a pin identifier at an end portion of the tie bars, the heat spreaders connected to one another and to the peripheral frame by the tie bars, the width of the stand-off legs wider than widths of the tie bars; at least portions of the upper surfaces of the tie bars being thinned to reduce heights of the tie bars; the upper surfaces of the heat spreader in an elevated position supported by the peripheral frame; and the heat spreaders and the tie bars covered by an package molding compound exposing the upper surface of the heat spreaders and one surface of the pin identifier coplanar to the upper surfaces of the heat spreaders. | 09-27-2012 |
20120286407 | Semiconductor Device and Method of Forming Leadframe with Conductive Bodies for Vertical Electrical Interconnect of Semiconductor Die - A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die. | 11-15-2012 |
20130009294 | MULTI-CHIP PACKAGE HAVING LEADERFRAME-TYPE CONTACT FINGERS - Disclosed is a multi-chip package having leadframe-type contact fingers, primarily comprising a leadframe, a non-conductive tape, a first chip and a second chip disposed on the first chip. The leadframe includes a die paddle on which the first chip is disposed and a plurality of first contact fingers, moreover, at least a second contact finger is integrally extended from the die paddle and is located among the first contact fingers so that the first and second contact fingers are arranged in a row. The non-conductive tape is attached onto the first and second contact fingers conforming to the arranging row of the first contact fingers so that the second contact finger is mechanically fastened with the first contact fingers. An encapsulant encapsulates the first chip, the second chip and the non-conductive tape with a plated metal layer formed on the bottom surfaces of the first and second contact fingers and exposed from the encapsulant. Accordingly, delamination of the conventional substrate or a die paddle can be avoided and the amount of tie bars used can be decreased. | 01-10-2013 |
20130049180 | QFN DEVICE AND LEAD FRAME THEREFOR - A lead frame for a quad flat no-lead (QFN) type semiconductor device package includes a die pad, a plurality of leads that surround the die pad. The outer edge of leads includes a channel that extends from a lower surface to an upper surface of the leads. A semiconductor die is attached to the die pad. An inner edge of each lead is electrically connected to a corresponding bonding pad on the semiconductor die. The assembly is covered with an encapsulation material except that the outer edge of each lead and the corresponding channel are exposed. The channel allows solder to flow up the outer edge of a lead when the QFN device is soldered to a substrate, which improves the ability to perform visual inspection of the solder-lead connection. | 02-28-2013 |
20130075881 | MEMORY CARD PACKAGE WITH A SMALL SUBSTRATE - Disclosed is a memory card package with a small substrate by using a metal die pad having an opening to substitute the chip-carrying function of a conventional substrate so that substrate dimension can be reduced. A substrate is attached under the metal die pad. A first chip is disposed on the substrate located inside the opening. A second chip is disposed on the metal die pad without covering the opening. A card-like encapsulant encapsulates the metal die pad, the top surface of the substrate, the first chip, and the second chip. The dimension of the substrate is smaller than the dimension of the encapsulant. The substrate has a lumpy sidewall encapsulated by the encapsulant so that the bottom surface of the substrate is coplanar with a bottom side of the encapsulant to increase the adhesion between the substrate and the encapsulant. | 03-28-2013 |
20130234306 | LEAD FRAME FOR ASSEMBLING SEMICONDUCTOR DEVICE - A lead frame has a flag, a peripheral frame, and main tie bars coupling the flag to the peripheral frame. At least one cross tie bar extends between two of the main tie bars and an inner row of external connector pads extending from an inner side of the cross tie bar and an outer row of external connector pads extending from an outer side of the cross tie bar. Both an inner non-electrically conductive support bar and an outer non-electrically conductive support bar are attached across the two of the main tie bars. The inner non-electrically conductive support bar is attached to upper surfaces of the two of the main tie bars and to upper surfaces of the inner row of the external connector pads. | 09-12-2013 |
20130249067 | Clip Frame Semiconductor Packages and Methods of Formation Thereof - In one embodiment, a semiconductor package includes a clip frame with a first clip having a first support structure, a first lever, and a first contact portion, which is disposed on a front side of the semiconductor package. The first support structure is adjacent an opposite back side of the semiconductor package. The first lever joins the first contact portion and the first support structure. A first die is disposed over the first support structure of the first clip. The first die has a first contact pad on the front side of the semiconductor package. An encapsulant material surrounds the first die and the first clip. | 09-26-2013 |
20130256852 | Stacked Semiconductor Package - A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed. | 10-03-2013 |
20130270683 | SEMICONDUCTOR PACKAGES WITH HEAT DISSIPATION STRUCTURES AND RELATED METHODS - Semiconductor packages including a die pad, at least one connecting bar, at least one supporting portion, a plurality of leads, a semiconductor chip, a heat sink and a molding compound. The connecting bar connects the die pad and the supporting portion. The leads are electrically isolated from each other and the die pad. The semiconductor chip is disposed on the die pad and electrically connected to the leads. The heat sink is supported by the supporting portion. The molding compound encapsulates the semiconductor chip and the heat sink. Heat from the semiconductor chip is efficiently dissipated from the die pad through the connecting bar, through the supporting portion, and through the heat sink. | 10-17-2013 |
20140070386 | Semiconductor Package with Connecting Plate for Internal Connection - A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding. | 03-13-2014 |
20140145318 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package. | 05-29-2014 |
20140264795 | NO-EXPOSED-PAD QUAD FLAT NO-LEAD (QFN) PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed on the metal substrate, and extending to the proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads. | 09-18-2014 |
20140299978 | QUAD FLAT NON-LEAD PACKAGE - A quad flat non-lead package includes a chip, a chip carrier including a bearing surface adapted for the mounting of the chip, a plurality of leads mounted around the chip carrier and electrically connected to the chip, each lead having an opening located in an outer edge of a rear end thereof, and a molding compound formed on the chip, the chip carrier and the leads by compression molding to let the opening of each lead be exposed to the outside. The design of the openings of the leads can provide more tin-climbing area to improve soldering quality and yield, thereby lowering the manufacturing cost and facilitating testing after the soldering process. The invention also provides a lead frame for quad flat non-lead package. | 10-09-2014 |
20140319663 | LEAD FRAME, METHOD FOR MANUFACTURING LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region. | 10-30-2014 |
20140327122 | MICRO LEAD FRAME STRUCTURE HAVING REINFORCING PORTIONS AND METHOD - In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes. | 11-06-2014 |
20140332939 | Dual Lead Frame Semiconductor Package and Method of Manufacture - A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing dine. | 11-13-2014 |
20140339691 | SEMICONDUCTOR DEVICE HAVING A PLURALITY OF CIRCUITS ARRANGED ON A SIDE OF A SEMICONDUCTOR CHIP - A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group. | 11-20-2014 |
20140374890 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1. | 12-25-2014 |
20150014831 | SEMICONDUCTOR DEVICE WITH CORNER TIE BARS - A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process. | 01-15-2015 |
20150061094 | CAVITY PACKAGE WITH PRE-MOLDED CAVITY LEADFRAME - A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow. | 03-05-2015 |
20150084169 | SEMICONDUCTOR PACKAGE WITH STRESS RELIEF AND HEAT SPREADER - A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle. | 03-26-2015 |
20150325503 | Method of singularizing packages and leadframe - A method of singularizing a matrix array of packages is provided, wherein the method comprises providing a matrix array of packages, wherein the matrix array is formed on a leadframe; cutting predefined leads of the leadframe by a punching process; and singularizing the packages of the matrix array of packages by a sawing process. | 11-12-2015 |
20150332989 | GANG CLIPS HAVING DISTRIBUTED-FUNCTION TIE BARS - Gang clips ( | 11-19-2015 |
20150340304 | Power Semiconductor Package - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 11-26-2015 |
20160056097 | SEMICONDUCTOR DEVICE WITH INSPECTABLE SOLDER JOINTS - A Quad Flat Non-leaded (QFN) semiconductor die package has a semiconductor die mounted on a die flag of a lead frame. A covers the semiconductor die. The housing has a base and sides. There are electrically conductive mounting feet, each of which has an exposed base portion in the base of the housing and an exposed side portion in the one of the sides of the housing. Bond wires electrically connect electrodes of the semiconductor die to respective ones of the mounting feet. | 02-25-2016 |
20160093559 | SEMICONDUCTOR PACKAGE WITH SMALL GATE CLIP AND ASSEMBLY METHOD - A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads. | 03-31-2016 |
20160104663 | PATTERNED LEAD FRAME - A lead frame having a plurality of concentric lead frame rings configured to receive and support a variety of integrated circuit die having a variety of sizes. The rings are separated from each other by gaps and coupled together by a plurality of tie bars. The concentric rings may be circular or rectangular. The tie bars may extend diagonally from the rings or perpendicularly to the rings. | 04-14-2016 |
20160141230 | SEMICONDUCTOR DEVICE AND LEAD FRAME HAVING VERTICAL CONNECTION BARS - A semiconductor device includes a lead frame having a die support area and a plurality of inner and outer row leads surrounding the die support area, and a semiconductor die mounted on the die support area and electrically connected to the leads with bond wires. A molding material encapsulates the semiconductor die, the bond wires, and the leads, and defines a package body. The semiconductor device further includes connection bars extending vertically from the leads to a top surface of the package body. The connection bars connect the inner row leads to respective ones of the outer row leads before the molding process is performed. | 05-19-2016 |
20160379918 | SEMICONDUCTOR PACKAGE WITH SMALL GATE CLIP AND ASSEMBLY METHOD - A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads. | 12-29-2016 |