| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257669000 | With stress relief | 62 |
| 20080203547 | INSERT MOLDED LEADFRAME ASSEMBLY - An insert molded leadframe assembly (IMLA) for an electrical connector is disclosed. The IMLA may include an array of electrically conductive contacts, a dielectric leadframe housing overmolded onto the array of contacts, and a mass disposed within the leadframe housing. The additional mass may shift the IMLA's center of gravity, thereby providing a counterbalance to a non-proportional ball-grid array connector. | 08-28-2008 |
| 20080217751 | SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor element mounting substrate | 09-11-2008 |
| 20080224282 | Semiconductor device and method of manufacturing the same - A technique for preventing cracks and residual resin on a semiconductor chip in a molding process in the assembly of semiconductor devices is provided. A distance from a bottom surface of a cavity of a lower mold die to a ceiling surface of a cavity of an upper mold die of a resin molding die is made same as or smaller than a distance from a lower surface of a die pad to an upper surface of a plate terminal, and an U-shape elastic body is arranged on semiconductor elements between the plate terminal and the die pad, thereby mitigating a load due to a clamp pressure of mold dies in the molding process by an elastic deformation of the elastic body. Consequently, a load applied on the semiconductor devices is reduced, thereby preventing formation of cracks on the semiconductor elements. | 09-18-2008 |
| 20080296746 | LEAD FRAME AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has a hanging lead piece that supports the mounting portions and an electrode connection piece that connects the plurality of electrodes, and a half-blanking portion that has a concave portion formed in a thickness direction of the lead frame and a protrusion formed at a position corresponding to the concave portion, and which is covered with a sealing resin material that seals the semiconductor element. A stress-dispersing portion for dispersing stress that arises, when the half-blanking portion is formed, is provided in the corner portion. | 12-04-2008 |
| 20090051016 | ELECTRONIC COMPONENT WITH BUFFER LAYER - An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an entire bottom surface of the semiconductor chip. | 02-26-2009 |
| 20090072360 | Molded semiconductor device including IC-chip covered with conductor member - A semiconductor device according to the present invention includes a conductor member, an IC-chip and leads, all molded together with a resin mold. The conductor member is composed of a base portion on which the IC-chip is mounted, a cover portion for covering a functioning surface of the IC-chip, and a bent portion connecting the cover portion to the base portion. The base portion includes a lead portion that is grounded. The cover portion and the base portion are positioned substantially in parallel to each other, and the IC-chip is disposed in an inner space between the cover portion and the base portion. The lead portion to be grounded and the leads electrically connected to the IC-chip extend out of the resin mold. Since the IC-hip is disposed in the inner space of the conductor member that is grounded, the IC-chip is protected from the electromagnetic noises and from electrostatic charges otherwise accumulated in the resin mold. | 03-19-2009 |
| 20090108421 | APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES - An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. | 04-30-2009 |
| 20090146275 | LEAD FRAME AND SEMICONDUCTOR DEVICE PROVIDED WITH LEAD FRAME - A lead frame and a semiconductor device having a lead frame are disclosed. The lead frame is provided with a mount bed to mount a semiconductor chip, first and second lead terminals and first and second extension portions of band-shapes. The first and the second extension portions extend from sides of the first and second lead terminals and are bent. An electronic component is attached to Tip portions of the first and the second extension portions with connection conductors interposed in between. | 06-11-2009 |
| 20090179313 | FLEX CLIP CONNECTOR FOR SEMICONDUCTOR DEVICE - A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure. | 07-16-2009 |
| 20090230521 | Stress Mitigation in Packaged Microchips - A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity and contacting the die. The packaged microchip also has mold material substantially encapsulating part of the top surface of the portion of the lead frame. | 09-17-2009 |
| 20100013067 | Stress Mitigation in Packaged Microchips - A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus. | 01-21-2010 |
| 20100072585 | TOP EXPOSED CLIP WITH WINDOW ARRAY - A clip for a semiconductor device package may include a metal sheet including an array of windows and one or more conductive fingers. Each of the conductive fingers has a first end and a second end. The first end is electrically connected to the metal sheet at one of the windows. Each of the conductive fingers is adapted to provide electrical connection to a top semiconductor region of a semiconductor device or a lead frame at the second end. | 03-25-2010 |
| 20100133669 | CRACK STOPPING STRUCTURE AND METHOD FOR FABRICATING THE SAME - A crack stopping structure is disclosed. The crack stopping structure includes a semiconductor substrate having a die region, a die seal ring region, and a scribe line region; a metal interconnect structure disposed on the semiconductor substrate of the scribe line region; and a plurality of dielectric layers disposed on the semiconductor substrate of the die region, the die seal ring region, and the scribe line region. The dielectric layers include a first opening exposing the surface of the metal interconnect structure of the scribe line region and a second opening exposing the dielectric layer adjacent to the metal interconnect structure such that the metal interconnect structure and the exposed portion of the dielectric layer form a step. | 06-03-2010 |
| 20110062566 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS - A semiconductor device comprising: a substrate; a terminal on the substrate's first surface; a first electrode on the first surface connected to the terminal; an electronic element on the substrate's second surface; a second electrode connected to the electronic element; a groove on the second surface leading to the second electrode; a conductive portion inside the grove connected to the second electrode's rear face; a first wiring on the first surface connected to the first electrode; a second wiring connecting the first wiring and the terminal; a stress-absorbing layer between the substrate and terminal; a land connecting the first wiring and the second wiring, the land opening a part of the stress-absorbing layer and exposing the first wiring, the land being in a region surrounded by terminals, and the land being along a straight line connecting the centers of diagonal terminals, with the region between the terminals. | 03-17-2011 |
| 20110068444 | Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP - A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer. | 03-24-2011 |
| 20110084370 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 04-14-2011 |
| 20110089545 | APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES - An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. | 04-21-2011 |
| 20110101511 | POWER SEMICONDUCTOR PACKAGE - The present invention features a power semiconductor package and a method of forming the same that includes forming, in the body, a stress relief region disposed between a pair of mounting regions and attaching a semiconductor die in each of the mounting regions. The semiconductor die has first and second sets of electrical contacts with the first set being on a first surface of the semiconductor die and the second set being disposed upon a second surface of the semiconductor die opposite to the first surface. The first set is in electrical communication with the mounting region. Walls are formed on outer sides of the pair of mounting regions, defining a shaped body, with the shaped body and walls defining an electrically conductive path that extends from the first set and terminates on side of the package common with the second set. | 05-05-2011 |
| 20110133319 | AUXILIARY LEADFRAME MEMBER FOR STABILIZING THE BOND WIRE PROCESS - A semiconductor package comprises a die attach pad and an auxiliary support member at least partially circumscribing the die attach pad. A set of contact leads is formed extending outward from the die attach pad. A first set of contact pads is formed on the bottom surface of the distal ends of the contact leads. An optional second set of contact pads is formed at the bottom surface of the proximal end. The auxiliary support member prevents damage to the contact leads and prevents the leads from bending during the manufacturing process. | 06-09-2011 |
| 20110180914 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die. | 07-28-2011 |
| 20110204497 | Semiconductor integrated circuit and method for manufacturing the same - A semiconductor integrated circuit having a semiconductor chip mounted over a tape- or film-like substrate, the semiconductor integrated circuit having a higher strength against bending, as well as a method for manufacturing the semiconductor integrated circuit, are disclosed. The semiconductor integrated circuit comprises a bendable tape-like substrate, the tape-like substrate including external terminals, internal terminals provided for coupling to a rectangular semiconductor chip, and wiring lines for coupling the internal terminals and the external terminals with each other; and a reinforcing member for reinforcing the semiconductor chip over the tape-like substrate in a longitudinal direction of the semiconductor chip, the semiconductor chip and the reinforcing member being sealed with resin. | 08-25-2011 |
| 20110233743 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view. | 09-29-2011 |
| 20110233744 | INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a leadframe; forming a protruding pad on the leadframe; attaching a die to the leadframe; electrically connecting the die to the leadframe; and encapsulating at least portions of the leadframe, the protruding pad, and the die in an encapsulant. | 09-29-2011 |
| 20120061811 | APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES - An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a heat sink plate and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the heat sink plate. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. | 03-15-2012 |
| 20130015565 | SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE ARRAY AND SEMICONDUCTOR DEVICE HAVING THE SAME - A substrate structure has a first surface and a second surface. A plurality of carrying members are formed on the first surface and a plurality of conductive traces are formed on the second surface. In addition, the substrate structure has a first, a second and a third thermal stress relief structures. The first thermal stress relief structure is that lengths of the substrate structure in different axial directions are substantially equal to each other. The second thermal stress relief structure is that a plurality of separated alignment marks are formed on the substrate structure. The third thermal stress relief structure is that the substrate structure has at least one clearance area extending along one of the axial directions of the substrate structure and the clearance area has no carrying members and no conductive traces formed thereon. | 01-17-2013 |
| 20130056860 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE - According to one embodiment, a resin-encapsulated semiconductor includes a base a semiconductor chip provided on the base, stress relief members provided on the base and out side semiconductor chip, and each of the stress relief members relieving stress applied to the semiconductor chip. | 03-07-2013 |
| 20130168839 | APPARATUS FOR INTEGRATED CIRCUIT PACKAGING - Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board. | 07-04-2013 |
| 20130221505 | PRINTED WIRING BOARD - A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup. | 08-29-2013 |
| 20130228906 | INTERCONNECT FOR AN OPTOELECTRONIC DEVICE - Interconnects for optoelectronic devices are described. For example, an interconnect for an optoelectronic device includes an interconnect body having an inner surface, an outer surface, a first end, and a second end. A plurality of bond pads is coupled to the inner surface of the interconnect body, between the first and second ends. A stress relief feature is disposed in the interconnect body. The stress relief feature includes a slot disposed entirely within the interconnect body without extending through to the inner surface, without extending through to the outer surface, without extending through to the first end, and without extending through to the second end of the interconnect body. | 09-05-2013 |
| 20130328179 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTING MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone. | 12-12-2013 |
| 20140021594 | Packaging Structures and Methods for Semiconductor Devices - Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate. | 01-23-2014 |
| 20140027890 | Low Stress Package For an Integrated Circuit - A package that electrically connects an integrated circuit to a printed circuit board includes a frame and a package body that encases a portion of the frame and the integrated circuit. The frame includes a mounting region that is connected to the printed circuit board, and a cantilevering region that cantilevers away from the mounting region. The cantilevering region retains the integrated circuit in a flexible fashion. | 01-30-2014 |
| 20140054758 | STACKED DUAL CHIP PACKAGE HAVING LEVELING PROJECTIONS - The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication. | 02-27-2014 |
| 20140091444 | SEMICONDUCTOR UNIT AND METHOD FOR MANUFACTURING THE SAME - A semiconductor unit includes a base, an insulating substrate bonded to the base, a conductive plate made of a metal of poor solderability, a semiconductor device mounted to the insulating substrate through the conductive plate, and a metal plate interposed between the conductive plate and the semiconductor device and made of a metal of good solderability as compared to the metal used for the conductive plate. The base, the insulating substrate, the conductive plate and the metal plate are brazed together, and the semiconductor device is soldered to the metal plate. | 04-03-2014 |
| 20140124911 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region. | 05-08-2014 |
| 20140131846 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion. | 05-15-2014 |
| 20140145317 | ELECTRONIC COMPONENT DEVICE - A wiring board includes a wiring forming region in which a plurality of wiring layers are stacked while sandwiching insulating layers, an outer periphery region which is arranged around the wiring forming region and in which a reinforcing pattern is formed in the same layer as each of the wiring layers. An area ratio of the reinforcing pattern to the outer periphery region and an area ratio of the wiring layer to the wiring forming region are substantially the same in each of the layers, and the reinforcing patterns exist without a gap in the outer periphery region when the wiring board is viewed in planar perspective. | 05-29-2014 |
| 20140159214 | LOW COST REPACKAGING OF THINNED INTEGRATED DEVICES - A method for mounting and embedding a thinned integrated circuit within a substrate is provided. In one embodiment, the thinned integrated circuit can receive one or more biasing substrate layers on a first surface of the thinned integrated circuit. When the thinned integrated circuit is embedded within a supporting substrate, such as a printed circuit board, the biasing substrate layers can position the thinned integrated circuit toward a centerline of the printed circuit board. Positioning the thinned integrated circuit toward the centerline can increase the resistance to breakage. | 06-12-2014 |
| 20140167235 | SEMICONDUCTOR MODULE - A semiconductor module has a metallic base plate; an insulated circuit board fixed on the metallic base plate; a semiconductor element mounted on the insulated circuit board; a resin case to house the semiconductor element, and having an upper surface with an opening; a terminal exposed from the opening of the resin case to an outer portion in a vertical direction; and an insulating holding piece having a triangular or a rectangular cross-section and one surface contacting the terminal. The terminal has a projecting portion disposed inside the resin case to restrict a movement of the terminal in the vertical direction. The resin case has a first recess portion to fit the projecting portion and a second recess portion disposed on the upper surface of the resin case so that the holding piece pushes the projecting portion on the terminal toward the first recess portion for insertion. | 06-19-2014 |
| 20140191379 | LOW-K CHIP PACKAGING STRUCTURE - A low-k chip packaging structure comprising chip body I ( | 07-10-2014 |
| 20140246765 | PRINTED WIRING BOARD - A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup layer laminated on first surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on second surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost interlayer resin insulation layer of the first buildup layer has thermal expansion coefficient which is set lower than thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer. | 09-04-2014 |
| 20140252576 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor device has a packaging structure in which a top surface of a semiconductor chip | 09-11-2014 |
| 20140306329 | SEMICONDUCTOR PACKAGE - A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing 98 wt % or more of one metallic element such as silver having a melting point of 400° C. or higher, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members. | 10-16-2014 |
| 20140312479 | ESCAPE ROUTES - Methods of and devices for providing escaping routes for the flux and gases generated to move away from the solder joint in the process of solder joint formation. | 10-23-2014 |
| 20150084168 | PACKAGE ENCAPSULANT RELIEF FEATURE - A microelectronic device package including a package substrate, microelectronic component disposed on a first surface of a first portion of the substrate, and encapsulant material surrounding the microelectronic electronic component. An exposed surface of the first portion of the substrate is exposed through an opening in a first major surface of the encapsulant material. The exposed surface of the first portion has an edge. Encapsulant material is adjacent to the edge at the first major surface. The exposed surface is opposite the first surface. A stress relief feature located in one of the first major surface or a second major surface of the encapsulant material. The second major surface is opposite the first major surface. The stress relief feature reduces an amount of the encapsulant material and is 1 mm or less of a plane of the edge of the exposed surface. The plane is generally perpendicular to the exposed surface. | 03-26-2015 |
| 20150108624 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group. | 04-23-2015 |
| 20150348916 | RING STRUCTURES IN DEVICE DIE - A die includes a metal pad, a passivation layer over the metal pad, and a polymer layer over the passivation layer. A metal pillar is over and electrically coupled to the metal pad. A metal ring is coplanar with the metal pillar. The polymer layer includes a portion coplanar with the metal pillar and the metal ring. | 12-03-2015 |
| 20150371933 | MICRO LEAD FRAME STRUCTURE HAVING REINFORCING PORTIONS AND METHOD - In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes. | 12-24-2015 |
| 20150380362 | LEAD FINGER LOCKING STRUCTURE - Various aspects are directed to apparatuses, systems and related methods involving the mitigation of issues relating to thermal expansion and contraction of lead fingers of an integrated circuit package. Consistent with one or more embodiments, lead fingers on a leadframe substrate each have a locking structure that secures the lead finger in place relative to the substrate. The lead fingers provide a location to attach a bond wire to an integrated circuit, and connect the bond wire to terminals at a perimeter of the leadframe. The locking structure and arrangement of the lead fingers mitigate issues such as cracking or breaking of a solder connection of the bond wire to the leadframe, which can occur due to thermal expansion and contraction. | 12-31-2015 |
| 20160005681 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a frame formed of a metal and including multiple grooves formed in a surface, and, a semiconductor chip connected with the surface of the frame. A semiconductor device includes the semiconductor chip, and a base frame formed of copper and bonded to the bottom face of the semiconductor chip. In addition, the semiconductor chip and the base frame are bonded together by surface activation. | 01-07-2016 |
| 20160013139 | Semiconductor Structure and Method of Fabricating the Same | 01-14-2016 |
| 20160043023 | SYSTEM AND METHOD FOR METAL MATRIX MOUNTING SCHEME - An integrated circuit assembly element formed via an additive manufacturing technique, such as mixing a conductive material with a memory metal to form a portion of a substrate in desired locations, such as along the footprint of die, are discussed herein. In operation (e.g. in response to thermal cycling of the assembly) the memory metal contracts while the conductive material expands. The result is an element having reduced thermal expansion, which can be net zero coefficient of thermal expansion and/or be catered to the coefficient of thermal expansion of a desired material, such as the silicon die. | 02-11-2016 |
| 20160043041 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate dudes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die. | 02-11-2016 |
| 20160079186 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - There is provided a technology by which the position of 1 pin in a tabless package can be recognized easily. The rear surfaces of plural leads are exposed on a rear surface of a resin-sealed body which seals a semiconductor chip etc., a image recognition area is further provided adjacent to 1 pin (lead with index 1), and a rear surface of an identification mark is exposed from the rear surface of the resin-sealed body of the image recognition area. This identification mark is made of the same conductive member as the plural leads. | 03-17-2016 |
| 20160086893 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar, wherein the elastic modulus of the substrate is of about 3 to about 10 GPa at about 20 to about 30° C. and of about 1 to about 5 GPa at about 250 to about 270° C. | 03-24-2016 |
| 20160111379 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a lower surface bonded to an insulating substrate side, and a plate-shaped lead terminal bonded to an upper surface of the semiconductor element, and having a horizontally extending portion. The horizontally extending portion in the lead terminal is bonded to the semiconductor element and includes a linearly extending portion in a planar view. The semiconductor device further includes a sealing resin that seals the semiconductor element together with the linearly extending portion in the lead terminal. A linear expansion coefficient of the sealing resin shows a value intermediate between a linear expansion coefficient of the lead terminal and a linear expansion coefficient of the semiconductor element, and the lead terminal includes a recess or a projection to horizontally and partially separate the linearly extending portion into parts. | 04-21-2016 |
| 20160118349 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces. | 04-28-2016 |
| 20160126167 | SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MODULE, AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE - A semiconductor module is configured such that heat radiation substrates are connected to lead frames and semiconductor chips are directly connected to the lead frames, so that the semiconductor chips are not connected to the lead frames through conductive portions of the heat radiation substrates. Therefore, the conductive portions can have a solid shape without being divided. As such, an occurrence of curving of the heat radiation substrates is suppressed when a temperature is reduced from a high temperature to a room temperature after resin-sealing at the high temperature or the like. Therefore, connection between the semiconductor chip and the lead frames and connection between the lead frames and the heat radiation substrates enhance. | 05-05-2016 |
| 20160133549 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion. | 05-12-2016 |
| 20160155710 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | 06-02-2016 |
| 20160181183 | METHOD FOR PREVENTING DIE PAD DELAMINATION | 06-23-2016 |
| 20160204046 | SEMICONDUCTOR DEVICE | 07-14-2016 |
