Entries |
Document | Title | Date |
20080237815 | TAPE CARRIER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A tape carrier includes: a base film with insulating property; a wiring pattern provided on the base film within a product region, the product region being demarcated by a cutting line so as to divide the tape carrier into individual products by cutting along the tape carrier along the cut line; and a solder resist provided on the base film so as to cover the wiring pattern. The solder resist protrudes outward from within the product region. | 10-02-2008 |
20080272471 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device includes an electro-optical panel having a substrate; a plurality of input terminals that are arranged in a first direction on the substrate; and a semiconductor device provided with a plurality of input bumps electrically connected to the input terminals through conductive organic members. The input terminals connected to the input bumps that are positioned substantially at the center of the semiconductor device in the first direction have allowable connection resistance values smaller than those of the other input terminals. | 11-06-2008 |
20080308914 | CHIP PACKAGE - A chip package including a circuit substrate having an opening, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface and a first rear surface opposite to the first active surface, the first chip is flipped on and electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first chip, and each first bonding wire passes through the opening. The component is disposed over the first rear surface. The first adhesive layer adhered between the first rear surface and the component includes a first B-staged adhesive layer adhered on the first rear surface and the component and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component. The molding compound is disposed on the circuit substrate. | 12-18-2008 |
20080308915 | CHIP PACKAGE - A chip package including a circuit substrate, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface, a first rear surface and first bonding pads, the first rear surface is adhered on the circuit substrate and the first chip is electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first bonding pads of the first chip. The component is disposed over the first active surface of the first chip. The first adhesive layer adhered between the first active surface and the component without covering the first bonding pads and includes a first B-staged adhesive layer adhered on a portion of the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component. | 12-18-2008 |
20090079047 | COF PACKAGE AND TAPE SUBSTRATE USED IN SAME - The present invention provides a COF package which comprises a tape substrate including a plurality of external input terminals and a plurality of external output terminals provided in a chip non-mounting area, a plurality of input wirings connected to the external input terminals respectively, a plurality of output wirings connected to the external output terminals respectively, a plurality of internal input wirings which are provided from the chip non-mounting area to a chip mounting area and provided between the input wirings and which are connected to the external input terminals, respectively, and a dummy wiring provided from the chip non-mounting area to the chip mounting area and provided between the internal input wirings; and a semiconductor chip including a plurality of input electrodes connected to the input wirings respectively, a plurality of output electrodes connected to the input wirings respectively, internal input electrodes connected to the internal input wirings respectively, and a dummy electrode provided with being spaced from each input electrode along one side lying over a chip surface, and connected to the dummy wiring. | 03-26-2009 |
20090096071 | SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING THE SAME - A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved. | 04-16-2009 |
20090115034 | Semiconductor device - A semiconductor device according to the present invention includes a base tape (film carrier tape); a semiconductor chip mounted on the base tape; conducting leads formed on the base tape to be connected to the semiconductor chip; input terminals and output terminals connected to the conducting leads; and a protecting layer formed to cover the conducting leads completely. The base tape is provided at its side edges with roller-contact regions, where carrier rollers are to be in contact with. No holes and no unevenness area is formed on the roller-contact regions. | 05-07-2009 |
20090121328 | Glass Substrate of Flat Panel Display and Display Integrated Circuit Chip - An exemplary glass substrate of flat panel display is adapted for an integrated circuit (IC) chip. The IC chip has two opposite long sides and two opposite short sides. The glass substrate includes a display area and a plurality of conductive wires. The display area has a plurality of display elements formed therein. The conductive wires are electrically coupled to the IC chip and the display area, to transmit a signal provided from the IC chip to the display area. The IC chip includes a plurality of output terminals arranged at the long sides and electrically coupled to the respective conductive wires. The present invention also provides a display IC chip for receiving and outputting a first color signal, a second color signal and a third color signal. | 05-14-2009 |
20090152692 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING - An integrated circuit package system includes: providing an interposer having a bond pad and a contact pad; mounting the interposer in an offset location over a carrier with an exposed side of the interposer coplanar with an edge of the carrier; connecting an electrical interconnect between bond pad and the carrier; and forming a package encapsulation over the carrier and the electrical interconnect with both the contact pad and the exposed side of the interposer not covered. | 06-18-2009 |
20090152693 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring board having: plural stacked insulating layers; test pads and external connection pads which are disposed on a face of the plural stacked insulating layers located on the side opposite to that where another wiring board is connected; first wiring patterns which electrically connect internal connection pads with the test pads; and second wiring patterns which electrically connect semiconductor element mounting pads with the external connection pads. The external connection pads are placed on the inner side of the test pads. | 06-18-2009 |
20090179312 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM - An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe. | 07-16-2009 |
20100176497 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM - An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height. | 07-15-2010 |
20100264526 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa. | 10-21-2010 |
20110049688 | TCP-type semiconductor device - A TCP type semiconductor device, which is connected to a plurality of substrate-side electrodes parallel to each other and each having a linear shape, has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connecting between the semiconductor chip and the plurality of substrate-side electrodes, respectively. Each of the plurality of leads has an external terminal section extending in a first direction and configured to come in contact with corresponding one of the plurality of substrate-side electrodes. A part of the external terminal section is a wide section that is formed wider than the other section of the external terminal section A position of the wide section in the first direction is different between adjacent leads of the plurality of leads. | 03-03-2011 |
20110101510 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the substrate includes an insulator, a first pad and a second pad, which are provided on an upper surface of the insulator, a through-hole, which is formed in the insulator such that a lower surface of the first pad is exposed, and a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the second pad is exposed. | 05-05-2011 |
20110127657 | WIRING CIRCUIT STRUCTURE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE USING THE STRUCTURE - A conductor layer | 06-02-2011 |
20110147903 | Leadframe Circuit and Method Therefor - An integrated circuit leadframe device supports various chip arrangements. As consistent with various embodiments, a leadframe includes a plurality of banks of conductive integrated circuit chip connectors. Each bank has a plurality of conductive strips respectively having an end portion, the end portions of each of the strips in the bank being substantially parallel to one another and arranged at an oblique angle to end portions of strips in at least one of the other banks. Each of the end portions has a tip extending to an interior portion of the leadframe device and separated from the other tips by a gap. A fastening material is arranged on at least some of the conductive strips and configured to fasten an integrated circuit chip to the conductive strips | 06-23-2011 |
20110163426 | Dice Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration - A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material. | 07-07-2011 |
20110169147 | CHIP PACKAGE STRUCTURE AND PACKAGE SUBSTRATE - A chip package structure for being disposed on a carrier includes a package substrate and a chip. The package substrate includes a laminated layer, a patterned conductive layer, a solder-mask layer, at least one outer pad and a padding pattern. The patterned conductive layer is disposed on a first surface of the laminated layer and has at least one inner pad. The solder resist layer is disposed on the first surface and has at least one opening exposed the inner pad. The outer pad is disposed on the solder resist layer, located within the opening, and is connected with the inner pad. The padding pattern is disposed on the solder resist layer. A height of the padding pattern relative to the first surface is greater than that of the outer pad. The chip is located on a second surface of the laminated layer and electrically connected to the package substrate. | 07-14-2011 |
20110169148 | TAPE WIRING SUBSTRATE AND TAPE PACKAGE USING THE SAME - A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern. | 07-14-2011 |
20110198740 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor storage device includes an organic board provided with external connection terminals on one surface and formed as an individual piece into a plane shape substantially identical to that of an area where the external connection terminals are provided, a lead frame having a mounting area positioned relative to the organic board, and a semiconductor memory chip bonded to the mounting area. | 08-18-2011 |
20110233741 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device including an organic substrate with an external connection terminal and a semiconductor memory chip. The semiconductor memory device further includes a lead frame having a bonded portion and an installation portion. It further includes a resin mold for sealing the semiconductor memory chip. The lead frame is provided with a plurality of extensions at least from one of the installation portion and the bonded portion, in a way of extending at least to two or more sides of the resin mold. | 09-29-2011 |
20110233742 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. | 09-29-2011 |
20110316131 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 12-29-2011 |
20120018861 | TAPE CARRIER SUBSTRATE - A tape carrier substrate includes: a tape carrier base | 01-26-2012 |
20120061810 | LED LEAD FRAME HAVING DIFFERENT MOUNTING SURFACES - An LED lead frame comprises an insulative housing including a top surface, a bottom surface, and four side surfaces connected the top surface and the bottom surface, and a cavity recessed from the top surface. A pair of conductive leads each has a portion embedded into the insulative housing and another portion exposed out of the insulative housing. The another portion includes an end portion extending downwardly along one of the side surface, a bottom soldering portion extending continuously from the end portion along the bottom surface, and a pair of side soldering portions extending upwardly from two ends of the bottom soldering portion along another two opposite side surfaces. The bottom soldering portion and the side soldering portions can be used as an alternative mounting surface. | 03-15-2012 |
20120112330 | SEMICONDUCTOR DEVICE - A semiconductor device, such as a semiconductor device of chip on film package, is provided. The semiconductor device includes at least an integrated circuit formed on a film base, each integrated circuit includes a chip and a plurality of leads formed interior to a boundary of a predetermined range, each lead is formed with a predetermined distance from the boundary. While the integrated circuit is punched from the film base along the boundary, conductive residue of leads left on the puncher is therefore reduced or avoided. | 05-10-2012 |
20120133035 | TCP-TYPE SEMICONDUCTOR DEVICE AND METHOD OF TESTING THEREOF - A semiconductor device includes a base film, a semiconductor chip mounted on the base film, and a plurality of leads formed on the base film, each of the leads including one end coupled to the semiconductor chip and another end being opposite to the one end. The another end of a first one of the leads and the another end of a second one of the leads are located at different positions respectively between the semiconductor chip and a cut line along which the base film is cut. | 05-31-2012 |
20120153445 | HYBRID SUBSTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS FOR FABRICATING SEMICONDUCTOR PACKAGES - Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer. | 06-21-2012 |
20120168918 | SEMICONDUCTOR PACKAGES - Provided is a semiconductor package including: a semiconductor chip mounted on a die pad; at least one lead connected electrically to the semiconductor chip; and a flexible film substrate including a metal wiring, which electrically connects the semiconductor chip and the at least one lead, wherein the semiconductor chip is electrically connected to the film substrate through a first connection member which contacts the semiconductor chip and the metal wiring; and the film substrate is electrically connected to the at least one lead through a second connection member which contacts the metal wiring and the at least one lead. | 07-05-2012 |
20120175754 | WIRING BOARD - A wiring board including a core substrate made of an insulative material and having a penetrating portion, a first interlayer insulation layer formed on the surface of the core substrate, a first conductive circuit formed on the surface of the first interlayer insulation layer, a first via conductor formed in the first interlayer insulation layer, and an electronic component accommodated in the penetrating portion of the core substrate and including a semiconductor element, a bump body mounted on the semiconductor element, a conductive circuit connected to the bump body, an interlayer resin insulation layer formed on the conductive circuit, and a via conductor formed in the interlayer resin insulation layer. The first via conductor has a tapering direction which is opposite of a tapering direction of the via conductor in the electronic component. | 07-12-2012 |
20120199960 | WIRE BONDING FOR INTERCONNECTION BETWEEN INTERPOSER AND FLIP CHIP DIE - An integrated circuit (IC) device includes an interposer having a dielectric substrate having a first side, a second side, and an inner aperture, wherein a plurality of electrically conductive traces are on the first side. An IC die includes a topside semiconductor surface having active circuitry and a bottomside surface, wherein the topside semiconductor surface includes a plurality of bond pads, and is attached over the inner aperture onto the interposer. First wirebond interconnects couple respective bond pads to respective electrically conductive traces. A workpiece includes a top workpiece surface including a plurality of contact pads thereon attached to the first side of the interposer. Second interconnects couple respective conductive traces to respective contact pads on the workpiece. | 08-09-2012 |
20120211877 | Semiconductor Device And Method For Manufacturing Same - A semiconductor device includes (i) a tape base material, (ii) a wiring pattern, (iii) a semiconductor element which is electrically connected with the wiring pattern, (iv) a top-side insulating protective film which covers a top surface of the tape base material and has an top-side opening section provided in a region where the top-side insulating protective film faces the semiconductor element, and (v) a reverse-side insulating protective film which covers a reverse surface of the tape base material and has a reverse-side opening section provided on a reverse side below the top-side opening section. The top-side insulating protective film has a protruding opening section extending outwardly from the region. An opening of the reverse-side opening section is 1.00 time to 8.50 times larger in an area than the region. | 08-23-2012 |
20120241928 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIPCHIP LEADFRAME AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system and method of manufacture thereof includes: leads and a paddle; a first encapsulant molded between the leads and the paddle, the first encapsulant thinner than the leads; a non-conductive layer over the paddle; and conductive traces directly on the leads, the first encapsulant, and the non-conductive layer. | 09-27-2012 |
20120273928 | CHIP ON FILM TYPE SEMICONDUCTOR PACKAGE - A chip on film (COF) type semiconductor package is provided. The chip on film (COF) type semiconductor package includes a film, a plurality of leads formed on a surface of the film, a chip adhered to ends of the leads, an underfill layer filled within a space between the chip and the leads, and a heat dissipation layer adhered to an other surface of the film, the heat dissipation layer including a graphite material layer, a protection layer formed on a surface of the graphite material layer to cover the graphite material layer, and an adhesion layer formed on an other surface of the graphite material layer to adhere the heat dissipation layer to the other surface of the film. | 11-01-2012 |
20120299167 | UNIFORMITY CONTROL FOR IC PASSIVATION STRUCTURE - The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads. | 11-29-2012 |
20120299168 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base carrier having a base carrier hole from a base carrier interconnection side to a base carrier device side; mounting a base integrated circuit over the base carrier; forming an encapsulation over the base carrier covering the base integrated circuit, the encapsulation having an encapsulation top side and having an encapsulation hole directly over the base carrier hole; and forming an interconnection structure as a single integral structure through the base carrier hole and the encapsulation hole, the interconnection structure directly on the encapsulation top side and directly on the base carrier interconnection side. | 11-29-2012 |
20120299169 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 11-29-2012 |
20120313228 | IMPEDENCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces. | 12-13-2012 |
20130069213 | POWER MODULE PACKAGE - Disclosed herein is a power module package including: a first substrate having one surface and the other surface; a second substrate contacting one surface of the first substrate; a third substrate contacting one side of the other surface of the first substrate; a first lead frame contacting the other side of the other surface of the first substrate; and a second lead frame electrically connected to the third substrate. | 03-21-2013 |
20130119524 | CHIP PACKAGE, METHOD FOR FORMING THE SAME, AND PACKAGE WAFER - A chip package includes: a substrate having a first surface and a second surface; a device region disposed in or on the substrate; a conducting pad disposed in the substrate or on the first surface, wherein the conducting pad is electrically connected to the device region; a hole extending from the second surface towards the first surface of the substrate; a wiring layer disposed on the second surface of the substrate and extending towards the first surface of the substrate along a sidewall of the hole to make electrical contact with the conducting pad, wherein a thickness of a first portion of the wiring layer located directly on the conducting pad is smaller than a thickness of the second portion of the wiring layer located directly on the sidewall of the hole; and an insulating layer disposed between the substrate and the wiring layer. | 05-16-2013 |
20130140687 | SEMICONDUCTOR DEVICE - According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring. | 06-06-2013 |
20130161801 | Module Including a Discrete Device Mounted on a DCB Substrate - A module includes a DCB substrate and a discrete device mounted on the DCB substrate, wherein the discrete device comprises a leadframe, a semiconductor chip mounted on the leadframe and an encapsulation material covering the semiconductor chip. | 06-27-2013 |
20130221503 | SEMICONDUCTOR PACKAGE - A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads. | 08-29-2013 |
20130221504 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING A SEMICONDUCTOR MODULE - An exemplary semiconductor module includes a substrate formed of a ceramic insulator, and at least one metallic layer formed on the substrate. The metallic layer includes a deepening for placing and fixing a contact element. The contact element is at least partially āLā-shaped and includes a first arm for fixing the contact element at the deepening, and a second arm for interconnecting the contact element with an external device. The deepening has a horizontal dimension which is about ā¦0.5 mm bigger than the horizontal dimension of the contact element. | 08-29-2013 |
20130228905 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE - A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallisation region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallisation region. | 09-05-2013 |
20130313695 | SEMICONDUCTOR DEVICE - In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti. | 11-28-2013 |
20130341775 | SEMICONDUCTOR MODULE - A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns. | 12-26-2013 |
20140001612 | Multiple Die Packaging Interposer Structure and Method | 01-02-2014 |
20140027889 | RECONSTITUTED WAFER PACKAGE WITH HIGH VOLTAGE DISCRETE ACTIVE DICE AND INTEGRATED FIELD PLATE FOR HIGH TEMPERATURE LEAKAGE CURRENT STABILITY - A reconstituted wafer level package for a versatile high-voltage capable component is disclosed. The reconstituted wafer package includes a dice substantially encapsulated by a mold material except for a first face. A dielectric layer is disposed on the first face of the dice. The package further includes an array of ball bumps formed on an exterior facing portion of the dielectric layer. Further, a field plate is disposed within the dielectric material and interposed between the first face of the dice and the ball bump array. The field plate may be spaced from the dice by a predetermined distance to prevent dielectric breakdown of the material of the dielectric layer. | 01-30-2014 |
20140042601 | MULTI-CHIP STACKING OF INTEGRATED CIRCUIT DEVICES USING PARTIAL DEVICE OVERLAP - One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A second IC device is located on a second side of the substrate opposite the first side and overlaps the IC device region and the WLFO region. The second IC device contacts a first portion of the signal traces in the IC device region and contacts a first portion of the power traces in the WLFO region. | 02-13-2014 |
20140042602 | WIRING BOARD AND METHOD FOR MANUFACTURING WIRING BOARD - A wiring board includes a substrate having a cavity, and an electronic component accommodated in the cavity of the substrate. The substrate has a thickness which is greater than a thickness of the electronic component such that a ratio of the thickness of the substrate to the thickness of the electronic component is set in a range of 0.3 or greater and 0.7 or less. | 02-13-2014 |
20140084430 | SEMICONDUCTOR CHIP AND FILM AND TAB PACKAGE COMPRISING THE CHIP AND FILM - A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge. | 03-27-2014 |
20140097525 | CIRCUIT BOARDS, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGES INCLUDING THE CIRCUIT BOARDS - Provided is a circuit board, which may include a base layer, an adhesive film, a conductive circuit, and a through via. The adhesive film and the conductive circuit may be provided in plurality to be alternately stacked on the base layer. The through via may be formed through soldering. Since the base layer is not damaged during the soldering, the through via may include various conductive materials. The through via makes it possible to easily connect the conductive circuits having different functions to one another. Accordingly, the circuit board may have multi functions. Thicknesses of the conductive circuits may be adjusted to protect the conductive circuits from folding or bending of the base layer. The circuit board having a multi-layered structure can function not only as a fabric or clothes but also as an electronic circuit. | 04-10-2014 |
20140103503 | Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability - A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate. | 04-17-2014 |
20140103504 | SEMICONDUCTOR DEVICE - A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure. | 04-17-2014 |
20140117519 | SEMICONDUCTOR DEVICE - The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps. | 05-01-2014 |
20140124910 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - Semiconductor packages and methods of forming the same may be provided. According to the semiconductor package of the present inventive concepts, a bump attached to and protruded from a bonding pad on a surface of a semiconductor chip is inserted into a through-hole defined in a package substrate. As a result, a thickness of the semiconductor package may be reduced by at least a height of the bump. Because an empty space does not exist between a semiconductor chip and the package substrate, the semiconductor package does not need a conventional underfill resin layer. Accordingly, processes of forming the semiconductor package may be simplified. | 05-08-2014 |
20140138808 | LEADFRAME AREA ARRAY PACKAGING TECHNOLOGY - Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package. | 05-22-2014 |
20140138809 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure and a manufacturing method thereof are disclosed. The package structure includes an outer lead, a driver chip, a soft material, and a solidified material. There is a distance between the driver chip and the outer lead. The soft material is used to fill the space in the package structure except the driver chip and the outer lead. The solidified material is formed in at least one region on the soft material between the driver chip and the outer lead. The hardness of the solidified material is higher than the hardness of the soft material. | 05-22-2014 |
20140159213 | ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads. | 06-12-2014 |
20140167234 | Single Layer Coreless Substrate - An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages. | 06-19-2014 |
20140191378 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe. | 07-10-2014 |
20140264794 | LOW CTE INTERPOSER WITHOUT TSV STRUCTURE - A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element. | 09-18-2014 |
20140367837 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MAKING THE SAME - The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer. | 12-18-2014 |
20150008566 | METHOD AND STRUCTURE OF PANELIZED PACKAGING OF SEMICONDUCTOR DEVICES - A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape ( | 01-08-2015 |
20150061093 | INTERPOSER AND SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD OF MANUFACTURING INTERPOSER - Disclosed herein is an interposer, including: an interposer substrate configured by stacking an insulating layer of one layer or more and interlayer connected through a via; a cavity penetrating through a center of the interposer substrate in a thickness direction; and a connection electrode having a post part which is disposed on at least one of an upper surface and a lower surface of the interposer substrate, thereby increasing electrical characteristics and reducing manufacturing cost and time. | 03-05-2015 |
20150091145 | Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSP - A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure. | 04-02-2015 |
20150097277 | FAN-OUT SEMICONDUCTOR PACKAGE WITH COPPER PILLAR BUMPS - A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier. | 04-09-2015 |
20150357270 | INTEGRATED ELECTRONIC PACKAGE AND METHOD OF FABRICATION - An integrated electronic package includes an integrated circuit (IC) die and conductive discrete components. Electrical interconnects are formed directly between bond pads on an active side of the IC die and contacts on the conductive discrete components without an intervening lead frame. The IC die, conductive discrete components and electrical interconnects are embedded in an encapsulation material. Contact surfaces of at least some of the conductive discrete components are exposed from the encapsulation material and can be attached to a printed circuit board in order to mount the integrated electronic package to the printed circuit board. | 12-10-2015 |
20150357308 | CHIP-ON-FILM (COF) TAPE AND CORRESPONDING COF BONDING METHOD - The present invention provides a chip-on-film (COF) tape and a corresponding COF bonding method. The COF tape comprises a base tape, a plurality of first COFs and second COFs, the first and second COFs are arranged on the base tape in an alternating manner, and are correspondingly punched onto a moving platform by a punching mechanism, and are respectively bonded onto two side edges of a liquid crystal panel. The present invention can simultaneously process the bonding operations of the two types of COF by using only one COF tape and one set of equipment, thus lowering the cost and increasing the productivity. | 12-10-2015 |
20160013353 | MOUNTING MEMBER HAVING DIE PAD UNIT AND TERMINALS, AND PHOTOCOUPLER HAVING THE MOUNTING MEMBER | 01-14-2016 |
20160035590 | SYSTEM-IN-PACKAGES AND METHODS FOR FORMING SAME - One or more embodiments are directed to a system-in-package (SiP) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer. Furthermore, prior to setting or curing, the encapsulation layer is able to flow between the semiconductor chips and the interposer to provide further mechanical support for the semiconductor chips. Thus, the process for forming the SiP is reduced, resulting in a faster processing time and a lower cost. Additionally, one or more embodiments described herein reduce or eliminate warpage of the interposer. | 02-04-2016 |
20160035659 | BALL GRID ARRAY AND LAND GRID ARRAY ASSEMBLIES FABRICATED USING TEMPORARY RESIST - Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder. | 02-04-2016 |
20160035663 | Semiconductor Package System and Method - A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. | 02-04-2016 |
20160035667 | Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices - Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes providing a protective film, coupling dies to the protective film, and disposing a molding material around the dies. The protective film includes a substantially opaque material at predetermined wavelengths of light. | 02-04-2016 |
20160049359 | INTERPOSER WITH CONDUCTIVE POST AND FABRICATION METHOD THEREOF - An interposer is provided, including a substrate body, a plurality of conductive posts formed in the substrate body, and a plurality of conductive pads formed on the substrate body and electrically connected to the conductive posts. The conductive pads and the conductive posts are integrally formed. As such, no interface is formed between the conductive pads and the conductive posts, thereby preventing delamination or cracking from occurring between the conductive pads and the conductive posts. | 02-18-2016 |
20160079153 | Driving Chip Package and Display Device Including the Same - A display device includes a display panel and a chip-on-film (COF) bonded to the display panel. The chip-on-film includes a film on which a driving chip is mounted, a plurality of film lines on the film, and at least one dummy pattern on the film between an adjacent pair of films in the plurality of film lines. | 03-17-2016 |
20160109744 | DISPLAY DEVICE - In the technical field of display, a display device for solving the technical problem of fanout mura of the pixels controlled by the wires located at both sides of a fanout is provided. The display device according to the present disclosure comprises a substrate and a chip on film connected to the fanout on the substrate through a bounding lead. The bounding lead comprises a plurality of parallel wires, each of the wires comprising a conductive portion and all or some of the wires each comprising a non-conductive portion. In the bounding lead, the areas of the conductive portions of the wires gradually decrease from the wires located at both ends of the bounding lead to those located at the center thereof. The present disclosure can be applied to display devices, such as liquid crystal television and liquid crystal display, etc. | 04-21-2016 |
20160111349 | PACKAGED SEMICONDUCTOR DEVICES - A semiconductor device has a semiconductor chip having a first surface with metallized terminals and a parallel second surface. A frame of insulating material adheres to at the sidewalls of the chip. The frame has a first surface planar with the first chip surface and a parallel second surface planar with the second chip surface. The first frame surface includes one or more embedded metallic fiducials extending from the first surface to the insulating material. At least one film of sputtered metal extends from the terminals across the surface of the polymeric layer to the fiducials. The film is patterned to form extended contact pads over the frame and rerouting traces between the chip terminals and the extended contact pads. The film adheres to the surfaces. | 04-21-2016 |
20160126192 | Power Semiconductor Module Having a Direct Copper Bonded Substrate and an Integrated Passive Component, and an Integrated Power Module - A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided. | 05-05-2016 |
20160133550 | DOUBLE-SIDED CHIP ON FILM PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF - A double-sided chip on film (COF) packaging structure and a manufacturing method thereof are disclosed. The double-sided COF structure includes a metal layer, a first insulating layer, a second insulating layer, a chip, and an encapsulant. The first insulating layer and second insulating layer are disposed on a first surface and a second surface of metal layer respectively. The first surface and second surface are opposite. The first insulating layer includes a first part and a second part separated from each other. An accommodating space is existed between the first part and the second part and a part of the first surface is exposed. The chip is accommodated in the accommodating space and disposed on the exposed part of the first surface. The encapsulant fills the spaces between the chip and the first part and between the chip and the second part to form the double-sided COF packaging structure. | 05-12-2016 |
20160181171 | Integrated circuit with printed bond connections | 06-23-2016 |
20160181195 | SUBSTRATE STRIP AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME | 06-23-2016 |
20160190032 | WIRING BOARD AND SEMICONDUCTOR PACKAGE INCLUDING WIRING BOARD - According to an embodiment, a wiring board includes an insulating board including a heat transfer region made of silicon nitride and having a thickness in a range between 0.2 mm and 1 mm; and a wiring layer including a pad stacked on the heat transfer region and made of a metal material having a thickness of 1.5 mm or more. | 06-30-2016 |
20160197032 | SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS ON PARTIAL ENCAPSULATION AND NON-PHOTOSENSITIVE PASSIVATION LAYERS | 07-07-2016 |
20160204079 | Methods and Apparatus of Packaging with Interposers | 07-14-2016 |
20160254215 | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME | 09-01-2016 |
20160254219 | TAPE FOR ELECTRONIC DEVICES WITH REINFORCED LEAD CRACK | 09-01-2016 |
20160254220 | LOW WARPING CORELESS SUBSTRATE AND SEMICONDUCTOR ASSEMBLY USING THE SAME | 09-01-2016 |
20160379938 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes a first reinforcement pattern stacked on a lower surface of a first insulation layer at a peripheral region located at an outer side of a wiring formation region. A first reinforcement via extends through a second insulation layer in the thickness-wise direction and contacts the first reinforcement pattern. A second reinforcement pattern is stacked on a lower surface of the second insulation layer and connected to the first reinforcement pattern by the first reinforcement via. The first reinforcement via includes a top that partially extends into the first insulation layer. | 12-29-2016 |
20170236783 | PACKAGE STRUCTURE | 08-17-2017 |
20170236788 | Semiconductor Device and Method of Forming Interconnect Substrate for FO-WLCSP | 08-17-2017 |
20180025987 | Wafer-Level Packaged Components and Methods Therefor | 01-25-2018 |
20180025992 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | 01-25-2018 |
20180025994 | SURFACE MOUNT PACKAGE AND MANUFACTURING METHOD THEREOF | 01-25-2018 |
20180026017 | Dies-on-Package Devices and Methods Therefor | 01-25-2018 |
20180026019 | Package-on-Package Devices with WLP Components with Dual RDLS for Surface Mount Dies and Methods Therefor | 01-25-2018 |
20190148258 | POWER SEMICONDUCTOR DEVICE | 05-16-2019 |
20190148274 | Intergrated Circuit Packages and Methods of Forming Same | 05-16-2019 |
20190148310 | SEMICONDUCTOR PACKAGE SUBSTRATE SUPPORT STRUCTURES FOR BALL-GRID ARRAY CAVITIES, AND METHODS OF ASSEMBLING SAME | 05-16-2019 |
20190148311 | MICROELECTRONIC BOND PADS HAVING INTEGRATED SPRING STRUCTURES | 05-16-2019 |
20220139817 | BALL GRID ARRAY PACKAGE AND PACKAGE SUBSTRATE THEREOF - A package substrate is adapted to a ball grid array package. The substrate includes two substrate contacts, two solder ball pads, two via holes and two signal lines. A connection line of the two substrate contacts is substantially perpendicular to a connection line of the two solder ball pads. The two substrate contacts are respectively connected to the two via holes by the two signal lines. Each signal line includes a circuit trace section, an approaching section and a bifurcating section connected in sequence. The two circuit trace sections of each signal line are substantially arranged in parallel. The two approaching sections are substantially arranged in parallel and substantially symmetrical about the connection line of the solder ball pads. The two bifurcating sections are substantially symmetrical about the pad connection line and respectively electrically connected to the two via holes. | 05-05-2022 |
20220139839 | Integrated Circuit Package and Method - In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias. | 05-05-2022 |
20220139848 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die. | 05-05-2022 |