| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257660000 | With means to shield device contained in housing or package from charged particles (e.g., alpha particles) or highly ionizing radiation (i.e., hard X-rays or shorter wavelength) | 87 |
| 20080251895 | APPARATUS FOR SHIELDING INTEGRATED CIRCUIT DEVICES - A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die. In one embodiment, an integrated circuit apparatus for use in high reliability applications is disclosed. The integrated circuit apparatus is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates. | 10-16-2008 |
| 20080315376 | Conformal EMI shielding with enhanced reliability - An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a molded package panel to a process carrier ( | 12-25-2008 |
| 20080315377 | PACKAGED ELECTRONIC MODULES AND FABRICATION METHODS THEREOF IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM - Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer. | 12-25-2008 |
| 20090008753 | INTEGRATED CIRCUIT WITH INTRA-CHIP AND EXTRA-CHIP RF COMMUNICATION - An integrated circuit includes a first integrated circuit die having a first circuit and a first intra-chip interface and a second integrated circuit die having a second circuit and a second intra-chip interface and a remote interface, wherein the first intra-chip interface and the second intra-chip interface electro-magnetically communicate first signals between the first circuit and the second circuit, and wherein the remote interface is coupled to engage in electromagnetic communications with a remote device. In an embodiment of the present invention, a shielding element shields the electromagnetic communications with the remote device from the electromagnetic communication of the first signals. In other embodiments, antenna beam patterns or differing polarizations are used to isolate the electromagnetic communications with the remote device from the electromagnetic communication of the first signals. | 01-08-2009 |
| 20090079041 | Semiconductor Package and Method of Reducing Electromagnetic Interference Between Devices - A wafer level semiconductor package has a substrate and an RF module and baseband module coupled to the substrate with solder bumps. An underfill material is disposed under the RF module and baseband module. A first shielding layer is applied to a first surface of the substrate. A seed layer is deposited on the substrate and RF module and baseband module. A second shielding layer is plated over the seed layer, except over the contact pads on the substrate. The second shielding layer can be made from copper, gold, nickel, or aluminum. The first and second shielding layers substantially cover the wafer level semiconductor package to isolate the baseband module from electromagnetic interference generated by the RF module. The first and second shielding layers are grounded through the substrate. | 03-26-2009 |
| 20090140399 | Semiconductor Module with Switching Components and Driver Electronics - A semiconductor module comprises at least one semiconductor chip having at least one semiconductor switch. The at least one semiconductor chip is arranged on a carrier substrate. At least one driver component drives the at least one semiconductor switch. The at least one driver component is arranged on a circuit board. The at least one driver component has at least one input for receiving a control signal. The circuit board has a galvanic isolation in a signal path between the at least one driver component and the at least one semiconductor chip. | 06-04-2009 |
| 20090179311 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING THE SAME - A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the side edges, the rear side and the top side, on which surface-mountable external contacts are arranged. One embodiment includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip. | 07-16-2009 |
| 20090184405 | Package structure - A package structure is provided. The package structure includes a substrate, a semiconductor device, and a shielding cap. The substrate has at least an alignment recess located at a corner of the substrate. The semiconductor device is disposed on an upper surface of the substrate. The shielding cap having an alignment pin covers the semiconductor device. The alignment pin is inserted into the alignment recess. | 07-23-2009 |
| 20090194851 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of tile package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of a grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 08-06-2009 |
| 20090194852 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) a grounding element disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface; (4) a package body disposed adjacent to the upper surface and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a lateral surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The grounding element corresponds to a remnant of a conductive bump, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 08-06-2009 |
| 20090194853 | SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a shielded stacked integrated circuit packaging system includes forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure. | 08-06-2009 |
| 20090243053 | STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS - A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate. | 10-01-2009 |
| 20090256244 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 10-15-2009 |
| 20090261460 | Wafer Level Integration Package - A semiconductor package has a first conductive layer formed on a top surface of a substrate. A conductive via is formed between the first conductive layer and a bottom surface of the substrate. A semiconductor component is mounted to the substrate and electrically connected to the first electrical contact pad. The semiconductor component can be a flip chip semiconductor device, wire bond semiconductor device, or passive component. An encapsulant is deposited over the semiconductor component. The encapsulant extends into a channel formed on a side of the substrate from the top surface to the bottom surface of the substrate. An interconnect structure is formed over the bottom surface of the substrate. A heat spreader structure can be disposed over the semiconductor component. An EMI shield can be disposed over the semiconductor component. A plurality of semiconductor components can be stacked in a package-in-package arrangement. | 10-22-2009 |
| 20090273062 | SEMICONDUCTOR PACKAGE HEAT SPREADER - A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate. | 11-05-2009 |
| 20090294930 | Semiconductor packages having electromagnetic interference-shielding function, manufacturing method thereof and jig - The present invention relates to relates to a semiconductor package having a function of shielding electromagnetic interference (EMI), a manufacturing method thereof and a jig, and more particularly, to such a semiconductor package having an electromagnetic interference (EMI)-shielding function, a manufacturing method thereof and a jig for use in a plasma sputtering, in which a nickel alloy is coated on the surface of a semiconductor package by a sputtering method so as to shield electromagnetic interference (EMI) generated from the semiconductor package. | 12-03-2009 |
| 20090294931 | Methods of Making an Electronic Component Package and Semiconductor Chip Packages - An electronic component package having an EMI shielded space is disclosed. The package comprises a substrate having an electronic component located on its surface and a conductive enclosure having a top and downwardly extending sides enclosing the component and defining a shielded space. A vent opening is provided through the substrate and is located in the shielded space for venting the shielded space. A second vent opening may be provided in the top of the conductive enclosure. | 12-03-2009 |
| 20090302439 | Semiconductor Device Having Electrical Devices Mounted to IPD Structure and Method of Shielding Electromagnetic Interference - A semiconductor device is made by forming an integrated passive device (IPD) structure on a substrate, mounting first and second electrical devices to a first surface of the IPD structure, depositing encapsulant over the first and second electrical devices and IPD structure, forming a shielding layer over the encapsulant, and electrically connecting the shielding layer to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant. | 12-10-2009 |
| 20090315156 | PACKAGED INTEGRATED CIRCUIT HAVING CONFORMAL ELECTROMAGNETIC SHIELDS AND METHODS TO FORM THE SAME - Example packaged integrated circuit (IC) chips having conformal electromagnetic shields and methods to form the same are disclosed. A disclosed packaged IC chip comprises an IC attached to a first surface of a substrate, the substrate having a conductive pad on the first surface, a first conductive element electrically coupled to the conductive pad on the first surface of the substrate, a molding compound to encapsulate the IC and the first conductive element, the molding compound exposing a surface of the first conductive element, a conformal electromagnetic shield on the molding compound in electrical contact with the exposed surface of the first conductive element, and an externally exposed second conductive element attached to a second surface of the substrate, the second conductive element in electrical contact with the first conductive element. | 12-24-2009 |
| 20090321898 | CONFORMAL SHIELDING INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads. | 12-31-2009 |
| 20100013064 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit defining a cut-out portion disposed adjacent to a periphery of the substrate unit; (2) a grounding element disposed in the cut-out portion and at least partially extending between an upper surface and a lower surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body. The EMI shield is electrically connected to a connection surface of the grounding element, such that the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 01-21-2010 |
| 20100013065 | STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME - A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC. | 01-21-2010 |
| 20100013066 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip. | 01-21-2010 |
| 20100032815 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit; (2) a semiconductor device disposed adjacent to the upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body. A periphery of the package body is laterally recessed, such that a connection surface of the grounding element is electrically exposed and electrically connected to the EMI shield. The grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 02-11-2010 |
| 20100052117 | STACKABLE MULTI-CHIP PACKAGE SYSTEM WITH SUPPORT STRUCTURE - A stackable multi-chip package system is provided including forming an external interconnect, having a base and a tip, and a paddle; mounting a first integrated circuit die over the paddle; stacking a second integrated circuit die over the first integrated circuit die in a active side to active side configuration; connecting the first integrated circuit die and the base; connecting the second integrated circuit die and the base; and molding the first integrated circuit die, the second integrated circuit die, the paddle, and the external interconnect with the external interconnect partially exposed. | 03-04-2010 |
| 20100109132 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure. | 05-06-2010 |
| 20100109133 | SEMICONDUCTOR DEVICE - A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip. | 05-06-2010 |
| 20100140759 | Semiconductor Device and Method of Forming a Shielding Layer over a Semiconductor Die after Forming a Build-Up Interconnect Structure - A semiconductor device is made by forming a build-up interconnect structure over a substrate. A semiconductor die is mounted to the build-up interconnect structure. The semiconductor die is electrically connected to the build-up interconnect structure. A ground pad is formed on the build-up interconnect structure. An encapsulant is formed over the semiconductor die and build-up interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the build-up interconnect structure to isolate the semiconductor die from inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. The substrate is removed. A backside interconnect structure is formed over the build-up interconnect structure, opposite the semiconductor die. | 06-10-2010 |
| 20100140760 | ALPHA SHIELDING TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed. | 06-10-2010 |
| 20100155912 | APPARATUS FOR SHIELDING INTEGRATED CIRCUIT DEVICES - A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die. In one embodiment, an integrated circuit apparatus for use in high reliability applications is disclosed. The integrated circuit apparatus is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates. | 06-24-2010 |
| 20100200967 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING SHIELD - An integrated circuit package system includes: a substrate; a first device attached to the substrate; a shield attached to the substrate and surrounding the first device; apertures formed within the shield; the shield configured to block electromagnetic energy that passes through the apertures; and an encapsulation material deposited through the apertures. | 08-12-2010 |
| 20100207258 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including at least a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer disposed over the top surface of the laminate substrate can protect the chip package from the underneath EMI radiation. The chip package may further include another shielding layer over the molding compound of the chip package. | 08-19-2010 |
| 20100207259 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element. | 08-19-2010 |
| 20100213584 | ULTRA WIDEBAND HERMETICALLY SEALED SURFACE MOUNT TECHNOLOGY FOR MICROWAVE MONOLITHIC INTEGRATED CIRCUIT PACKAGE - An ultra wideband hermetically sealed surface mount package for a microwave monolithic integrated circuit (MMIC) is provided including: an integrated circuit; a package body being mounted with the integrated circuit and comprising a plurality of first dielectrics formed in a multilayer, a first line unit mounted to a circuit substrate and is electrically connected with an external circuit, a second line unit upwardly extended from the first line unit and is electrically connected with the first line unit, a third line unit extended to the right angle from the second line unit and is electrically connected with the second line unit, and a bonding unit that electrically connects the third line unit and the mounted integrated circuit; and a package cover being formed on the package body to seal the integrated circuit and comprising a plurality of second dielectrics formed in a multilayer. | 08-26-2010 |
| 20100213585 | SEMICONDUCTOR DEVICE - A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip. | 08-26-2010 |
| 20100224969 | ELECTRONIC DEVICE AND METHOD OF PACKAGING AN ELECTRONIC DEVICE - An electronic device and a method of packaging an electronic device are disclosed. In one embodiment, the electronic device can include a first die. The electronic device can also include a dielectric layer defining a first opening. The first die can be disposed within the first opening. Further, the electronic device can include an encapsulating material disposed adjacent to the first die. The encapsulating material can have a different composition as compared to the dielectric layer. In a particular embodiment, the electronic device can also include an electrically conductive carrier contacting the dielectric layer and the encapsulating material. | 09-09-2010 |
| 20100237477 | Semiconductor Device and Method of Mounting Pre-Fabricated Shielding Frame over Semiconductor Die - A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference. | 09-23-2010 |
| 20100264524 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE - A substrate for a semiconductor package includes a dielectric substrate, a circuit pattern formed on a first surface of the dielectric substrate, and an electromagnetic band gap (EGB) pattern. The EGB pattern includes multiple unit structures formed on a second surface of the dielectric substrate, where each unit structure includes a flat conductor electrically connected to the circuit pattern through a ground connection, and multiple spiral-patterned conductors electrically connected to the flat conductor. The second surface is formed on an opposite side of the dielectric substrate from the first surface. Each flat conductor is electrically connected to a flat conductor of another one of the unit structures. At least one of the spiral-patterned conductors in each one of the unit structures is electrically connected to another one of the spiral-patterned conductors. | 10-21-2010 |
| 20100276792 | Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure - A semiconductor device has a substrate containing a conductive layer. An interconnect structure is formed over the substrate and electrically connected to the conductive layer. A semiconductor component is mounted to the substrate. An encapsulant is deposited over the semiconductor component and interconnect structure. A channel is formed in the encapsulant to expose the interconnect structure. Solder paste is deposited in the channel prior to forming the shielding layer. A shielding layer is formed over the encapsulant and semiconductor component. The shielding layer can be conformally applied over the encapsulant and semiconductor die and into the channel. The shielding layer extends into the channel and electrically connects to the interconnect structure. A docking pin is formed on the shielding layer, which extends into the channel and electrically connects to the interconnect structure. A chamfer area is formed around a perimeter of the shielding layer. | 11-04-2010 |
| 20110001222 | ELECTRONIC DEVICE, LAYERED SUBSTRATE, AND METHODS OF MANUFACTURING SAME - An electronic device comprises an electronic element package and a mounting substrate on which the electronic element package is mounted. The electronic element package has an LGA electrode. The mounting substrate has a through-hole having a conductor which covers an inner wall. The LGA electrode has an area larger than an opening area of the through-hole on a side facing the LGA electrode. The electronic element package is mounted on the mounting substrate so that at least a part of the opening of the through-hole overlaps with the LGA electrode. The LGA electrode and the conductor of the through-hole are electrically connected to a conductive material provided inside the through-hole. In the LGA electrode, at least a part of the region that does not overlap with the opening of the through-hole is joined to the mounting substrate by an adhesive. | 01-06-2011 |
| 20110006408 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a shielding layer conformally covering the underlying molding compound for is provided. The shielding layer can smoothly cover the molding compound and over the rounded or blunted, top edges of the molding compound, which provides better electromagnetic interferences shielding and better shielding performance. | 01-13-2011 |
| 20110049685 | SEMICONDUCTOR DEVICE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - In accordance with the present invention, there is provided a quad flat no leads (QFN) semiconductor device or package including a leadframe wherein the leads of the leadframe are selectively formed so that portions one or more prescribed leads are exposed in a package body of the semiconductor package and electrically connected to an electromagnetic interference (EMI) shielding layer applied to the package body. In certain embodiments of the present invention, one or more tie bars of the leadframe may also be formed so as to be exposed in the package body of the semiconductor package and electrically connected to the shielding layer applied to the package body. Thus, in the present invention, the shielding layer may be electrically connected to one or more leads alone or in combination with one or more tie bars of the leadframe. | 03-03-2011 |
| 20110084368 | OVERMOLDED SEMICONDUCTOR PACKAGE WITH A WIREBOND CAGE FOR EMI SHIELDING - According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component. | 04-14-2011 |
| 20110089540 | SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE - A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap. | 04-21-2011 |
| 20110089541 | Area reduction for electrical diode chips - Using electrical printing technologies to form package level conductor leads for electrical diode circuit, the preferred embodiments of the present invention significantly reduces the areas of surface mount electrical diodes or ESD circuits. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. Additional cost reduction can be achieved by using none-crystalline semiconductor electrical diodes. | 04-21-2011 |
| 20110089542 | Area reduction for electrical diode chips - Using electrical printing technologies to form package level conductor leads for electrical diode circuit, the preferred embodiments of the present invention significantly reduces the areas of surface mount electrical diodes or ESD circuits. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. Additional cost reduction can be achieved by using none-crystalline semiconductor electrical diodes. | 04-21-2011 |
| 20110095403 | Semiconductor Device and Method of Forming a Shielding Layer over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded through the Die TSV - A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die. | 04-28-2011 |
| 20110095404 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A disclosed semiconductor device includes a semiconductor chip having an electrode pad on a circuit forming face of the semiconductor chip, an internal connection terminal formed on the electrode pad, a stepped portion formed along an outer edge portion of the circuit forming face of the semiconductor chip, a first insulating layer formed on the circuit forming face of the semiconductor chip to cover at least the stepped portion, a second insulating layer formed on the circuit forming face of the semiconductor chip to cover the first insulating layer, and an interconnection formed on the second insulating layer and electrically connected to the electrode pad via the internal connection terminal. | 04-28-2011 |
| 20110101509 | Wafer Integrated With Permanent Carrier and Method Therefor - A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer. | 05-05-2011 |
| 20110115060 | Wafer-Level Semiconductor Device Packages with Electromagnetic Interference Shielding - Described herein are wafer-level semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a semiconductor device; (2) a package body covering lateral surfaces of the semiconductor device, a lower surface of the package body and a lower surface of the semiconductor device defining a front surface; (3) a set of redistribution layers disposed adjacent to the front surface, the set of redistribution layers including a grounding element that includes a connection surface electrically exposed adjacent to at least one lateral surface of the set of redistribution layers; and (4) an EMI shield disposed adjacent to the package body and electrically connected to the connection surface of the grounding element. The grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 05-19-2011 |
| 20110127653 | PACKAGE SYSTEM WITH A SHIELDED INVERTED INTERNAL STACKING MODULE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package system includes: providing a base package substrate having conductive elements; providing an internal stacking module having a semiconductor die mounted on a package substrate and a first encapsulant surrounding at least portions of the semiconductor die and the package substrate; covering at least portions of the first encapsulant in the internal stacking module with an electromagnetic interference shield, the electromagnetic interference shield shaped to have an outside face; mounting the internal stacking module over the base package substrate with the outside face of the electromagnetic interference shield facing the base package substrate; and encapsulating at least portions of the internal stacking module, the electromagnetic interference shield, and the base package substrate using a second encapsulant. | 06-02-2011 |
| 20110127654 | Semiconductor Package and Manufacturing Methods Thereof - A semiconductor package and manufacturing methods thereof are provided. In one embodiment, the semiconductor package includes a die, a shield, a package body, and a redistribution layer. The die has an active surface and an inactive surface. The shield is disposed over the inactive surface of the die. The package body encapsulates the die and a first portion of the shield, where a first surface of the package body is substantially coplanar with the active surface of the die. The redistribution layer is disposed on the active surface of the die and on portions of the first surface of the package body. | 06-02-2011 |
| 20110147901 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes forming a lead frame including providing a tie bar plate, forming conductive columns on the tie bar plate, forming a dielectric layer on the conductive columns, applying a conductive shield layer on the dielectric layer, and exposing the conductive columns through the dielectric layer and the conductive shield layer; forming a base package substrate; mounting a base integrated circuit die on the base package substrate; mounting the tie bar plate, over the base integrated circuit die, conductively coupled to the base package substrate to form the conductive shield layer into an electro-magnetic interference shield; and removing the tie bar plate to expose the conductive columns from the dielectric layer. | 06-23-2011 |
| 20110147902 | Integrated Circuit Comprising Light Absorbing Adhesive - The invention relates to a structure | 06-23-2011 |
| 20110175211 | Method And Structure To Reduce Soft Error Rate Susceptibility In Semiconductor Structures - A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device. | 07-21-2011 |
| 20110186973 | Semiconductor Device and Method of Forming Air Gap Adjacent to Stress Sensitive Region of the Die - A semiconductor device is made by mounting an insulating layer over a temporary substrate. A via is formed through the insulating layer. The via is filled with conductive material. A semiconductor die has a stress sensitive region. A dam is formed around the stress sensitive region. The semiconductor die is mounted to the conductive via. The dam creates a gap adjacent to the stress sensitive region. An encapsulant is deposited over the semiconductor die. The dam blocks the encapsulant from entering the gap. The temporary substrate is removed. A first interconnect structure is formed over the semiconductor die. The gap isolates the stress sensitive region from the first interconnect structure. A shielding layer or heat sink can be formed over the semiconductor die. A second interconnect structure can be formed over the semiconductor die opposite the first interconnect structure. | 08-04-2011 |
| 20110215450 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a carrier having a cavity and a carrier top side adjacent to the cavity; mounting an integrated circuit in the cavity; forming an encapsulation surrounding the integrated circuit; and attaching a conductive channel to the carrier top side, the conductive channel over the encapsulation. | 09-08-2011 |
| 20110260303 | Semiconductor Device and Method of Forming Openings in Thermally-Conductive Frame of FO-WLCSP to Dissipate Heat and Reduce Package Height - A semiconductor device has a thermally-conductive frame and interconnect structure formed over the frame. The interconnect structure has an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. A portion of a back surface of the first die is removed by grinding. An EMI shielding layer can be formed over the first die. The first die can be mounted in a recess of the thermally-conductive frame. An opening is formed in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure. A second semiconductor die is mounted over the thermally-conductive frame opposite the first die. The second die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame. | 10-27-2011 |
| 20110298109 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED EMI SHIELDING FRAME WITH CAVITIES CONTAINING PENETRABLE MATERIAL OVER SEMICONDUCTOR DIE - A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame. | 12-08-2011 |
| 20110298110 | Semiconductor Device and Method of Forming Thermally Conductive Layer Between Semiconductor Die and Build-Up Interconnect Structure - A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant. | 12-08-2011 |
| 20110298111 | SEMICONDUCTOR PACKAGE AND MANUFACTRING METHOD THEREOF - There is provided a semiconductor package capable of protecting a passive element, a semiconductor chip, or the like included in the package from external force and having enhanced Electro Magnetic Interference (EMI) and Electro Magnetic Susceptibility (EMS) characteristics and a manufacturing method thereof. The semiconductor package includes a substrate having at least one cavity formed in a side surface thereof and an electrode provided within the cavity; at least one electronic component mounted on a surface of the substrate; a mold part sealing the electronic component and having insulating properties; and a shield part attached to the mold part to cover an outer surface of the mold part, electrically connected to the electrode provided within the cavity, and having conductive properties. | 12-08-2011 |
| 20120012991 | Integrated shielding for a package-on-package system - An electronic package-on-package system with integrated shielding. The package-on-package system includes a first package having a first die and a second package having a second die and a substrate. The system also includes a conductive shield having a first portion and a second portion. The first portion is disposed between the first die and the second die and the second portion is disposed between the substrate and the first portion. The first portion is coupled to the second portion for shielding the first die from the second die. | 01-19-2012 |
| 20120104574 | INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE - A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package. | 05-03-2012 |
| 20120112327 | Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die - A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame. | 05-10-2012 |
| 20120112328 | Semiconductor Device and Method of Mounting Pre-Fabricated Shielding Frame over Semiconductor Die - A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference. | 05-10-2012 |
| 20120126382 | MAGNETIC SHIELDING FOR MULTI-CHIP MODULE PACKAGING - A system comprises a plurality of stacked integrated circuit dice, each integrated circuit die comprising at least one circuit, a package enclosing the plurality of dice, and at least two magnetic shields configured to magnetically shield the at least one circuit of each of the plurality of integrate circuit dice. At least one of the magnetic shields is within the package, and at least two of the plurality of stacked integrated circuit dice are positioned between the at least two magnetic shields. | 05-24-2012 |
| 20120139092 | MULTI-CHIP STACK STRUCTURE - A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips. | 06-07-2012 |
| 20120153443 | PACKAGED SEMICONDUCTOR CHIPS WITH ARRAY - A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. | 06-21-2012 |
| 20120161300 | IONIZING RADIATION BLOCKING IN IC CHIP TO REDUCE SOFT ERRORS - Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip. | 06-28-2012 |
| 20120199959 | EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE - An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. The UBM field is separated from each UBM pad by a gap extending from the UBM pad to the UBM field so as to electrically isolate the UBM field from the UBM pad. | 08-09-2012 |
| 20120211876 | MODULE IC PACKAGE STRUCTURE - A module IC package structure includes a substrate unit, a radio frequency unit, an inner shielding unit, an insulative package unit, and an outer shielding unit. The substrate unit includes a circuit substrate. The radio frequency unit includes at least one radio frequency element disposed on and electrically connected to the circuit substrate. The inner shielding unit includes an inner metal shielding layer formed on a predetermined surface of the radio frequency element. The insulative package unit includes an insulative package resin body disposed on the circuit substrate to cover the radio frequency element. The outer shielding unit is formed on the outer surface of the insulative package resin body and electrically connected to the circuit substrate. The inner metal shielding layer is a radio frequency property maintaining layer disposed between the radio frequency element and one part of the outer shielding unit for shielding the radio frequency element. | 08-23-2012 |
| 20120228751 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and method of manufacture are provided. The semiconductor package may include a package substrate, a semiconductor chip, a molding member and a grounding member. The package substrate may include a ground pad and a signal pad. The semiconductor chip may be arranged on an upper surface of the package substrate. The semiconductor chip may be electrically connected with the signal pad of the package substrate. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The grounding member may be arranged on a surface of the molding member. The grounding member may be electrically connected with the ground pad. | 09-13-2012 |
| 20120228752 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate; a signal pad and a ground pad disposed on the substrate; a first and a second conducting layers disposed on the substrate and electrically connected to the signal pad and the ground pad, respectively, wherein the first and the second conducting layers extend from an upper surface of the substrate towards a lower surface of the substrate along a first and a second side surfaces of the substrate, respectively, and the first and the second conducting layers protrude from the lower surface; and a protection layer disposed on the substrate, wherein the protection layer completely covers the entire portion of the first conducting layer located on the first side surface of the substrate, and the entire portion of the second conducting layer located on the second side surface of the substrate is not covered by the protection layer. | 09-13-2012 |
| 20120267768 | FORMATION OF ALPHA PARTICLE SHIELDS IN CHIP PACKAGING - A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads. | 10-25-2012 |
| 20120292751 | Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield - A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die. | 11-22-2012 |
| 20130015564 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAMEAANM Matsuki; HirohisaAACI YokohamaAACO JPAAGP Matsuki; Hirohisa Yokohama JPAANM Sakuma; MasaoAACI YokohamaAACO JPAAGP Sakuma; Masao Yokohama JP - A semiconductor device (semiconductor module) includes a circuit board (module board) and a semiconductor element mounted on the circuit board. A shielding layer that blocks electromagnetic waves is disposed on the upper surface of the semiconductor element, and an antenna element is disposed over the shielding layer. The semiconductor element and the antenna element are electrically connected to each other by a connecting portion. This structure enables the semiconductor device to be reduced in size and to have both an electromagnetic-wave blocking function and an antenna function. | 01-17-2013 |
| 20130062740 | TUNABLE RADIATION SOURCE - An energy distribution of soft error-inducing radiation likely to be encountered by an electronic circuit during operation is determined. A tuned radiation source having a source energy distribution similar to the determined energy distribution is prepared. The electronic circuit is tested using the tuned radiation source. | 03-14-2013 |
| 20130093068 | Semiconductor Device and Method of Forming Air Gap Adjacent to Stress Sensitive Region of the Die - A semiconductor device is made by mounting an insulating layer over a temporary substrate. A via is formed through the insulating layer. The via is filled with conductive material. A semiconductor die has a stress sensitive region. A dam is formed around the stress sensitive region. The semiconductor die is mounted to the conductive via. The dam creates a gap adjacent to the stress sensitive region. An encapsulant is deposited over the semiconductor die. The dam blocks the encapsulant from entering the gap. The temporary substrate is removed. A first interconnect structure is formed over the semiconductor die. The gap isolates the stress sensitive region from the first interconnect structure. A shielding layer or heat sink can be formed over the semiconductor die. A second interconnect structure can be formed over the semiconductor die opposite the first interconnect structure. | 04-18-2013 |
| 20130113089 | MODULE IC PACKAGE STRUCTURE HAVING A METAL SHIELDING FUNCTION FOR PREVENTING ELECTRICAL MALFUNCTION INDUCED BY SHORT-CIRCUIT - A module IC package structure having a metal shielding function includes a substrate unit, an electronic unit, a shielding unit, and an insulative unit. The substrate unit includes a substrate body and at least one grounding pad disposed on the substrate body. The electronic unit includes at least one electronic module disposed on the circuit substrate and electrically connected to the circuit substrate. The shielding unit includes a metal shielding layer formed on an external surface of the at least one electronic module, and the metal shielding layer contacts the at least one grounding pad. The insulative unit includes an insulative layer formed on an external surface of the metal shielding layer. Hence, the module IC package structure can be used to prevent electrical malfunction induced by short-circuit due to the design of forming the insulative layer formed on the external surface of the metal shielding layer. | 05-09-2013 |
| 20130127025 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - There are provided a semiconductor package and a manufacturing method thereof, capable of increasing integration by mounting electronic devices on both surfaces of a substrate. The semiconductor package includes a first substrate having mounting electrodes on both surfaces thereof; a plurality of electronic devices mounted on both surfaces of the first substrate; and a second substrate exposed in cavities and bonded to a bottom surface of the first substrate so as to accommodate the electronic devices mounted on the bottom surface of the first substrate in the cavities. | 05-23-2013 |
| 20130207248 | DEVICE INCLUDING ELECTRICAL, ELECTRONIC, ELECTROMECHANICAL OR ELECTROOPTICAL COMPONENTS HAVING REDUCED SENSITIVITY AT A LOW DOSE RATE - A device for a space application, the device including at least one electronic, electromechanical or electro-optical component encapsulated in a package, the package comprising a hydrogen getter guaranteeing resistance to ionizing radiation and in particular at a low dose rate, responsible for ELDRS behavior. In one embodiment, the package may include a cap that hermetically seals a package base. Advantageously, a process may be implemented in order to promote the migration of hydrogen molecules or H+ protons toward the getter and trap said molecules or protons in the getter for the useful lifetime of the component. | 08-15-2013 |
| 20130221500 | System-In-Package with Integrated Socket - There are disclosed herein various implementations of a system-in-package with integrated socket. In one such implementation, the system-in-package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, an interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The interposer is configured to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors. In addition, a socket encloses the first and second active dies and the interposer, the socket being electrically coupled to at least one of the first active die, the second active die, and the interposer. | 08-29-2013 |
| 20130249064 | STACKED PACKAGE AND METHOD OF MANUFACTURING STACKED PACKAGE - According to an embodiment, there are provided a semiconductor chip having a semiconductor element formed thereon, a pad electrode formed on the semiconductor chip and connected to the semiconductor element, a resin layer formed on the semiconductor chip, a foundation insulating layer on which an electronic element and an internal electrode are formed, a hollow body formed on the foundation insulating layer to cover the electronic element and having a top surface side embedded in the resin layer, an opening portion formed on the foundation insulating layer and configured to expose a back surface of the internal electrode, and a conductive layer configured to connect the pad electrode and the internal electrode through the opening portion. | 09-26-2013 |
| 20130292808 | SEMICONDUCTOR PACKAGE INTEGRATED WITH CONFORMAL SHIELD AND ANTENNA - A semiconductor package includes a substrate, a semiconductor die, a package body, an electromagnetic interference shield, a dielectric structure and an antenna element. The substrate comprises a grounding segment and a feeding point. The semiconductor die is disposed on the substrate. The package body encapsulates the semiconductor die. The electromagnetic interference shield is formed on the package body. The dielectric structure encapsulates the electromagnetic interference shield. The antenna element is formed on the dielectric structure and electrically connecting the grounding segment of the substrate and the feeding point. | 11-07-2013 |
| 20140027887 | WAFER BACKSIDE DOPING FOR THERMAL NEUTRON SHIELDING - A semiconductor device includes a semiconductor substrate and at least one integrated circuit formed on a frontside of the semiconductor substrate. A shielding layer is formed on a backside of the semiconductor substrate. The shielding layer includes one or more elements having a high thermal neutron absorption cross section. | 01-30-2014 |
| 20150069588 | RADIATION HARDENED MICROELECTRONIC CHIP PACKAGING TECHNOLOGY - A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation. | 03-12-2015 |
| 20150380336 | PACKAGED SEMICONDUCTOR CHIPS WITH ARRAY - A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. | 12-31-2015 |
