| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257657000 | Stepped profile | 9 |
| 20110221045 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device with a high breakdown voltage yield of a bipolar transistor and a high bandwidth and quantum efficiency of a light receiving element. An optical semiconductor device includes monolithically integrated transistor and light receiving element. The light receiving element includes a p-type semiconductor layer, an n-type epitaxial layer formed on the p-type semiconductor layer, and an n-type diffusion layer formed on the n-type epitaxial layer. An n-type impurity concentration of the n-type diffusion layer is 3×10 | 09-15-2011 |
| 20120007223 | Power Semiconductor Element With Two-Stage Impurity Concentration Profile - A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth. | 01-12-2012 |
| 20120032313 | SEMICONDUCTOR DEVICE HAVING LATERAL DIODE - A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer. | 02-09-2012 |
| 20130049177 | WAFER STRUCTURE FOR ELECTRONIC INTEGRATED CIRCUIT MANUFACTURING - A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits. | 02-28-2013 |
| 20130049178 | WAFER STRUCTURE FOR ELECTRONIC INTEGRATED CIRCUIT MANUFACTURING - A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits. | 02-28-2013 |
| 20140210058 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer. | 07-31-2014 |
| 20140231970 | METHOD FOR PROCESSING A CARRIER, A CARRIER, AN ELECTRONIC DEVICE AND A LITHOGRAPHIC MASK - Various embodiments provide a method for processing a carrier, the method including changing the three-dimensional structure of a mask layer arranged over the carrier so that at least two mask layer regions are formed having different mask layer thicknesses; and applying an ion implantation process to the at least two mask layer regions to form at least two implanted regions in the carrier having different implantation depth profiles. | 08-21-2014 |
| 20140339686 | Group III-V Device with a Selectively Modified Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 11-20-2014 |
| 20150130032 | ULTRA HIGH VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH CURRENT GAIN - A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region. The device further comprises a second electrode electrically connected to the fourth semiconductor region and to the fifth semiconductor region. | 05-14-2015 |
