| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257656000 | With high resistivity (e.g., "intrinsic") layer between P and N layers (e.g., PIN diode) | 32 |
| 20080217749 | Low Capacitance Transient Voltage Suppressor - A transient voltage suppressor includes a reverse bias transient voltage suppressor PN diode connected in series with a forward biased PIN diode, the series circuit formed by the PN diode and the PIN diode is connected between first and second terminals and in parallel with a reverse biased PIN diode. | 09-11-2008 |
| 20090001527 | Series-shunt switch with thermal terminal - A series-shunt switch is provided. The switch includes a PIN diode having an input electrical terminal, an output electrical terminal and a thermal terminal. The thermal terminal is configured to provide continuity of diode thermal ground with respect to a circuit thermal ground node. | 01-01-2009 |
| 20090127673 | METHOD FOR PRODUCING SEMI-CONDUCTING DEVICES AND DEVICES OBTAINED WITH THIS METHOD - A semi-conducting device has at least one layer doped with a doping agent and a layer of another type deposited on the doped layer in a single reaction chamber. An operation for avoiding the contamination of the other layer by the doping agent separates the steps of depositing each of the layers. | 05-21-2009 |
| 20090179310 | Pillar devices and methods of making thereof - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings. | 07-16-2009 |
| 20100025827 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A PIN diode has an n | 02-04-2010 |
| 20100127358 | Integration of damascene type diodes and conductive wires for memory device - A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element. | 05-27-2010 |
| 20100148324 | Dual Insulating Layer Diode With Asymmetric Interface State And Method Of Fabrication - An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors. | 06-17-2010 |
| 20100181657 | NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE - A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided. | 07-22-2010 |
| 20100187662 | Method for forming silicon film, method for forming pn junction and pn junction formed using the same - A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon. | 07-29-2010 |
| 20100258919 | SEMICONDUCTOR PATCH ANTENNA - A semiconductor patch antenna for microwave radiation having a wide pin-junction or pn-junction with the depletion region or embodiments having a separating buried oxide (SiO | 10-14-2010 |
| 20110186972 | Method for Producing a Protective Structure - A protective structure is produced by providing a semiconductor substrate with a doping of a first conductivity type. A semiconductor layer with a doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, wherein the buried layer is produced at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone with a doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone with a doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first region and the second region of the semiconductor layer. A common connection device is formed for the first dopant zone and the second dopant zone. | 08-04-2011 |
| 20120001305 | Method of Manufacturing Vertical Pin Diodes - The invention concerns a method of manufacturing a vertical PIN diode comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer, intrinsic layer and P-type layer; forming an anode contact of the vertical PIN diode by forming an anode metallization on a first portion of the P-type layer defining an anode region; forming an electrically insulating layer around the anode region such that a first portion of the intrinsic layer extends vertically between the N-type layer and the anode region and second portions of the intrinsic layer extend vertically between the N-type layer and the electrically insulating layer; forming a trench in the electrically insulating layer and in the second portions of the intrinsic layer so as to expose a portion of the N-type layer defining a cathode region and to define a sacrificial side-guard ring consisting of a portion of the electrically insulating layer that extends laterally between the trench and the anode region and laterally surrounds said anode region; and forming a cathode contact of the vertical PIN diode by forming a cathode metallization on the exposed portion of the N-type layer defining the cathode region. | 01-05-2012 |
| 20120007222 | METHOD OF MANUFACTURING DIODE, AND DIODE - The present specification provides a method of efficiently manufacturing diodes in which recovery surge voltage is hardly generated. | 01-12-2012 |
| 20120126377 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions. | 05-24-2012 |
| 20120161298 | DIODE AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT INCLUDING THE SAME - A diode includes a first region having a first conductive type impurity and formed in a first well having the first conductive type impurity, a second region formed in the first well and having a second conductive type impurity, and a semiconductor pattern disposed above the first well and including a first portion having the first conductive type impurity and a second portion having the second conductive type impurity. The first region and the first portion are coupled with an anode, and the second region and the second portion are coupled with a cathode. | 06-28-2012 |
| 20120256304 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - This semiconductor device includes: a substrate; and a plurality of thin-film diodes which are supported by the substrate and electrically connected in parallel with each other. The thin-film diodes include at least one thin-film diode of a first type ( | 10-11-2012 |
| 20120299163 | PIN DIODE - Provided is a PIN diode that can suppress thermal destruction from occurring at the time of a reverse bias exceeding a breakdown voltage by current concentration on a curved part of an anode region. The PIN diode is configured to have: a semiconductor substrate | 11-29-2012 |
| 20120299164 | PIN DIODE - A PIN diode having improved avalanche resistance is provided. The PIN diode includes: a semiconductor substrate | 11-29-2012 |
| 20120306060 | Protective Structure - A protective structure is produced by providing a semiconductor substrate having doping of a first conductivity type. A semiconductor layer having doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, producing a layer at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone having doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone having doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first and second regions of the semiconductor layer. A common connection device is formed for the first and second dopant zones. | 12-06-2012 |
| 20130043567 | Method For Forming Silicon Film, Method For Forming PN Junction And PN Junction Formed Using The Same - A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon. | 02-21-2013 |
| 20130093066 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer. | 04-18-2013 |
| 20130175675 | METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE - A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided. | 07-11-2013 |
| 20130334670 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer. | 12-19-2013 |
| 20130341771 | PROTECTIVE STRUCTURE - A protective structure may include: a semiconductor substrate having a doping of a first conductivity type; a semiconductor layer having a doping of a second conductivity type arranged at a surface of the semiconductor substrate; a buried layer having a doping of the second conductivity type arranged in a first region of the semiconductor layer and at the junction between the semiconductor layer and the semiconductor substrate; a first dopant zone having a doping of the first conductivity type arranged in the first region of the semiconductor layer above the buried layer; a second dopant zone having a doping of the second conductivity type arranged in a second region of the semiconductor layer; an electrical insulation arranged between the first region and the second region of the semiconductor layer; and a common connection device for the first dopant zone and the second dopant zone. | 12-26-2013 |
| 20140001608 | SEMICONDUCTOR SUBSTRATE HAVING HIGH AND LOW-RESISTIVITY PORTIONS | 01-02-2014 |
| 20140061876 | METHOD OF MANUFACTURING VERTICAL PIN DIODES - Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region. | 03-06-2014 |
| 20140117514 | METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE - A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided. | 05-01-2014 |
| 20140124905 | VIBRATION NOISE SHIELD IN A SEMICONDUCTOR SENSOR - A semiconductor device comprises a substrate, a cathode, an outer ring, an anode, an electrically insulating layer, and an electrically conducting layer. The substrate includes a semiconducting material having a first conduction type. The substrate has a first face and a second face substantially parallel to the first face. A cathode is disposed at the second face and has the first conduction type. An outer ring, having the first conduction type, is disposed at an outer perimeter of the first face of the substrate. An anode, having the second conduction type, is disposed at the first face of the substrate within an inner perimeter of the outer ring. An electrically insulating layer is disposed over the outer ring. An electrically conducting layer is disposed over the electrically insulating layer and over the outer ring. The electrically conducting layer electrically is insulated from the outer ring by the electrically insulating layer. | 05-08-2014 |
| 20150061090 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a drift layer having a first conductive type; a first semiconductor layer having a second conductive type and arranged in a surface portion of the drift layer; a second semiconductor layer having the first conductive type, arranged at a position of the drift layer spaced apart from the first semiconductor layer, and having a carrier density larger than the drift layer; a hole injection layer having the second conductive type and arranged selectively in the second semiconductor layer; a first electrode electrically connecting to the first semiconductor layer; a second electrode electrically connecting to the second semiconductor layer and the hole injection layer. The second semiconductor layer has a carrier density smaller than a spatial charge density. | 03-05-2015 |
| 20160027952 | Pin Diode and Manufacturing Method Thereof, and X-Ray Detector Using Pin Diode and Manufacturing Method Thereof - Provided herein is a PIN diode, a manufacturing method thereof, an x-ray detector using the PIN diode, and a manufacturing method thereof, the PIN diode manufacturing method according to an embodiment of the present disclosure including forming a lower electrode layer, and forming a lower electrode by etching the lower electrode layer; depositing a PIN layer for formation of a PIN structure above the lower electrode, and depositing an upper electrode layer for formation of the upper electrode above the PIN layer; forming a photo resist pattern above the upper electrode layer, and forming the upper electrode by etching the upper electrode layer having the photo resist pattern as a mask; forming the PIN structure by etching the PIN layer; etching an edge area of the upper electrode having the photo resist pattern as a mask; and removing the photo resist pattern. | 01-28-2016 |
| 20160056305 | SEMICONDUCTOR DEVICE - A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously. | 02-25-2016 |
| 20160079442 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND PIN DIODE | 03-17-2016 |
