| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257640000 | At least one layer of silicon nitride | 19 |
| 20080203541 | Semiconductor device and manufacturing method of the same - A protective insulation film covering a surface of a compound semiconductor region is formed to have a two-layer structure of a first insulation film and a second insulation film which have different properties. The first insulation film is a non-stoichiometric silicon nitride film while the second insulation film is a silicon nitride film in an almost stoichiometric state. | 08-28-2008 |
| 20080211066 | BARRIER FILM AND METHOD OF PRODUCING BARRIER FILM - A barrier film formed on top of a substrate, a barrier film formed so as to cover a functional element region fabricated on top of a substrate, or a barrier film formed on both a substrate and a functional element region, wherein the barrier film includes at least one layer of a silicon nitride film formed by laminating two or more silicon nitride layers having different Si/N composition ratios. | 09-04-2008 |
| 20090166814 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL - A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased. | 07-02-2009 |
| 20090166815 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a compound semiconductor laminated structure having a plurality of compound semiconductor layers formed over a semiconductor substrate, a first insulation film covering at least a part of a surface of the compound semiconductor laminated structure, and a second insulation film formed on the first insulation film, wherein the second insulation film includes more hydrogen than the first insulation film. | 07-02-2009 |
| 20090267199 | ISOLATION LAYER HAVING A BILAYER STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench. | 10-29-2009 |
| 20090289333 | Annealing a Buffer Layer for Fabricating Electronic Devices on Compliant Substrates - A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing. | 11-26-2009 |
| 20100270658 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A method is disclosed for producing a semiconductor device produced by (i) doping hydrogen ions or rare gas ions into a device substrate in which a transfer layer ( | 10-28-2010 |
| 20100276790 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL - A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased. | 11-04-2010 |
| 20110169141 | INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS - A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO | 07-14-2011 |
| 20110241184 | INTEGRATED CIRCUIT DEVICES HAVING SELECTIVELY STRENGTHENED COMPOSITE INTERLAYER INSULATION LAYERS AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location. | 10-06-2011 |
| 20120098108 | PASSIVATION FILM FOR ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a passivation film for an electronic device having a nitride film formed on a substrate by a plasma-enhanced chemical vapor deposition (PECVD) method using a silicon-containing gas and a nitrogen-containing gas and a plasma-processed film formed by plasma processing a surface of the nitride film by a PECVD method using an NH | 04-26-2012 |
| 20130075875 | SILICON NITRIDE FILM OF SEMICONDUCTOR ELEMENT, AND METHOD AND APPARATUS FOR PRODUCING SILICON NITRIDE FILM - Disclosed are: a silicon nitride film of a semiconductor element, which is formed by applying a bias power and appropriately controls hydrogen leaving from the silicon nitride film; and a method and apparatus for producing a silicon nitride film. Specifically disclosed is a silicon nitride film which is formed on a substrate ( | 03-28-2013 |
| 20130082362 | Semiconductor Device and Manufacturing Method thereof - A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process. | 04-04-2013 |
| 20130161799 | Patterned Semiconductor Bases, and Patterning Methods - Some embodiments include patterning methods. First and second masking features may be formed over first and second regions of a semiconductor base, respectively. A protective mask may be formed over the second masking features. First and second spacers may be formed along sidewall edges of the first masking features and along lateral edges of the protective mask, respectively. The protective mask and the first masking features may be removed without removing the second masking features, without removing the first spacers, and without removing the second spacers. The first spacers may be third masking features that are at a tighter pitch than the first masking features. Patterns of the second masking features and the third masking features may be transferred into the semiconductor base. Some embodiments include patterned semiconductor bases. | 06-27-2013 |
| 20140077343 | DUMMY WAFER STRUCTURE AND METHOD OF FORMING THE SAME - A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity. | 03-20-2014 |
| 20140264782 | FORMATION OF A HIGH ASPECT RATIO CONTACT HOLE - A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole. | 09-18-2014 |
| 20150028459 | METHOD FOR SEMICONDUCTOR SELF-ALIGNED PATTERNING - A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; | 01-29-2015 |
| 20160203971 | GATE STACK MATERIALS FOR SEMICONDUCTOR APPLICATIONS FOR LITHOGRAPHIC OVERLAY IMPROVEMENT | 07-14-2016 |
| 257641000 | Combined with glass layer | 1 |
| 20090166816 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device may include: forming an oxide film pattern and a poly film pattern over a semiconductor substrate to expose a portion of the surface of the semiconductor substrate; and then forming a spacer composed of a first insulating material on sidewalls of the oxide film pattern and the poly film pattern; and then forming a second insulating film over the semiconductor substrate including the spacer and the poly film, the second insulating film having a first portion formed over the exposed portion of the semiconductor substrate, a second portion formed over the poly film pattern and a third portion formed at an incline between the first and second portions. | 07-02-2009 |
