| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257637000 | Three or more insulating layers | 45 |
| 20080224275 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film. | 09-18-2008 |
| 20080246125 | Semiconductor device and method for manufacturing semiconductor device - The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a hard mask layer having a film containing silicon and oxygen formed on the barrier layer, wherein the barrier layer consists of a silicon nitride film and a film containing silicon, carbon, and nitride that are laminated from the bottom in that order, and functions to prevent the fluorine in the fluorine added carbon film from moving to the hard mask layer. | 10-09-2008 |
| 20080258271 | Multi-dielectric films for semiconductor devices and methods of fabricating multi-dielectric films - A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials. | 10-23-2008 |
| 20080296741 | SEMICONDUCTOR DEVICE - Passivation films including first and second layers (first passivation film) are formed on a GaAs substrate (semiconductor substrate). A SiN film (second passivation film) is formed on the passivation films as a top layer passivation film by a catalytic chemical vapor deposition. The SiN film formed by catalytic chemical vapor deposition has a lower degree of hygroscopicity than that of a conventional SiN film formed by plasma chemical vapor deposition. | 12-04-2008 |
| 20080296742 | SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING THEREOF - A semiconductor device having silicon-oxide-nitride-oxide-silicon (SONOS) structure that overcomes spatial limitations which trap charges by not utilizing a flat, planar structure of the ONO film including a charging trap layer, thereby making it possible to improve reliability for data preserving characteristic of a SONOS device. | 12-04-2008 |
| 20080296743 | Semiconductor device and method for fabricating the same - The present invention relates to a semiconductor device, and a method for fabricating a semiconductor device, which involves an oxide-nitride-oxide stack in a silicon-oxide-nitride-oxide-silicon device. Barrier characteristics of an upper blocking dielectric layer and/or a lower tunneling dielectric layer on upper and lower sides of a charge trapping dielectric layer are improved, so as to maintain holding characteristics of charges trapped in the charge trapping dielectric layer, making it possible to improve reliability of a semiconductor device containing the same. | 12-04-2008 |
| 20090085175 | SEMICONDUCTOR DEVICE CONTAINING A BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYER AND METHOD OF FORMING - A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described. | 04-02-2009 |
| 20090091004 | SEMICONDUCTOR DEVICE - A semiconductor device according to one aspect of the present invention includes a semiconductor substrate, an interlayer insulating film formed over the semiconductor substrate, a metal wiring formed over the interlayer insulating film, a protective insulating film formed on the metal wiring, and a resin film formed within a region having one side shorter than a predetermined length on the protective insulating film. The resin film covers all regions in which an interval of the metal wirings is equal to or less than a predetermined interval. | 04-09-2009 |
| 20090140397 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes capacitors formed on the surface of an interlayer insulating film in connection with capacitive contact plug, wherein capacitors are constituted of base-side lower electrode films having hollow-pillar shapes, metal plugs embedded in hollows of base-side lower electrode films, and top-side lower electrode films having hollow-pillar shapes engaged with the upper portions of the hollows as well as dielectric films and upper electrode films which are sequentially laminated so as to cover the peripheral surfaces of the base-side and top-side lower electrode films and the interior surfaces of the top-side lower electrode films. Side walls are further formed to connect together the adjacent base-side lower electrode films. Thus, it is possible to control the aspect ratio of a capacitor hole for embedding the metal plug from being excessively increased, and it is possible to increase the capacitive electrode area of each capacitor. | 06-04-2009 |
| 20090184401 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto. | 07-23-2009 |
| 20090321895 | SILICON THIN-FILM AND METHOD OF FORMING SILICON THIN-FILM - Issue Providing a silicon film which can prevent damage of electronic devices formed on a substrate from occurrence, can prevent apparatus arrangement from becoming large-scale one, can improve coherency of a silicon thin film to a substrate, and is hardly happened crack and/or flaking, and providing a method for forming the silicon thin film. | 12-31-2009 |
| 20100155909 | METHOD TO ENHANCE CHARGE TRAPPING - Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device. | 06-24-2010 |
| 20110012238 | ENGINEERED INTERCONNECT DIELECTRIC CAPS HAVING COMPRESSIVE STRESS AND INTERCONNECT STRUCTURES CONTAINING SAME - A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability. | 01-20-2011 |
| 20110012239 | Barrier Layer On Polymer Passivation For Integrated Circuit Packaging - A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues. | 01-20-2011 |
| 20110062561 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device comprising: forming a p type region and an n type region in a main surface of a semiconductor substrate, the p type region and the n type region being insulated from each other with an element-isolation region; forming a first insulating film on the p type region and on the n type region, the first insulating film being made of any one of a silicon oxide film and a silicon oxynitride film; forming a lanthanum oxide film on the first insulating film on the p type region; forming a second insulating film both on the lanthanum oxide film on the p type region and on the first insulating film on the n type region, the second insulating film containing any one of hafnium and zirconium; and forming a titanium nitride film on the second insulating film, the titanium nitride film satisfying Ti | 03-17-2011 |
| 20110108962 | SEMICONDUCTOR DEVICE HAVING A DEVICE ISOLATION STRUCTURE - An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer. | 05-12-2011 |
| 20110215447 | SEMICONDUCTOR CHIP WITH SEAL RING AND SACRIFICIAL CORNER PATTERN - A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner. | 09-08-2011 |
| 20110227203 | Method of Providing a Semiconductor Device With a Dielectric Layer and Semiconductor Device Thereof - In some embodiments, a method of providing a semiconductor device can include: (a) providing a substrate; (b) depositing a first metal layer over the substrate; (c) spin-coating a first dielectric material over the first metal layer, where the first dielectric material includes an organic siloxane-based dielectric material; and (d) depositing a second dielectric material comprising silicon nitride over the first dielectric material. Other embodiments are disclosed in this application. | 09-22-2011 |
| 20120007221 | MASK FOR FORMING INTEGRATED CIRCUIT - A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask. | 01-12-2012 |
| 20120074537 | DIELECTRIC STACK - A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness T | 03-29-2012 |
| 20120146196 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer. | 06-14-2012 |
| 20120161297 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus. | 06-28-2012 |
| 20120193768 | MULTIPLE-LAYER, MULTIPLE FILM HAVING THE SAME AND ELECTRONIC DEVICE HAVING THE SAME - The present invention provides a multiple layer that comprises two or more first inorganic material layers; and one or more second inorganic material layers that are positioned between the two first inorganic material layers and have the thickness of less than 5 nm, in which the first inorganic material layer is formed of one or more materials that are selected from silicon oxides, silicon carbide, silicon nitride, aluminum nitride and ITO, and the second inorganic material layer is formed of one or more materials that are selected from magnesium, calcium, aluminum, gallium, indium, zinc, tin, barium, and oxides and fluorides thereof, a multiple film that comprises the multiple layer, and an electronic device that comprises the multiple film. | 08-02-2012 |
| 20120223419 | METHOD FOR CONTROLLING THE DISTRIBUTION OF STRESSES IN A SEMICONDUCTOR-ON-INSULATOR TYPE STRUCTURE AND CORRESPONDING STRUCTURE - A method for controlling the distribution of the stresses in a structure of the semiconductor-on-insulator type during its manufacturing, which includes a thin layer of semiconducting material on a supporting substrate and an insulating layer present on each of the front and rear faces of the supporting substrate, with the insulating layer on the front face forming at least one portion of a thick buried insulator (BOX) layer. The method includes the adhesive bonding of the thin layer onto the supporting substrate. Prior to this adhesive bonding, the insulating layer on the rear face of the supporting substrate is covered with a distinct material that is capable of withstanding deoxidation. The covering material, in combination with this insulating layer on the rear face of the supporting substrate, at least partly compensates for the stress exerted by the buried insulator (BOX) on the supporting substrate. | 09-06-2012 |
| 20120299162 | BARRIER FILM FOR ELECTRONIC DEVICE, METHOD OF MANUFACTURE THEREOF, AND ARTICLES INCLUDING THE SAME - A barrier film for an electronic device, the barrier film including: a resin film; a layer-by-layer stack portion including a tabular inorganic particle layer and a binder layer which are alternately disposed on the resin film and are oppositely charged; and a filling portion that fills a defect portion of the tabular inorganic particle layer wherein the defect portion is a portion of the tabular inorganic particle layer where a tabular inorganic particle of the tabular inorganic particle layer is not present. | 11-29-2012 |
| 20130075874 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure. | 03-28-2013 |
| 20130093064 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process. | 04-18-2013 |
| 20130134564 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device implemented with structures to suppress leakage current generation during operation and a method of making the same is provided. The semiconductor device includes a semiconductor substrate of first conductivity type, a second insulation film, which has at least one aperture between first and second apertures, formed on top of a first insulation film. The semiconductor device layer structure accommodates tensile stress differences between device layers to suppress lattice dislocation defects during device manufacturing and thus improves device reliability and performance. | 05-30-2013 |
| 20130147022 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include an interlayer insulating layer containing hydrogen and a first passivation layer configured to prevent or inhibit an out-gassing of the hydrogen. In the method, a second passivation layer configured to control a warpage characteristic of a wafer may be formed on the first passivation layer. | 06-13-2013 |
| 20130193565 | SEMICONDUCTOR MASK BLANKS WITH A COMPATIBLE STOP LAYER - Provided is a method for creating a mask blank that include a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detect of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer. | 08-01-2013 |
| 20130249062 | FILM EMBEDDING METHOD AND SEMICONDUCTOR DEVICE - A method of forming an embedded film comprises depositing a first layer on a second layer that is disposed on a substrate and includes a material different from materials included in the first layer, forming an aperture through the first layer and into the second layer, the aperture having a side surface that includes an exposed portion of the first layer and an exposed portion of the second layer, bringing a material that includes organic molecules into contact with the exposed portion of the first layer and the exposed portion of the second layer to form a monomolecular film that covers the side surface, and forming the embedded film in the aperture with a material having a high enough affinity to the monomolecular film to substantially fill the aperture. | 09-26-2013 |
| 20140001607 | PASSIVATION SCHEME | 01-02-2014 |
| 20140061873 | METHOD FOR PROCESSING A WAFER, AND LAYER ARRANGEMENT - A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer. | 03-06-2014 |
| 20140239462 | PECVD FILMS FOR EUV LITHOGRAPHY - Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography. | 08-28-2014 |
| 20140246760 | Charge Protection for III-Nitride Devices - A semiconductor device includes a III-nitride semiconductor substrate having a two-dimensional charge carrier gas at a depth from a main surface of the III-nitride semiconductor substrate. A surface protection layer is provided on the main surface of the III-nitride semiconductor substrate. The surface protection layer has charge traps in a band gap which exist at room temperature operation of the semiconductor device. A contact is provided in electrical connection with the two-dimensional charge carrier gas in the III-nitride semiconductor substrate. A charge protection layer is provided on the surface protection layer. The charge protection layer includes an oxide and shields the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of silicon nitride. | 09-04-2014 |
| 20140284773 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, a first electrode which extends in a first direction and is surrounded by the first semiconductor layer except at one end thereof, and a first insulation film which is formed between the first semiconductor layer and the first electrode. A film thickness of the first insulation film between the other end of the first electrode in a second direction opposite to the first direction and the first semiconductor layer includes a thickness that is greater than a thickness of the first insulation film along a side surface of the first electrode. The semiconductor device also includes a second electrode which faces the second semiconductor layer, and a second insulation film which is formed between the second electrode and the second semiconductor layer. | 09-25-2014 |
| 20150048488 | Semiconductor Devices, Methods of Manufacture Thereof, and Inter-metal Dielectric (IMD) Structures - Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure. | 02-19-2015 |
| 20150054143 | PASSIVATION STRUCTURE AND METHOD OF MAKING THE SAME - A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer. | 02-26-2015 |
| 20150061088 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer. | 03-05-2015 |
| 20150137333 | METHODS OF SELECTIVELY FORMING A MATERIAL USING A PARYLENE COATING AND RELATED SEMICONDUCTOR STRUCTURES - Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures. | 05-21-2015 |
| 20150311308 | ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS - Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al | 10-29-2015 |
| 20160035616 | HANDLER WAFER REMOVAL BY USE OF SACRIFICIAL INERT LAYER - The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer. | 02-04-2016 |
| 20160086868 | PASSIVATION STRUCTURE AND METHOD OF MAKING THE SAME - A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer. | 03-24-2016 |
| 20160141263 | SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE - According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface. | 05-19-2016 |
| 20160172450 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | 06-16-2016 |
