Class / Patent application number | Description | Number of patent applications / Date published |
257627000 | With specified crystal plane or axis | 62 |
20080224274 | Semiconductor device, semiconductor display device, and manufacturing method of semiconductor device - To achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way. In addition, to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which crystal faces and/or crystal axes of single-crystalline semiconductor layers of a first conductive MISFET and a second conductive MISFET are different. The crystal faces and/or crystal axes are arranged so that mobility of carriers flowing in channel length directions in the respective MISFETs is increased. Such a structure can increase mobility of carriers flowing through channels of the MISFETs and high speed operation of a semiconductor integrated circuit can be achieved. Further, low voltage driving becomes possible, and low power consumption can be realized. | 09-18-2008 |
20080265379 | Laser Diode Orientation on Mis-Cut Substrates - A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate ( | 10-30-2008 |
20080315370 | FABRICATION OF OPTICAL-QUALITY FACETS VERTICAL TO A (001) ORIENTATION SUBSTRATE BY SELECTIVE EPITAXIAL GROWTH - Methods for forming {110} type facets on a (001) oriented substrate of Group III-V compounds and Group IV semiconductors using selective epitaxial growth is provided. The methods include forming a dielectric film on a (100) substrate. The dielectric film can then be patterned to expose a portion of the substrate and to form a substrate-dielectric film boundary substantially parallel to a <110> direction. A {110} type sidewall facet can then be formed by epitaxially growing a semiconductor layer on the exposed portion of the substrate and the dielectric film. | 12-25-2008 |
20090001523 | Systems and Methods for Processing a Film, and Thin Films - In some embodiments, a method of processing a film is provided, the method comprising defining a plurality of spaced-apart regions to be pre-crystallized within the film, the film being disposed on a substrate and capable of laser-induced melting; generating a laser beam having a fluence that is selected to form a mixture of solid and liquid in the film and where a fraction of the film is molten throughout its thickness in an irradiated region; positioning the film relative to the laser beam in preparation for at least partially pre-crystallizing a first region of said plurality of spaced-apart regions; directing the laser beam onto a moving at least partially reflective optical element in the path of the laser beam, the moving optical element redirecting the beam so as to scan a first portion of the first region with the beam in a first direction at a first velocity, wherein the first velocity is selected such that the beam irradiates and forms the mixture of solid and liquid in the first portion of the first region, wherein said first portion of the first region upon cooling forms crystalline grains having predominantly the same crystallographic orientation in at least a single direction; and crystallizing at least the first portion of the first region using laser-induced melting. | 01-01-2009 |
20090008749 | Device made of single-crystal silicon - A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a | 01-08-2009 |
20090039473 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second side closer to the lower surface, exposing a portion where the dislocation concentrated region does not exist above on the lower surface by removing the substrate on the second side along with at least a part of the dislocation concentrated region, and forming an electrode on the portion. | 02-12-2009 |
20090057847 | Gallium nitride wafer - A gallium nitride wafer | 03-05-2009 |
20090146262 | INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECHNOLOGY - An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate. | 06-11-2009 |
20090146263 | STRUCTURE AND METHOD TO INCREASE EFFECTIVE MOSFET WIDTH - An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI. | 06-11-2009 |
20090152684 | MANUFACTURE-FRIENDLY BUFFER LAYER FOR FERROELECTRIC MEDIA - The present invention describes a method including: providing a substrate; forming a buffer layer epitaxially over the substrate with a manufacture-friendly process; forming a bottom electrode epitaxially over the buffer layer; and forming a ferroelectric layer epitaxially over the bottom electrode. | 06-18-2009 |
20090236698 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability. | 09-24-2009 |
20090302432 | SILICON EPITAXIAL WAFER AND THE PRODUCTION METHOD THEREOF - A silicon epitaxial wafer obtained by growing a silicon epitaxial layer on a surface of a silicon wafer having a diameter of at least 300 mm produced by slicing a silicon single crystal ingot doped with boron and germanium grown by the Czochralski method, wherein boron is doped to be at a concentration of 8.5×10 | 12-10-2009 |
20100019355 | Multi-Level Nanowire Structure And Method Of Making The Same - A method for making a multi-level nanowire structure includes establishing a first plurality of nanowires on a substrate surface, wherein at least some of the nanowires are i) aligned at a predetermined crystallographically defined angle with respect to the substrate surface, ii) aligned substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii. An insulating layer is established between the nanowires of the first plurality such that one of two opposed ends of at least some of the nanowires positioned i) at the predetermined crystallographically defined angle, ii) substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii is exposed. Regions are grown from each of the exposed ends, and such regions coalesce to form a substantially continuous layer on the insulating layer. A second plurality of nanowires is established on the substantially continuous layer. | 01-28-2010 |
20100025826 | Field Effect Transistors with Channels Oriented to Different Crystal Planes - An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface. | 02-04-2010 |
20100038756 | (110) ORIENTED SILICON SUBSTRATE AND A BONDED PAIR OF SUBSTRATES COMPRISING SAID (110) ORIENTED SILICON SUBSTRATE - The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates comprising a first silicon substrate with (100) orientation and a second silicon substrate with (110) orientation. It is the object of the present invention to provide methods and substrates of the above mentioned type with a high efficiency wherein the formed (110) substrate has at least near and at its surface virtually no defects. The object is solved by a method of fabricating a silicon substrate with (110) orientation and by a method of fabricating a bonded pair of silicon substrates, comprising the steps of providing a basic silicon substrate with (110) orientation, said basic silicon substrate having a roughness being equal or less than 0.15 nm RMS in a 2×2 μm | 02-18-2010 |
20100052113 | EPITAXIAL FILM, PIEZOELECTRIC ELEMENT, FERROELECTRIC ELEMENT, MANUFACTURING METHODS OF THE SAME, AND LIQUID DISCHARGE HEAD - There are disclosed an epitaxial film, comprising: heating an Si substrate provided with an SiO | 03-04-2010 |
20100072580 | ULTRA-THIN OXIDE BONDING FOR SI TO SI DUAL ORIENTATION BONDING - A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms. | 03-25-2010 |
20100117203 | OXIDE-CONTAINING FILM FORMED FROM SILICON - A process for forming an oxide-containing film from silicon is provided that includes heating the silicon substrates to a process temperature of between 250° C. and 1100° C. with admission into the process chamber of diatomic reductant source gas Z-Z′ where Z and Z′ are each H, D and T and a stable source of oxide ion. Multiple exhaust ports exist along the vertical extent of the process chamber to create reactant across flow. A batch of silicon substrates is provided having multiple silicon base layers, each of the silicon base layers having exposed <110> and <100> planes and a film residual stress associated with the film being formed at a temperature of less than 600° C. and having a <110> film thickness that exceeds a <100> film thickness on the <100> crystallographic plane by less than 20%, or a film characterized by thickness anisotropy less than 18% and an electrical breakdown field of greater than 10.5 MV/cm. | 05-13-2010 |
20100148318 | Three-Dimensional Semiconductor Template for Making High Efficiency Thin-Film Solar Cells - A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template. | 06-17-2010 |
20100148319 | Substrates for High-Efficiency Thin-Film Solar Cells Based on Crystalline Templates - A three-dimensional thin-film semiconductor substrate having a plurality of ridges on the surface of the semiconductor substrate which define a base opening of an inverted pyramidal cavity and walls defining the inverted pyramidal cavity is provided. And a fabrication method for a 3-D TFSS by forming a porous silicon layer on a silicon template having a top surface aligned along a (100) crystallographic orientation plane of the silicon template and a plurality of walls each aligned along a (111) crystallographic orientation plane of the silicon template and forming an inverted pyramidal cavity. The porous silicon layer forms substantially conformal on the silicon template. Then forming a substantially conformal epitaxial silicon layer on the porous silicon layer and releasing the epitaxial silicon layer from the silicon template. | 06-17-2010 |
20100148320 | VICINAL GALLIUM NITRIDE SUBSTRATE FOR HIGH QUALITY HOMOEPITAXY - A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm | 06-17-2010 |
20100187660 | Method To Create SOI Layer For 3D-Stacking Memory Array - A 3-D stacked semiconductor device is formed by forming a trench is formed through a top surface in a dielectric layer to expose the crystalline silicon layer having a (100) crystal plane, such that the trench walls are parallel to a <100> direction. Epitaxial silicon is grown between the trench walls to a level that is below the top surface of the dielectric layer. Epitaxial silicon is laterally grown using the top portion of the epitaxially grown silicon as a seed to form a laterally grown epitaxial layer having a (100) crystal plane on the dielectric layer. | 07-29-2010 |
20100200962 | SILOCON WAFER SUPPORTING METHOD, HEAT TREATMENT JIG AND HEAT-TREATED WAFER - Provided is a method applicable to the production of silicon wafers having crystal orientation <100> or <110> and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment jig for use in carrying out that method. It becomes possible to suppress the shear stress which contributes to the extension of the slip generated at each wafer-supporting element contact point as an initiation, suppress slip growth and thus markedly improve the yield of heat-treated silicon wafers. The heat-treated wafer obtained by using the supporting method and the heat treatment jig has few slip, in particular has no long and large slip, and is high in quality. | 08-12-2010 |
20100237474 | Unpolished Semiconductor Wafer and Method For Producing An Unpolished Semiconductor Wafer - Unpolished semiconductor wafers are produced by: (a) pulling a single crystal of a semiconductor material, (b) grinding the single crystal round, (c) separating a semiconductor wafer from this crystal, (d) rounding the edge of the semiconductor wafer, (e) surface-grinding at least one side of the semiconductor wafer, (f) treating the semiconductor wafer with an etchant, and (g) cleaning the semiconductor wafer. The unpolished semiconductor wafers have, on at least the front side, a reflectivity of 95% or more, a surface roughness of 3 nm or less, have a thickness of 80-2500 μm, an overall planarity value GBIR of 5 μm or less with an edge exclusion of 3 mm and a photolithographic resolution of at least 0.8 μm, and which furthermore contain a native oxide layer with a thickness of 0.5-3 nm on both sides. | 09-23-2010 |
20100314722 | SOI WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SOI WAFER - The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 Ω·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer. | 12-16-2010 |
20110031592 | SILICON EPITAXIAL WAFER AND METHOD FOR PRODUCTION THEREOF - Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode). | 02-10-2011 |
20110037150 | SUBSTRATE COMPRISING DIFFERENT TYPES OF SURFACES AND METHOD FOR OBTAINING SUCH SUBSTRATES - A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized. | 02-17-2011 |
20110049681 | Semiconductor Structure and a Method of Forming the Same - Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate. | 03-03-2011 |
20110079883 | FERROELECTRIC THIN FILM - Provided is a ferroelectric thin film formed on a substrate and having an amount of remanent polarization increased in its entirety. The ferroelectric thin film contains a perovskite-type metal oxide formed on a substrate, the ferroelectric thin film containing a column group formed of multiple columns each formed of a spinel-type metal oxide, in which the column group is in a state of standing in a direction perpendicular to a surface of the substrate, or in a state of slanting at a slant angle in a range of −10° or more to +10° or less with respect to the perpendicular direction. | 04-07-2011 |
20110121434 | METHOD OF FABRICATING A PLANAR SEMICONDUCTOR NANOWIRE - A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semi-conductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane. | 05-26-2011 |
20110193201 | METHOD TO FABRICATE AND TREAT A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE, ENABLING DISPLACEMENT OF DISLOCATIONS, AND CORRESPONDING STRUCTURE - The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate ( | 08-11-2011 |
20120104565 | EPITAXIAL WAFER AND METHOD FOR PRODUCING THE SAME - When a mixed gas of trichlorosilane and dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 1000 to 1100° C., preferably, 1040 to 1080° C. When dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 900 to 1150° C., preferably, 1000 to 1150° C. According to this, a silicon epitaxial wafer, which has low haze level, excellent flatness (edge roll-off), and reduced orientation dependence of epitaxial growth rate, and is capable of responding to the higher integration of semiconductor devices, can be obtained, and this epitaxial wafer can be used widely in production of semiconductor devices. | 05-03-2012 |
20130062738 | Single Crystal Silicon Membrane with a Suspension Layer, Method for Fabricating the Same, and a Micro-Heater - To form a single crystal silicon membrane with a suspension layer, a single crystal silicon substrate with crystal orientation <111> is prepared. A doped layer is formed on the top surface of the single crystal silicon substrate. Multiple main etching windows are formed through the doped layer. A cavity is formed through the single crystal silicon substrate by anisotropic etching. The doped layer is above the cavity to form a suspension layer. If two electrode layers are formed on the two ends of the suspension layer, a micro-heater is constructed. The main etching windows extend in parallel to a crystal plane {111}. By both the single crystal structure and different impurity concentrations of the single crystal silicon substrate, the single crystal silicon substrate has a higher etch selectivity. When a large-area cavity is formed, the thickness of the suspension layer is still controllable. | 03-14-2013 |
20130062739 | STRUCTURAL BODY AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group. | 03-14-2013 |
20130277809 | METHOD OF MANUFACTURING SILICON SINGLE CRYSTAL, SILICON SINGLE CRYSTAL, AND WAFER - P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm | 10-24-2013 |
20140103497 | PRODUCTION PROCESS FOR A MICROMECHANICAL COMPONENT AND MICROMECHANICAL COMPONENT - A production process for a micromechanical component includes at least partially structuring at least one structure from at least one monocrystalline silicon layer by at least performing a crystal-orientation-dependent etching step on an upper side of the silicon layer with a given ( | 04-17-2014 |
20140264776 | Semiconductor Wafer With A LayerOf AlzGa1-zN and Process For Producing It - A semiconductor wafer contains the following layers in the given order:
| 09-18-2014 |
20140264777 | Nanocrystalline Diamond Three-Dimensional Films in Patterned Semiconductor Substrates - An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate. | 09-18-2014 |
20140299974 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate. | 10-09-2014 |
20140361414 | Processes And Systems For Laser Crystallization Processing Of Film Regions On A Substrate Utilizing A Line-Type Beam, And Structures Of Such Film Regions - Process and system for processing a thin film sample, as well as at least one portion of the thin film structure are provided. Irradiation beam pulses can be shaped to define at least one line-type beam pulse, which includes a leading portion, a top portion and a trailing portion, in which at least one part has an intensity sufficient to at least partially melt a film sample. Irradiating a first portion of the film sample to at least partially melt the first portion, and allowing the first portion to resolidify and crystallize to form an approximately uniform area therein. After the irradiation of the first portion of the film sample, irradiating a second portion using a second one of the line-type beam pulses to at least partially melt the second portion, and allowing the second portion to resolidify and crystallize to form an approximately uniform area therein. A section of the first portion impacted by the top portion of the first one of the line-type beam pulses is prevented from being irradiated by trailing portion of the second one of the line-type beam pulses. | 12-11-2014 |
20150069583 | III NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - Provided are a III nitride semiconductor device which can be operated at a lower voltage can be provided, in which device a good ohmic contact is achieved between the (000-1) plane side of the III nitride semiconductor layer and the electrode and a method of producing the III nitride semiconductor device. A III nitride semiconductor device of the present invention includes a plurality of protrusions rounded like domes in a predetermined region on the (000-1) plane side of the III nitride semiconductor layer; and an electrode on the upper surface of the predetermined region. | 03-12-2015 |
20150102469 | SEMICONDUCTOR STRUCTURE INCLUDING LATERALLY DISPOSED LAYERS HAVING DIFFERENT CRYSTAL ORIENTATIONS AND METHOD OF FABRICATING THE SAME - A semiconductor structure includes a substrate and first and second crystalline semiconductor layers. The first crystalline semiconductor layer has a first crystal orientation, and includes a crystallized amorphous region formed on the substrate. The second crystalline semiconductor layer is formed on the substrate, is laterally disposed of the first crystalline semiconductor layer, and has a second crystal orientation different from the first crystal orientation. A method of fabricating the semiconductor structure is also disclosed. | 04-16-2015 |
20150115414 | SAPPHIRE STRUCTURE WITH METAL SUBSTRUCTURE AND METHOD FOR PRODUCING THE SAME - A sapphire structure with a metal substructure is disclosed. The sapphire structure with a metal substructure includes a sapphire structure and a metal substructure. The sapphire structure includes a flat surface and a concave portion on the flat surface. The metal substructure in the concave portion is bonded to an inner surface of the concave portion and includes a surface portion that is substantially flush with the flat surface. | 04-30-2015 |
20150295021 | INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME - A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material. | 10-15-2015 |
20150348866 | Nanocrystalline Diamond Three-Dimensional Films in Patterned Semiconductor Substrates - An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate. | 12-03-2015 |
20160013159 | CHIP, CHIP-STACKED PACKAGE USING THE SAME, AND METHOD OF MANUFACTURING THE CHIP-STACKED PACKAGE | 01-14-2016 |
20160043174 | METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE - A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line. | 02-11-2016 |
257628000 | Major crystal plane or axis other than (100), (110), or (111) (e.g., (731) axis, crystal plane several degrees from (100) toward (011), etc.) | 15 |
20080217745 | Nitride Semiconductor Wafer - A nitride semiconductor substrate having properties preferable for the manufacture of various nitride semiconductor devices is made available, by specifying or controlling the local variation in the off-axis angle of the principal surface of the nitride semiconductor substrate. The substrate, being misoriented, is manufactured to have an off-axis angle distribution across its principal surface such that variation Δθ in the off-axis angle is continuous within a predetermined angular range. | 09-11-2008 |
20090014844 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors. | 01-15-2009 |
20090267196 | HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING - The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes. | 10-29-2009 |
20100133663 | TECHNIQUE FOR THE GROWTH OF PLANAR SEMI-POLAR GALLIUM NITRIDE - A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 | 06-03-2010 |
20100187661 | Sintered Silicon Wafer - Provided is a sintered silicon wafer, wherein the ratio [I(220)/I(111) . . . (1)] of intensity of a (220) plane and intensity of a (111) plane measured by X-ray diffraction is 0.5 or more and 0.8 or less, and the ratio [I(311)/I(111) . . . (2)] of intensity of a (311) plane and intensity of a (111) plane is 0.3 or more and 0.5 or less. The provided sintered silicon wafer has a smooth surface in which its surface roughness is equivalent to a single crystal silicon. | 07-29-2010 |
20100207253 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to control the plane orientation of crystal grains obtained by using a laser beam, into a direction that can be substantially regarded as one direction in an irradiation region of the laser beam. After forming a cap film over a semiconductor film, the semiconductor film is crystallized by using a CW laser or a pulse laser having a repetition rate of greater than or equal to 10 MHz. The obtained semiconductor film has a plurality of crystal grains having a width of greater than or equal to 0.01 μm and a length of greater than or equal to 1 μm. In a surface of the obtained semiconductor film, a ratio of an orientation {211} is greater than or equal to 0.4 within the range of an angle fluctuation of ±10°. | 08-19-2010 |
20120261802 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - As a substrate for a semiconductor device, a metal substrate is used, and the metal substrate is composed of a metal base body made of a first metal and a connecting metal layer made of a second metal for covering the metal base body. The substrate has a structure wherein a diffusion preventing layer for preventing diffusion of the first metal is provided on the connecting metal layer. | 10-18-2012 |
20120319249 | SEMICONDUCTOR CHIP, SEMICONDUCTOR WAFER AND SEMICONDUCTOR CHIP MANUFACTURING METHOD - The semiconductor chip ( | 12-20-2012 |
20130026607 | INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME - A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material. | 01-31-2013 |
20130037920 | SILICON EPITAXIAL WAFER AND METHOD FOR MANUFACTURING THE SAME - The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided. | 02-14-2013 |
20130082360 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer. | 04-04-2013 |
20130168833 | METHOD FOR ENHANCING GROWTH OF SEMIPOLAR (Al,In,Ga,B)N VIA METALORGANIC CHEMICAL VAPOR DEPOSITION - A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al,In,Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In | 07-04-2013 |
20140175616 | Composite of III-Nitride Crystal on Laterally Stacked Substrates - Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms. | 06-26-2014 |
20140353804 | Method for Producing Group III Nitride Semiconductor and Group III Nitride Semiconductor - A first side surface of post of the first stripe is formed so that a plane which is most parallel to the first side surface among low-index planes of the growing Group III nitride semiconductor is a m-plane (10-10), and a first angle between the first lateral vector obtained by orthogonally projecting a normal vector of the first side surfaces to the main surface and a m-axis projected vector obtained by orthogonally projecting a normal vector of the m-plane of the growing semiconductor to the main surface is from 0.5° to 6°. A second side surface of post of the second stripe is formed so that a plane which is most parallel to the second side surface among low-index planes of the growing semiconductor is an a-plane (11-20), and a second angle between the second lateral vector and an a-axis projected vector of the a-plane is from 0° to 10°. | 12-04-2014 |
20150008563 | Composite of III-Nitride Crystal on Laterally Stacked Substrates - Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms. With x-ray diffraction FWHMs being measured along an axis defined by a <0001> direction of the substrate projected onto either of the major surfaces, FWHM peak regions are present at intervals of 3 to 5 mm width. Also, with threading dislocation density being measured along a <0001> direction of the III-nitride crystal substrate, threading-dislocation-density peak regions are present at the 3 to 5 mm intervals. | 01-08-2015 |