| Entries |
| Document | Title | Date |
|---|
| 20080197455 | Semiconductor device and manufacturing method therefor - A semiconductor device having a rectangular exterior appearance includes a substrate for arranging an integrated circuit on the surface thereof, at least one rewire electrically connected to the integrated circuit via at least one pad electrode, at least one electrode terminal formed on the rewire, and a resin layer for completely sealing the substrate including the rewire such that the electrode terminal be exposed to the exterior. Slopes are formed at the corners between the backside and the side faces of the resin layer; and other slopes are further formed at the corners between the surface and the side faces of the resin layer. Thus, it is possible to reliably prevent the semiconductor device sealed with the resin layer from chipping or peeling irrespective of an impact occurring at the corners of the resin layer. | 08-21-2008 |
| 20080203538 | Semiconductor wafer with division guide pattern - A plurality of semiconductor elements and division regions are provided on a semiconductor subsubstrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region is guided by the division guide pattern. | 08-28-2008 |
| 20080211063 | Semiconductor wafer and manufacturing method of semiconductor device - A semiconductor wafer includes a semiconductor substrate, a semiconductor layer, and an oxide layer. The semiconductor layer is disposed on a surface of the semiconductor substrate and has a crystal structure similar to a crystal structure of the semiconductor substrate. The semiconductor layer includes an element section and a scribe section. The scribe section is disposed to divide the element section into a plurality of portions and is configurated to be used as a cutting allowance for dicing. Each of the portions includes a column structure in which columns having different conductivity types are arranged alternately. The oxide layer is disposed on a surface of the scribe section to be exposed to an outside of the semiconductor device. | 09-04-2008 |
| 20080217743 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to a method of manufacturing a semiconductor device, a short-circuit wiring is formed in a region on a wafer including a dicing region, and electrode pads for input and output signals of a plurality of devices disposed in a semiconductor device forming region are electrically short-circuited by the short-circuit wiring, so that occurrence of plasma damage is suppressed even if the wafer is subjected to various plasma processes. When the wafer subjected to the plasma processes is cut along the dicing region to separate a semiconductor device, the electrical short-circuit of the electrode pads by the short-circuit wiring is released, so that the functionally unwanted short-circuit of the devices or the like is appropriately released. | 09-11-2008 |
| 20080230873 | SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF MAKING - An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor. | 09-25-2008 |
| 20080230874 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer. | 09-25-2008 |
| 20080258266 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening. | 10-23-2008 |
| 20080265378 | Scribe line layout design - A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more slots to help relieve the pressure. Alternatively, instead of metal plates, grooves that may be filled with metal could be placed into the scribe lines. These metal plates could also be used concurrently with a seal ring for better protection during sawing. | 10-30-2008 |
| 20080272464 | Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die. | 11-06-2008 |
| 20080272465 | Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die. | 11-06-2008 |
| 20080283969 | Seal Ring Structure with Improved Cracking Protection - An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines. | 11-20-2008 |
| 20080283970 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 11-20-2008 |
| 20080283971 | Semiconductor Device and Its Fabrication Method - A semiconductor device and a fabrication method thereof are disclosed. The method includes attaching a wafer with a plurality of chips on a carrier board having an insulating layer, a plurality of conductive circuits and a bottom board; forming a plurality of first grooves between solder pads of adjacent chips to expose the conductive circuits, and filling the first grooves with an insulating adhesive layer; forming second grooves in the insulating adhesive layer; and cutting among the chips to separate the chips from one another. | 11-20-2008 |
| 20080290469 | Edge Seal For a Semiconductor Device and Method Therefor - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 11-27-2008 |
| 20080315366 | SEMICONDUCTOR DEVICE - The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an a interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented. | 12-25-2008 |
| 20090001520 | THINNED WAFER HAVING STRESS DISPERSION PARTS AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME - A thinned wafer having stress dispersion parts that make the wafer resistant to warpage and a method for manufacturing a semiconductor package using the same is described. The wafer includes a wafer body having a semiconductor chip forming zone and a peripheral zone located around the semiconductor chip forming zone; and the stress dispersion parts are located in the peripheral zone so as to disperse stress induced in the peripheral zone and the semiconductor chip forming zone. | 01-01-2009 |
| 20090001521 | Semiconductor wafer - A semiconductor wafer includes an insulation substrate with transparency; a silicon semiconductor layer formed on the insulation substrate; a chip forming area defined on the silicon semiconductor layer; a scribe line area defined on the silicon semiconductor layer for dividing the chip forming area; and an opaque pattern layer formed in the scribe line area. A plurality of opaque pattern portions is arranged apart from each other in the opaque pattern layer. | 01-01-2009 |
| 20090026585 | Semiconductor Device and Method for Manufacturing the same - A semiconductor device consistent with the present invention includes a semiconductor substrate having a semiconductor chip region and a scribe region; a first insulating layer formed in the semiconductor chip region of the semiconductor substrate; a metal contact plug formed in the first insulating layer; a metal sidewall formed on a side of the first insulating layer in the scribe region; a metallization wiring electrically connected with the substrate via the metal contact plug; and a second insulating layer and a protective layer formed over the metal contact plug and the metal sidewall so as to cover the semiconductor chip region and the scribe region. | 01-29-2009 |
| 20090039470 | STRESS RELIEF OF A SEMICONDUCTOR DEVICE - A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest structure includes one of curva-linear shapes and polygonal shapes concentrically oriented around a common center located at or near at least one corner of the die. | 02-12-2009 |
| 20090039471 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: (a) a semiconductor substrate having a dicing region circumscribing a chip region, the chip region including a central region and a peripheral region around the central region; (b) an active electrical structure formed to extend from a first main surface to a second surface vertically spaced apart from the first main surface in the central region of the semiconductor substrate; (c) a through dummy isolation structure formed within the peripheral region to extend from the first main surface of the semiconductor substrate to a third surface vertically spaced apart from the first main surface of the semiconductor substrate, the through dummy isolation structure surrounding the active electrical structure; (d) an insulating layer disbursed throughout the active electrical structure within the central region and around the through dummy isolation structure of the peripheral region, the insulating layer including top and opposed peripheral sides; and (e) a metal film located over the top and peripheral sides of the wiring insulating film and over the semiconductor substrate. | 02-12-2009 |
| 20090051010 | IC package sacrificial structures for crack propagation confinement - Systems and methods for preventing damage to a unit with preventive structures are presented. In an embodiment, a unit of a collection of units includes a functional area and a preventive structure configured to prevent cracks from propagating into the functional area. | 02-26-2009 |
| 20090051011 | Semiconductor device having seal ring structure and method of forming the same - A semiconductor device of the present invention includes a seal ring structure. The seal ring structure includes a first metal layer including a though hole, the through hole having a bottom portion filled with an insulating material, and a second metal layer formed on the first metal layer. The second metal layer has a projected portion projecting from a bottom of the second metal layer and the projected portion is inserted into a top portion of the through hole. | 02-26-2009 |
| 20090057842 | SELECTIVE REMOVAL OF ON-DIE REDISTRIBUTION INTERCONNECTS FROM SCRIBE-LINES - Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region. | 03-05-2009 |
| 20090057843 | SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies. | 03-05-2009 |
| 20090065902 | METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECEIVING AN ELECTRICAL CONNECTOR - A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate on which the die is mounted. Depositing the electrical traces directly on the surface and sloped edge of the die allows the die to be electrically coupled without bond wires, thereby allowing a reduction in the overall thickness of the package. | 03-12-2009 |
| 20090065903 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. | 03-12-2009 |
| 20090079038 | Method Of Making An Integrated Circuit Including Singulating A Semiconductor Wafer - A method of making an integrated circuit includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward an other of the first surface and the second surface. The method further includes sawing a second trench in the other surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer. | 03-26-2009 |
| 20090079039 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR DESIGNING MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, a moisture resistant ring provided in the semiconductor chip and having a chamfered flat part in a position corresponding to a corner of the semiconductor chip, and a first monitor pattern formed inside the moisture resistant ring. At least a part of the first monitor pattern is disposed inside an n-sided polygonal area (n is a natural number which is 4 or higher than 4) situated within the moisture resistant ring, and outside a quadrangular area situated inside the n-sided polygonal area. The n-sided polygonal area has a vertex at least at each of a first end and a second end of the chamfered flat part, and the quadrangular area has a vertex at least at a middle point of the chamfered flat part. | 03-26-2009 |
| 20090085168 | Semiconductor device and method for manufacturing same - When a photoresist or the like is spin-coated on a semiconductor chip comprising a seal ring is formed, striation due to corners of the seal ring is suppressed. A wiring metal layer and a contact are layered, and a seal structure ( | 04-02-2009 |
| 20090091001 | CRACK RESISTANT SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a peripheral of the integrated circuit unit of the semiconductor substrate and filled with a heterogeneous material different from a material of the semiconductor substrate, and a method of fabricating the semiconductor package, comprising: at least partially forming a trench around the peripheral of the integrated circuit unit of the semiconductor substrate, and filling the trench with a heterogeneous material different from that of the semiconductor substrate. In accordance with the present invention, the structural and mechanical strength and durability of the semiconductor package, specifically, the wafer level semiconductor package, are improved and the reliability of the product is significantly improved. Furthermore, a fail rate including crack/chipping during a subsequent mounting process lowers, to improve the yield and reduce the whole manufacturing cost. | 04-09-2009 |
| 20090108410 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region. | 04-30-2009 |
| 20090115024 | Seal ring structure with improved cracking protection and reduced problems - An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line. | 05-07-2009 |
| 20090115025 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device may include a chip including a chip including a silicon substrate having a semiconductor device area, a pad area and a scribe lane defining an outer contour of the chip. A semiconductor device may be formed in the semiconductor device area, and a pad electrically connected with the semiconductor device may be formed in the pad area. A crack prevention pattern may be formed on an outer contour of the chip, such that the crack prevention pattern extends from a lowest portion to a highest portion of the semiconductor device. A crack prevention pattern is manufactured such that chip cracking can be prevented during the sawing process. | 05-07-2009 |
| 20090121322 | Semiconductor chip and semiconductor device - A semiconductor chip comprises a semiconductor substrate, a multi-layer wiring structure on the semiconductor substrate, a seal ring structure on the semiconductor substrate, and a semiconductor element arranged in an inner region of said semiconductor chip and in a frame region of said semiconductor chip. The semiconductor element comprises a chip internal circuit, the inner region is enclosed by the seal ling structure, and the seal ring structure separates the frame region as being outside of the inner region. | 05-14-2009 |
| 20090127665 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device has preparation step of preparing a semiconductor substrate having a plurality of semiconductor chip formation regions and a scribe region arranged between the plurality of the semiconductor chip formation regions and including a substrate cutting position, a semiconductor chip formation step of forming semiconductor chips having electrode pads on the plurality of semiconductor chip formation regions, a first insulation layer formation step of forming a first insulation layer on the semiconductor chips and the scribe region of the semiconductor substrate, a second insulation layer formation step of forming a second insulation layer on the first insulation layer except for a region corresponding to the substrate cutting position, and a cutting step of cutting the semiconductor substrate at the substrate cutting position. | 05-21-2009 |
| 20090127666 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK - A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in āLā shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance. | 05-21-2009 |
| 20090134494 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention includes: a semiconductor element | 05-28-2009 |
| 20090134495 | Method of designing semiconductor device - A design method of a semiconductor device comprising forming a base wafer by using a plurality of semiconductor chips including a plurality of functional macros, generating macro test information by testing the plurality of function macros of the plurality of semiconductor devices; and picking a macro that is prohibited from being used out of the plurality of function macros based on the macro test information and a net list of user circuit. Since tests are carried out at the phase of a base wafer, it is possible to improve yield rates in the manufacture of semiconductor integrated circuits. | 05-28-2009 |
| 20090134496 | WAFER AND METHOD OF FORMING ALIGNMENT MARKERS - A wafer comprises a multi-layer structure. The multi-layer structure includes a first device structure neighbouring an area for receiving alignment markers. A plurality of alignment markers extend into the multi-layer structure and are located within the area for receiving alignment markers. The plurality of alignment markers is arranged to prevent propagation of a crack, when occurring, beyond a material-dependent critical length in a part of the multi-layer structure corresponding to the area for receiving the alignment structure. The material-dependent critical length is associated with the part of the multi-layer structure. | 05-28-2009 |
| 20090140391 | Seal Ring in Semiconductor Device - A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening. | 06-04-2009 |
| 20090140392 | WARPAGE RESISTANT SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes. | 06-04-2009 |
| 20090140393 | WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY - A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation. | 06-04-2009 |
| 20090146260 | Semiconductor wafer including cracking stopper structure and method of forming the same - A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators. The multi-level interconnections may extend in the device region. An electrode layer may be disposed over the stack of inter-layer insulators. The electrode layer may extend in the device region. The electrode layer may cover the multi-level interconnections. A cracking stopper groove may be disposed in the dicing region. The cracking stopper groove may be positioned outside the device region. | 06-11-2009 |
| 20090152683 | ROUNDED DIE CONFIGURATION FOR STRESS MINIMIZATION AND ENHANCED THERMO-MECHANICAL RELIABILITY - One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the invention, the sharpness of other corners and edges in the die are reduced. For example, reducing the sharpness of the bottom edge corners formed by the intersection of a sidewall and the back surface of a die can further diminish stress accumulations. One embodiment pertains to a wafer carried on a wafer support, where the wafer includes a multiplicity of such dice. Another embodiment involves a semiconductor package containing such dice. Methods of fabricating the dice are also described. | 06-18-2009 |
| 20090160029 | Scribe Seal Structure for Improved Noise Isolation - Disclosed is a semiconductor wafer with an array of integrated circuit chips with scribe lane structures forming edge and intra-chip seals for use in protecting the IC circuitry. Substantially parallel scribe seal structures extend around the periphery of each chip; the two scribe seal structures have a separation gap. Preferred embodiments of the invention also include wafers of ICs each having two or more distinctive circuitry blocks such as analog and digital circuitry, separated by an intra-chip seal. Preferred embodiments of also include ICs having two or more distinctive circuit blocks separated by a scribe seal structure with a separation gap and a routing channel for use in passing signals among the circuit blocks. | 06-25-2009 |
| 20090166810 | Semiconductor Device Crack-Deflecting Structure and Method - The invention relates to microelectronic semiconductor devices, and to mass-production of the same on semiconductor wafers with novel crack-deflecting structures and methods. According to the invention, a semiconductor device includes an active circuit area surrounded by an inactive area and circumscribed with a bulwark having a crack-deflecting face oriented toward the periphery of the device. Embodiments of the invention are disclosed, in which a semiconductor device, or multiple devices on a wafer, include bulwarks having series of minor arcs with their chords oriented toward the peripheries of the devices. Additional embodiments of the invention described include bulwarks having series of right angles oriented toward the peripheries of the devices. Examples of the invention also include preferred embodiments wherein the bulwarks further comprise series of discrete pickets, parallel bulwarks, and bulwarks in combination with scribe seals. | 07-02-2009 |
| 20090179304 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In the manufacture of semiconductor devices, cracking of a resin member caused during cutting and defects in the external appearance are prevented. | 07-16-2009 |
| 20090194850 | Crack Stops for Semiconductor Devices - Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions. | 08-06-2009 |
| 20090212399 | ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME - An electronic component includes a substrate, a functional element formed on the substrate, a plurality of terminals including a first terminal electrode connected to the functional element and a second terminal electrode layered on the first terminal electrode, and a feed line, one end of which is electrically connected to the first terminal electrode and the other end of which reaches an edge of the substrate, wherein the feed line includes a first portion directly reaching the edge, and a second portion branching from the first portion and then reaching the edge. | 08-27-2009 |
| 20090218660 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor substrate ( | 09-03-2009 |
| 20090250792 | Curing Low-k Dielectrics for Improving Mechanical Strength - An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer. | 10-08-2009 |
| 20090267193 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a circuit region on the semiconductor substrate, a plurality of metal wires formed in the circuit region on the semiconductor device and a seal ring region surrounding the circuit region. A distance L between an outer periphery of the circuit region and an inner periphery of the seal ring region and a minimum interval W | 10-29-2009 |
| 20090278236 | SEMICONDUCTOR DEVICE, WAFER STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A photo-resist used in photolithography in a microfabrication process may be formed uniformly even if trenches for separating semiconductor devices are formed before the microfabrication process. The two parallel trenches are formed between neighboring element forming regions in a p-type semiconductor layer containing a plurality of arrayed element forming regions and a convex portion formed between the two trenches is cut in separating the semiconductor devices. It becomes unnecessary to form a trench across a whole scribing region by this structure, so that a width of the trench may be reduced to be smaller than a thickness of a dicing blade or a diameter of a laser spot for example. As a result, it becomes possible to uniformly form the photo-resist used in the photolithography in the microfabrication process even if the trenches for separation are formed before the microfabrication process. | 11-12-2009 |
| 20090283869 | Scribe line structure for wafer dicing and method of making the same - The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer. | 11-19-2009 |
| 20090283870 | Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets - A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias. | 11-19-2009 |
| 20090294911 | Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets - A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die. | 12-03-2009 |
| 20090294912 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region. | 12-03-2009 |
| 20090294913 | Method for manufacturing semiconductor chip and semiconductor device - An improved yield of chips is realized by reducing the width of dicing streets on the front surface side of a semiconductor wafer. A method for semiconductor chip, divided a semiconductor wafer | 12-03-2009 |
| 20090302427 | Semiconductor Chip with Reinforcement Structure - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate wherein the semiconductor chip has a first side facing toward but separated from a second of the substrate to define an interface region. An array of electrical interconnects is provided between the semiconductor chip and the substrate positioned in the interface region. A reinforcement structure is coupled to the first side of the semiconductor chip and the second side of the substrate and in the interface region while outside the array of electrical interconnects. An underfill is provided in the interface region. | 12-10-2009 |
| 20090302428 | LASER BEAM MACHINING METHOD AND SEMICONDUCTOR CHIP - An object to be processed | 12-10-2009 |
| 20090321889 | Scribe Seal Connection - A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical impurities introduced during fabrication and assembly operations. A conductive structure penetrates the scribe seal, possibly in more than one location, connecting an interior region to an exterior region. A feedthrough vertical seal surrounds the conductive element in the IC and connects to the scribe seal. A horizontal diffusion barrier connects to the scribe seal and the feedthrough vertical seal. The feedthrough vertical seal, the horizontal diffusion barrier and the IC substrate form a continuous barrier to chemical impurities around the conductive element in the interior region. The conductive structure includes any combination of a doped region in an active area, an MOS transistor gate layer, and one or more interconnect metal layers. The feedthrough is compatible with aluminum and copper interconnect metallization. | 12-31-2009 |
| 20090321890 | Protective Seal Ring for Preventing Die-Saw Induced Stress - A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer. | 12-31-2009 |
| 20090321891 | METHOD AND APPARATUS FOR GENERATING RETICLE DATA - A method for generating reticle data for forming a reticle. The method includes recognizing a non-layout region free from main chips in a process pattern, dividing the non-layout region into a plurality of rectangular non-layout regions, generating scribe data using the plurality of divided rectangular non-layout region as a plurality of dummy chips, and generating a dummy pattern for each of the dummy chips. | 12-31-2009 |
| 20100001377 | Semiconductor device - A semiconductor device ( | 01-07-2010 |
| 20100013059 | DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES - The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench. | 01-21-2010 |
| 20100019353 | Semiconductor device and method for manufacturing the same - A semiconductor device and a method for manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films. | 01-28-2010 |
| 20100019354 | SEMICONDUCTOR CHIP SHAPE ALTERATION - The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners. | 01-28-2010 |
| 20100025824 | Structure for Reducing Integrated Circuit Corner Peeling - A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers. | 02-04-2010 |
| 20100032807 | Wafer level semiconductor module and method for manufacturing the same - A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas. | 02-11-2010 |
| 20100044838 | SEMICONDUCTOR COMPONENT WITH MARGINAL REGION - A semiconductor component having a semiconductor body includes an active region and a marginal region surrounding the active region. The marginal region extends from the active region as far as an edge of the semiconductor body. A zone composed of porous material is formed in the marginal region. | 02-25-2010 |
| 20100052106 | PACKAGE DEVICE HAVING CRACK ARREST FEATURE AND METHOD OF FORMING - A package device has a package substrate, a semiconductor die on the package substrate, and a molding compound on the package substrate and over the semiconductor die. The semiconductor die has a last passivation layer, an active circuit region in an internal portion of the die, an edge seal region along a periphery of the die, and a structure over the edge seal region extending above the last passivation layer, covered by the molding compound, and comprising a polymer material. The structure may extend at least five microns above the last passivation layer. The structure stops cracks in the molding compound from reaching the active circuit region. The cracks, if not stopped, can reach wire bonds in the active region and cause them to fail. | 03-04-2010 |
| 20100059864 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING ETCHING TO ETCH STOP REGIONS - A method of manufacturing a semiconductor device. The method includes providing a wafer having a first face and a second face opposite the first face, selectively doping the wafer via the first face to selectively form etch stop regions in the wafer and etching the wafer at the second face to the etch stop regions. | 03-11-2010 |
| 20100065947 | METHOD FOR EVALUATING IMPURITY DISTRIBUTION UNDER GATE ELECTRODE WITHOUT DAMAGING SILICON SUBSTRATE - A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. | 03-18-2010 |
| 20100072578 | Semiconductor chip and semiconductor wafer - A semiconductor chip which includes an element forming region formed over a substrate, a scribe line region which surrounds the element forming region, and a structure provided locally inside the scribe line region in at least one corner area of the semiconductor chip. The element forming region and the scribe line region include a plurality of interlayer dielectric films laminated over the substrate. The structure is constituted of corner pads sandwiching at least one of the interlayer dielectric films vertically in the direction of lamination, and vias interconnecting the corner pads. | 03-25-2010 |
| 20100078768 | Wafer cutting methods and packages using dice derived therefrom - A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection. | 04-01-2010 |
| 20100078769 | ENVIRONMENTAL DIE SEAL ENHANCEMENT FOR WAFER LEVEL CHIP SCALE PACKAGES - In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional circuit area that does not extend all the way into the corners of the rectangular die, and an outer scribe seal follows the perimeter of the die and into the corners, with the outer scribe seal having a continuous barrier wall towards the die edges so that moisture penetration in dielectric layers of the die is minimized, and cracks and delamination are stopped near the die edges. Limiting the extent of the insulating layer or layers in the WLCSP to cover the functional circuit area also reduces the stresses caused by these layers near the die corners. Other features further enhance the strength and barrier properties of the scribe seals and the layers near the die corners, terminate cracks and delamination at various levels within the dielectric stack of the die and the die protective overcoat, and prevent damage during the WLCSP assembly process. | 04-01-2010 |
| 20100090316 | WAFER WITH DESIGN PRINTED THEREIN - A printed wafer. A design is printed within a peripheral portion of the wafer. The peripheral portion of the wafer is between an outer boundary of an active portion of the wafer and an outer boundary of the wafer. The design may be a copy of a portion of a pattern that exists on a reticle of an exposure apparatus. The pattern may includes pattern elements such that adjacent pattern elements are separated by a spacing of about a sum of a first design tolerance (based on how accurately a reticle blind can be positioned within the exposure apparatus) and a second design tolerance (based on how sharply an edge of the reticle blind can be focused on the wafer by a lens). The design may visible to a naked eye unaided with no portion of the printed design within the active portion of the wafer. | 04-15-2010 |
| 20100096729 | GEOMETRY AND DESIGN FOR CONFORMAL ELECTRONICS - A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions. | 04-22-2010 |
| 20100096730 | PASSIVATION TECHNIQUE - A method of semiconductor wafer fabrication. The wafer is fabricated by receiving a semiconductor wafer having a substrate layer and at least one processed layer, cutting a trench into the wafer, wherein the trench penetrates through the at least one processed layer and only partially through the thickness of the substrate layer, and depositing a passivation layer over the at least one processed layer such that the trench is filled with the passivation material. | 04-22-2010 |
| 20100096731 | Semiconductor Device and Method of Forming Stepped-Down RDL and Recessed THV in Peripheral Region of the Device - A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer. | 04-22-2010 |
| 20100096732 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Interconnections are formed over an interlayer insulating film which covers MISFETQ | 04-22-2010 |
| 20100109128 | Crack Deflector Structure for Improving Semiconductor Device Robustness Against Saw-Induced Damage - An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal. | 05-06-2010 |
| 20100123219 | Heat Spreader Structures in Scribe Lines - An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge. | 05-20-2010 |
| 20100127355 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and method. One embodiment provides a semiconductor substrate having a plurality of cut regions. A metal layer is located within a cut region. The metal layer includes a recess, the recess having a slit-like shape. | 05-27-2010 |
| 20100127356 | STRUCTURES AND METHODS FOR REDUCING JUNCTION LEAKAGE IN SEMICONDUCTOR DEVICES - Structures and method for reducing junction leakage in semiconductor devices. The die can include a substrate having a cut edge, a first region of first conductivity type within the substrate and a region of a second conductivity type within the substrate and in contact with the first region forming a junction. At least one semiconductor device is on the substrate. A second region of the first conductivity type is between the plurality of semiconductor devices and the cut edge within the region of the second conductivity type, and extending to the junction. The second region of the first conductivity type can isolate the at least one semiconductor device from leakage pathways created by saw damage at the junction along the cut edge. | 05-27-2010 |
| 20100127357 | SEMICONDUCTOR DEVICE - A semiconductor device includes a seal ring formed on an outer circumference of an element forming region when seen from the top in a multilayer interconnect structure formed on a silicon layer, and dummy metal structures formed on a further outer circumference of the seal ring. The more inner circumference side the dummy interconnect is formed on, the more upper layer the dummy interconnect is arranged on. | 05-27-2010 |
| 20100140747 | Semiconductor devices - In a method of manufacturing a semiconductor device, a pad including at least one insulating interlayer and at least one conductive wiring may be formed in a pad area of a substrate. At least one wiring may be formed adjacent to the conductive wiring. At least one insulation layer may be formed adjacent to the insulating interlayer. At least one crack preventing structure may be formed in the insulation layer. The crack preventing structure may continuously extend in the insulation layer and portions of the insulation layer may also be continuous. When a semiconductor device includes at least one crack preventing structure disposed adjacent to a pad, a degradation of the semiconductor chip caused by an external impact and/or a stress may be efficiently prevented by the crack preventing structure. | 06-10-2010 |
| 20100140748 | INTEGRATED CIRCUITS ON A WAFER AND METHODS FOR MANUFACTURING INTEGRATED CIRCUITS - Integrated circuits ( | 06-10-2010 |
| 20100148313 | SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor apparatus, wherein a technique for manufacturing one semiconductor region by dividing the one semiconductor region into a plurality of divisional regions in regard of a step is applied, and one-side device portions formed simultaneously by a one-side treatment conducted primarily for the divisional region on one side and other-side device portions formed simultaneously by an other-side treatment conducted primarily for the divisional region on the other side are mixedly present in a joint region joining a boundary between the divisional regions. | 06-17-2010 |
| 20100148314 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACURING THE SAME - The present invention provides a semiconductor device and a method for manufacturing the same capable of inhibiting plasma damage. A semiconductor device according to one embodiment includes a protective pattern grounded to a semiconductor substrate in a scribe line area, on a wafer including a main chip area and the scribe line area formed around the main chip area. Plasma arching defects to a wafer can be reduced by forming a plasma arching protective pattern in a scribe line region and effectively using the scribe line region in an unused region of the wafer. | 06-17-2010 |
| 20100148315 | SEMICONDUCTOR WAFER AND A METHOD OF SEPARATING THE SAME - A semiconductor wafer includes a plurality of predetermined separation lines extending from an upper surface to a bottom surface; and a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines. Tensile stress is applied to regions of the semiconductor substrate provided with the predetermined separation lines. | 06-17-2010 |
| 20100176493 | METHOD OF SPLITTING A SUBSTRATE - A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate while the substrate is held in place on a portion of its periphery during the implanting; and splitting the substrate along the weakened zone by placing the held portion of the substrate in a splitting-wave initiation sector while positioning the notch for initiating a splitting wave followed by the propagation of the wave into the substrate. During splitting the notch is positioned so that it is in a quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate that is centered on the sector. | 07-15-2010 |
| 20100181650 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - With a general wafer level package process, in order to prevent corrosion of an aluminum type pad electrode in a scribe region in a plating process, the pad electrode is covered with a pad protective resin film at the same layer as an organic type protective film in a product region. However, this makes it impossible to perform the probe test on the pad electrode in the scribe region after rewiring formation. The present invention provides a method for manufacturing a semiconductor integrated circuit device of a wafer level package system. The organic type protective films in the chip regions and the scribe region are mutually combined to form an integral film pattern. In a pelletization step, the surface layer portion including the organic type protective film at the central part of the scribe region is first removed by laser grooving, to form a large-width groove. Then, a dicing processing of the central part in this groove results in separation into the chip regions. | 07-22-2010 |
| 20100193918 | EMBEDDED SCRIBE LANE CRACK ARREST STRUCTURE FOR IMPROVED IC PACKAGE RELIABILITY OF PLASTIC FLIP CHIP DEVICES - A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape, with the die separated by a plurality of scribe lanes. An existing die seal generally protects the boundary of the die but can still fail to fully protect the die from excessive cracks induced by dicing damage, particularly when dicing through brittle, low-k dielectrics. The system, method, and apparatus includes embedding a crack arrest structure (CAS) between adjacent scribe lanes. Upon a mechanical saw dicing the wafer, the CAS creates a moisture diffusion block, and can absorb or significantly diminish the energy of cracks propagating towards the individual die seals. Furthermore, the system, method, and apparatus can be implemented without the need to increase the width of the scribe lanes. | 08-05-2010 |
| 20100200959 | SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE, SEMICONDUCTOR PLATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: insulating layers formed in the plurality of groove portions; a rectangular unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode including an extended terminal portion extended from the unit region to the inside of the groove portion. The semiconductor substrate is manufactured by forming a plurality of groove portions along scribe lines; embedding an insulating material in the plurality of groove portions and planarizing a surface to form insulating layers; and forming a wiring electrode including an extended terminal portion extended from a rectangular unit region in contact with at least any one of the plurality of groove portions to the inside of the groove portion. | 08-12-2010 |
| 20100200960 | DEEP TRENCH CRACKSTOPS UNDER CONTACTS - Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns. | 08-12-2010 |
| 20100207250 | Semiconductor Chip with Protective Scribe Structure - Apparatus and methods pertaining to die scribe structures are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating an active region of a semiconductor die so that the active region has at least one corner. A scribe structure is fabricated around the active region so that the scribe structure includes at least one fillet. | 08-19-2010 |
| 20100207251 | Scribe Line Metal Structure - A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers. | 08-19-2010 |
| 20100207252 | Manufacturing method of semiconductor device - An adhesive layer of which thickness is over 25 Ī¼m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board. | 08-19-2010 |
| 20100230788 | CHIP STRUCTURE, WAFER STRUCTURE AND PROCESS OF FAABRICATING CHIP - A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate. | 09-16-2010 |
| 20100244200 | Integrated circuit connecting structure having flexible layout - A wafer has a cutting part filled with a connecting medium. After the wafer is cut into chips along the cutting part, two contacts on two surfaces of the chip can be connected through corresponding leading wires and the connecting medium. Thus, the chip can have a flexible layout. | 09-30-2010 |
| 20100252916 | STRUCTURE FOR IMPROVING DIE SAW QUALITY - A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6. | 10-07-2010 |
| 20100258916 | THERMAL STRESS REDUCTION - The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 Ī¼m, preferably from 5-40 Ī¼m, like 20 Ī¼m. | 10-14-2010 |
| 20100270655 | Integrated Circuits On A Wafer and Method For Separating Integrated Circuits On A Wafer - Integrated circuits ( | 10-28-2010 |
| 20100270656 | Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar. | 10-28-2010 |
| 20100283127 | METHOD FOR PACKING SEMICONDUCTOR COMPONENTS AND PRODUCT PRODUCED ACCORDING TO THE METHOD - A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed. | 11-11-2010 |
| 20100283128 | Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof - Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street. | 11-11-2010 |
| 20100283129 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An upper surface of a semiconductor substrate includes a first portion where a dielectric film is provided, and a second portion where the dielectric film is not provided, wherein the second portion is located in the periphery of the first portion. The upper surface of the semiconductor substrate is covered with a sealing resin. | 11-11-2010 |
| 20100301459 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - The warpage of a semiconductor wafer or a semiconductor chip is inhibited. A method includes a step of successively forming, pads formed over the main surface of the semiconductor chip, an insulation layer formed by covering the main surface such that the pads are exposed, an insulation film formed over the insulation layer such that the pads are exposed, rewirings formed over the insulation film and electrically coupled with the pads, respectively, an insulation film formed over each rewirings such that portions of the rewirings are exposed, and bumps respectively bonded with the regions of the rewirings exposed from the insulation film. Any one of the insulation film and the insulation layer is formed such that a portion of an insulation layer or the insulation film formed closer to the back surface side than the insulation film or the insulation layer is exposed. | 12-02-2010 |
| 20100308442 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF THE SAME - In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line. | 12-09-2010 |
| 20110006403 | SEMICONDUCTOR DEVICE AND THE METHOD FOR MANUFACTURING THE SAME - A semiconductor device is disclosed which includes active section | 01-13-2011 |
| 20110006404 | STRUCTURE AND METHOD OF WAFER LEVEL CHIP MOLDED PACKAGING - A wafer is provided having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies are provided, each of the dies is bonded to one of the plurality of semiconductor chips. One or more trenches are formed on the chip side of the wafer. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material, the protecting material substantially filling the one or more trenches. The wafer is diced to separate it into individual semiconductor packages. | 01-13-2011 |
| 20110024882 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region. | 02-03-2011 |
| 20110037148 | PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE - An integrated circuit apparatus is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires. | 02-17-2011 |
| 20110037149 | METHOD OF CUTTING A WAFER-LIKE OBJECT AND SEMICONDUCTOR CHIP - A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed. | 02-17-2011 |
| 20110057297 | SEMICONDUCTOR CHIPS HAVING GUARD RINGS AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer. | 03-10-2011 |
| 20110068435 | Semiconductor Chip with Crack Deflection Structure - Various die crack deflection structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a semiconductor chip including an outer edge, a first side and a second side opposite to the first side. A deflection structure is fabricated in the semiconductor chip. The deflection structure includes a sloped profile to deflect a crack propagating in the semiconductor chip toward the first side or the second side of the semiconductor chip. | 03-24-2011 |
| 20110068436 | METHODS AND STRUCTURES FOR ENHANCING PERIMETER-TO-SURFACE AREA HOMOGENEITY - Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions. | 03-24-2011 |
| 20110073996 | MULTIPLE DIE LAYOUT FOR FACILITATING THE COMBINING OF AN INDIVIDUAL DIE INTO A SINGLE DIE - A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die. | 03-31-2011 |
| 20110084364 | WAFER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a wafer, a first chip region and a second chip region are separated from each other by a dicing region. The dicing region includes: a first center region; a first intermediate region located on the first chip region's side of the first center region; a second intermediate region located on the second chip region's side of the first center region; a first outer region located on the first chip region's side of the first intermediate region; and a second outer region located on the second chip region's side of the second intermediate region. Surfaces of the first and second intermediate regions are respectively covered by bank-shaped resin films extending in a longitudinal direction of the dicing region. Respective surfaces of the first center region, the first outer region and the second outer region are not covered by resin films. | 04-14-2011 |
| 20110089539 | PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS - Methods for forming electrically conductive through-wafer interconnects in microelectronic devices and microelectronic devices are disclosed herein. In one embodiment, a microelectronic device can include a monolithic microelectronic substrate with an integrated circuit has a front side with integrated circuit interconnects thereon. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad. | 04-21-2011 |
| 20110101505 | Semiconductor Die Separation Method - According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out. | 05-05-2011 |
| 20110108957 | Semiconductor substrate, semiconductor device and method of manufacturing the same - A semiconductor substrate ( | 05-12-2011 |
| 20110115057 | DESIGN STRUCTURE FOR INTEGRATED CIRCUIT ALIGNMENT - A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region. | 05-19-2011 |
| 20110115058 | DEVICES WITH CRACK STOPS - An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device. | 05-19-2011 |
| 20110121432 | Semiconductor Device and Method of Forming Holes In Substrate to Interconnect Top Shield and Ground Shield - A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die. | 05-26-2011 |
| 20110127644 | WAFER AND METHOD FOR FORMING THE SAME - A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe region configured to be formed among the plurality of chips so as to separate each chip, and an alignment key pattern configured to be arranged on the plurality of chips. | 06-02-2011 |
| 20110127645 | WAFER AND METHOD FOR FORMING THE SAME - A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe line configured to be formed among the plurality of chips so as to separate each chip, and an align key line configured to be formed in one side of the wafer so as to form an align key pattern. | 06-02-2011 |
| 20110127646 | WAFER AND METHOD FOR FORMING THE SAME - A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe lane formed among the plurality of chips, configured to separate each of the plurality of chips using a Deep Reactive Ion Etching (DRIE) process, and an alignment key pattern configured to be arranged on the plurality of chips. The DRIE process is performed at a front side of the wafer on a basis of the align key pattern. | 06-02-2011 |
| 20110127647 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - A semiconductor device includes a semiconductor substrate having a main surface in which a semiconductor element region where a plurality of functional elements are formed is formed; a multilevel wiring layer disposed on the main surface of the semiconductor substrate; a first organic insulating material layer disposed on the multilevel wiring layer; a groove that penetrates the multilevel wiring layer on a scribe region that surrounds the semiconductor element region; and an organic insulating material that is spaced from the first organic insulating material layer and disposed in the groove. | 06-02-2011 |
| 20110127648 | Heat Spreader Structures in Scribe Lines - An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge. | 06-02-2011 |
| 20110140245 | STRUCTURE FOR INHIBITING BACK END OF LINE DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES - A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT. | 06-16-2011 |
| 20110147897 | OFFSET FIELD GRID FOR EFFICIENT WAFER LAYOUT - Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines. | 06-23-2011 |
| 20110147898 | METHOD FOR DICING A SEMICONDUCTOR WAFER, A CHIP DICED FROM A SEMICONDUCTOR WAFER, AND AN ARRAY OF CHIPS DICED FROM A SEMICONDUCTOR WAFER - A method for dicing a semiconductor wafer, including: cutting a reference slot in a back main surface of the wafer; cutting a back slot in the back main surface, the back slot positioned with respect to the reference slot; determining a desired location for a chip edge with respect to the reference slot; and applying radiant energy in a path such that a series of reformed regions are formed within the wafer along the path. A crystalline structure of the wafer is modified in the series of reformed regions and an alignment of an edge of the laser is with respect to the desired location for the chip edge and in alignment with the back slot. The method includes separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions. | 06-23-2011 |
| 20110156217 | POWER DEVICES HAVING REDUCED ON-RESISTANCE AND METHODS OF THEIR MANUFACTURE - A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging. | 06-30-2011 |
| 20110156218 | CHIP PACKAGE - A chip package is provided. The chip package includes a chip, having a plurality of conductive pads disposed along a periphery of the chip, wherein the conductive pads have a width. A seal ring includes a plurality of metal strips disposed within a space between the two adjacent conductive pads. Each metal strip is electrically connected to at most one of the two adjacent conductive pads. | 06-30-2011 |
| 20110156219 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed which can prevent interlayer cracking of interlayer dielectric films while improving the adhesion between the interlayer dielectric films in a dicing process using a dicing blade. In a scribing line area, dummy wirings are formed respectively in a blade area through which a dicing blade passes in a dicing process and in non-blade areas formed on both sides of the blade area and through which the dicing blade does not pass. In the non-blade areas, vertically adjacent dummy wirings are coupled together through dummy vias, while in the blade area the vertically adjacent dummy wirings are not coupled together through dummy vias. | 06-30-2011 |
| 20110156220 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiringdisposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same. | 06-30-2011 |
| 20110186967 | Component Stacking Using Pre-Formed Adhesive Films - A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film. | 08-04-2011 |
| 20110198731 | Apparatus and Method for Defining Laser Cleave Alignment - An apparatus includes a crystalline substrate. A cleaving guide on the substrate is positioned over a cleave plane of the crystalline substrate and positioned in a known location with respect to a feature of an electronic device on the substrate. Cleaving of the substrate along the cleave plane changes a physical characteristic of the cleaving guide and measurement of the physical characteristic provides a parameter representative of the relative position of the cleave plane and the cleaving guide. | 08-18-2011 |
| 20110221041 | Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die - A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. | 09-15-2011 |
| 20110221042 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A wafer structure ( | 09-15-2011 |
| 20110221043 | Semiconductor device and manufacturing method therefor - Provided is a semiconductor device suitable for preventing film peeling due to dicing and preventing abnormal discharge. The semiconductor device includes a scribe region ( | 09-15-2011 |
| 20110233735 | SEMICONDUCTOR WAFER AND ITS MANUFACTURE METHOD, AND SEMICONDUCTOR CHIP - A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer. | 09-29-2011 |
| 20110241177 | Semiconductor wafer including cracking stopper structure and method of forming the same - A semiconductor includes a semiconductor substrate having a main face, the semiconductor device having a device region and a dicing line and a stack of insulating layers over the semiconductor substrate. There is a multi-level interconnection structure in the stack of insulating layers. A passivation film covers the semiconductor substrate, the passivation film having an opening. The stack of insulating layers has a groove which extends from the opening and penetrates at least one of the insulating layers, the groove is positioned between the device region and the dicing line, and the groove is narrower in width than the opening. | 10-06-2011 |
| 20110241178 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic protective film | 10-06-2011 |
| 20110241179 | DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES - The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench. | 10-06-2011 |
| 20110248387 | SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME - A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion. | 10-13-2011 |
| 20110254136 | SEMICONDUCTOR DEVICE - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. | 10-20-2011 |
| 20110266656 | Semiconductor Device and Method of Forming Protective Coating Material Over Semiconductor Wafer to Reduce Lamination Tape Residue - A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer. | 11-03-2011 |
| 20110266657 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region. | 11-03-2011 |
| 20110272790 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR WAFER - A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region. | 11-10-2011 |
| 20110278701 | Scribe line structure for wafer dicing - The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer. | 11-17-2011 |
| 20110298095 | PASSIVATION LAYER EXTENSION TO CHIP EDGE - Embodiments of the invention provide a semiconductor chip having a passivation layer extending along a surface of a semiconductor substrate to an edge of the semiconductor substrate, and methods for their formation. One aspect of the invention provides a semiconductor chip comprising: a semiconductor substrate; a passivation layer including a photosensitive polyimide disposed along a surface of the semiconductor substrate and extending to at least one edge of the semiconductor substrate; and a channel extending through the passivation layer to the surface of the semiconductor substrate. | 12-08-2011 |
| 20110298096 | Semiconductor chip - A semiconductor wafer | 12-08-2011 |
| 20110304024 | VERTICAL CONDUCTIVE CONNECTIONS IN SEMICONDUCTOR SUBSTRATES - An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area. | 12-15-2011 |
| 20110304025 | NITRIDE COMPOUND SEMICONDUCTOR ELEMENT AND PRODUCTION METHOD THEREFOR - A nitride compound semiconductor element according to the present invention is a nitride compound semiconductor element including a substrate | 12-15-2011 |
| 20110316123 | Laminated semiconductor substrate, laminated chip package and method of manufacturing the same - In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions. | 12-29-2011 |
| 20120025354 | LAMINATED SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region. | 02-02-2012 |
| 20120025355 | LAMINATED SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have electromagnetic shielding layer formed in regions other than the scribe-groove parts using a ferromagnetic body. Further, in the laminated semiconductor substrate, a through hole which penetrates the plurality of semiconductor substrates laminated in a laminated direction is formed in the scribe-groove part, and the laminated semiconductor substrate has a through electrode penetrating the plurality of semiconductor substrates through the through hole. | 02-02-2012 |
| 20120038028 | MULTIPLE SEAL RING STRUCTURE - The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures. A semiconductor device fabricated by such a method is also provided. | 02-16-2012 |
| 20120056309 | SEMICONDUCTOR DEVICE WITH REDUCED HEAT-INDUCED LOSS - A semiconductor device which is capable of reducing a heat-induced loss includes a substrate and a circuit element disposed on the substrate. The substrate is of a rectangular shape with beveled surfaces on four corners thereof. | 03-08-2012 |
| 20120056310 | SEMICONDUCTOR DEVICE AND METHOD FOR INCREASING SEMICONDUCTOR DEVICE EFFECTIVE OPERATION AERA - A method for increasing semiconductor device effective operation area, comprising following steps: depositing first conductive layer on the substrate; using laser for scribing a plurality of the first scribe lines on the first conductive layer, where the scribe lines are scribed on the bottom of the first conductive layer; depositing a plurality of the semiconductor material layers on the first conductive layer and in the plurality of the first scribe lines; using laser for scribing a plurality of the second scribe lines on the semiconductor material layer, where the scribe lines are scribed on the bottom of the semiconductor material layer, each second scribe line is comprised of a plurality of the second pores; depositing a second conductive layer on the semiconductor material layer and in the plurality of the first scribe lines and the plurality of the second scribe lines; using laser for scribing a plurality of the third scribe lines on the second conductive layer, where the scribe lines are scribed on the bottom of the semiconductor material layer; wherein the second pores are shortened for shortening the distance between the first scribe line and second scribe line and the distance between the third scribe line and second scribe line. | 03-08-2012 |
| 20120068312 | ADHESIVE SHEET AND METHOD FOR MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - An adhesive sheet comprising a release substrate | 03-22-2012 |
| 20120091565 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 04-19-2012 |
| 20120098104 | SHIELDING TECHNIQUES FOR AN INTEGRATED CIRCUIT - Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches. | 04-26-2012 |
| 20120098105 | BOND PAD FOR WAFER AND PACKAGE FOR CMOS IMAGER - An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads. | 04-26-2012 |
| 20120119333 | PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP - Product chips and die that include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging. | 05-17-2012 |
| 20120119334 | LASER MACHINING METHOD AND CHIP - While reliably cutting an object to be processed, the strength of the resulting chips is improved. An object to be processed | 05-17-2012 |
| 20120161294 | Method of Batch Trimming Circuit Elements - Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit. | 06-28-2012 |
| 20120181669 | FRAME CELL FOR SHOT LAYOUT FLEXIBILITY - A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout. | 07-19-2012 |
| 20120181670 | SEMICONDUCTOR DEVICE HAVING SEAL WIRING - A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening. | 07-19-2012 |
| 20120181671 | METHOD FOR EVALUATING IMPURITY DISTRIBUTION UNDER GATE ELECTRODE WITHOUT DAMAGING SILICON SUBSTRATE - A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on a gate insulating film in a monitor region of the semiconductor substrate, a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. The gate electrode is removed without removing a gate insulating film by applying pyrolysis hydrogen generated by pyrolysis on the monitor semiconductor device in the monitor region, and the gate insulating film is removed by a wet process. Impurities distribution of a silicon active region appearing after the gate electrode is removed is measured and fed back to a semiconductor manufacturing process. | 07-19-2012 |
| 20120187544 | SEMICONDUCTOR APPARATUS HAVING PENETRATION ELECTRODE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, in a semiconductor apparatus, a semiconductor substrate has a first surface and a second surface opposite to the first surface. A semiconductor device is formed in a rectangular region enclosed by a plurality of dicing lines of the semiconductor substrate. The semiconductor device includes a first electrode provided on the first surface and a second electrode provided on the second surface so as to pass a current between the first electrode and the second electrode. A penetration electrode is formed in a region not enclosed by the dicing lines of the semiconductor substrate. One end of the penetration electrode extends on the first surface. The other end of the penetration electrode is electrically connected to the second electrode. | 07-26-2012 |
| 20120228744 | WAFER AND METHOD OF MANUFACTURING PACKAGE PRODUCT - To provide a wafer in which out-gas emitted between wafers during bonding of the wafers can be easily discharged to the outside and the bonded wafers can be favorably cut to improve the yields, and a method of manufacturing a package product using the wafer. A groove portion is formed in a wafer for lid substrate along a plurality of imaginary straight lines passing through a center in a diameter direction of the wafer for lid substrate and extending in the diameter direction. The groove portion is divided into a plurality of groove portions in the diameter direction placed such that the groove portions are not in contact with each other. | 09-13-2012 |
| 20120235284 | FILM-LIKE WAFER MOLD MATERIAL, MOLDED WAFER, AND SEMICONDUCTOR DEVICE - A film-like wafer mold material for molding a wafer in a lump, the material including a multilayer structure constituted of at least a first film layer and a second film layer provided on the first film layer, wherein the first film layer contains a silicone-backbone-containing polymer, a cross-linking agent, and a filler, and the second film layer, contains a silicone-backbone-containing polymer and a cross-linking agent, and further contains a filler in such a manner that a content rate of the filler becomes 0 or above and less than 100 when a content rate of the filler contained in the first film layer is assumed to be 100. The film-like wafer mold material has excellent transference performance with respect to a thin-film wafer with a large diameter, also has low-warp properties and excellent wafer protection performance after form shaping (after molding), and is preferably used for a wafer level package. | 09-20-2012 |
| 20120241914 | REDUCTION OF FLUORINE CONTAMINATION OF BOND PADS OF SEMICONDUCTOR DEVICES - A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications. | 09-27-2012 |
| 20120267765 | WAFER-LEVELED CHIP PACKAGING STRUCTURE AND METHOD THEREOF - A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias. | 10-25-2012 |
| 20120286397 | Die Seal for Integrated Circuit Device - Disclosed herein is a semiconductor device having a novel stress reduction structures that are employed in an effort to eliminate or at least reduce undesirable cracking or chipping of semiconductor die. In one example, the device includes a die comprising a semiconducting substrate, wherein the die includes a cut surface. The device also includes a first die seal that defines a perimeter, and at least one stress reducing structure, at least a portion of which is positioned between the perimeter defined by the first die seal and the cut surface, wherein the cut surface exposes at least a portion of the stress reducing structure. | 11-15-2012 |
| 20120286398 | SEMICONDUCTOR CHIP MODULE AND PLANAR STACK PACKAGE HAVING THE SAME - A semiconductor chip module includes a chip unit including at least two semiconductor chips disposed with a scribe lane interposed therebetween and each of which has a first surface on which bonding pads are disposed and a second surface that faces away from the first surface. Redistribution lines formed on the first surface of each semiconductor chip have first ends, which are connected with the bonding pads of each semiconductor chip, and second ends that extend to and are disposed on the scribe lane. Through electrodes formed to pass through the scribe lane are electrically connected with the second ends of the redistribution lines. | 11-15-2012 |
| 20120286399 | LEADFRAME AND METHOD FOR PACKAGING SEMICONDUCTOR DIE - In one embodiment, a method is provided for packaging a semiconductor die. A leadframe having a die-pad and one or more lead-pads is placed ( | 11-15-2012 |
| 20120292744 | CHIP PACKAGE, METHOD FOR FORMING THE SAME, AND PACKAGE WAFER - An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer. | 11-22-2012 |
| 20120299159 | STRUCTURE DESIGNS AND METHODS FOR INTEGRATED CIRCUIT ALIGNMENT - Devices and methods for pattern alignment are disclosed. In one embodiment, a semiconductor device includes a die including an integrated circuit region, an assembly isolation region around the integrated circuit region, and a seal ring region around the assembly isolation region. The device further includes a die alignment mark disposed within the seal ring region or the assembly isolation region. | 11-29-2012 |
| 20120306056 | Semiconductor wafer and method of producing the same - A semiconductor wafer ( | 12-06-2012 |
| 20120313222 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure. | 12-13-2012 |
| 20120313223 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITHOUT GROUND CONTACT PAD - The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package. | 12-13-2012 |
| 20120326280 | LAMINATED FILM AND USE THEREOF - Provided is a laminated film wherein the space between semiconductor elements that are three-dimensionally mounted can be filled easily and securely. The laminated film of the present invention is a laminated film for filling the space between semiconductor elements that are electrically connected through a member or connection, the film including a dicing sheet in which a pressure-sensitive adhesive layer is laminated on a base material and a curable film that is laminated on the pressure-sensitive adhesive layer, wherein the curable film has a lowest melt viscosity at 50 to 200Ā° C. of 1Ć10 | 12-27-2012 |
| 20130009284 | SUBSTRATE DIVIDING METHOD - A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate | 01-10-2013 |
| 20130009285 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR WAFER - A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region. | 01-10-2013 |
| 20130026605 | WLCSP for Small, High Volume Die - The disclosed WLCSP solution overcomes the limitations of fan-out WLCSP solutions, and other conventional solutions for WLCSP for small, high volume die, by increasing the width of scribe regions between die on a semiconductor substrate to accommodate bonding structures (e.g., solder balls) that partially extend beyond peripheral edges of the die. The scribe regions can be widened in x and y directions on the wafer. The widened scribe regions can be incorporated into the design of the mask set. | 01-31-2013 |
| 20130037916 | BREAK PATTERN OF SILICON WAFER, SILICON WAFER, AND SILICON SUBSTRATE - A break pattern of a silicon wafer includes a line to be cut which is set in the silicon wafer assuming a surface as a (110) face in a surface direction of a first (111) face perpendicular to the (110) face; and through holes which are provided in a plurality of rows on the line to be cut, wherein each of the through holes has a first (111) face, a second (111) face which intersects the first (111) face, and a third (111) face which intersects the second (111) face and the first (111) face, an intersecting point with end edges of the second (111) face and the third (111) face is assumed as a point closest to the adjacent through holes. | 02-14-2013 |
| 20130043566 | SEMICONDUCTOR DEVICE AND FLIP-CHIP PACKAGE - A semiconductor device includes a substrate having a circuit formation region, an interlayer insulating film formed on the substrate, a first seal ring formed in the interlayer insulating film to surround the circuit formation region, a first protective film formed on the interlayer insulating film in the circuit formation region and on the first seal ring, and a second protective film formed on the first protective film and inside relative to the first seal ring. The first protective film has a first surface contacting the second protective film, a second surface located directly on the first seal ring, and a third surface connecting the first surface and the second surface together, and an end of the second protective film is located inside relative to the third surface. | 02-21-2013 |
| 20130069205 | SEMICONDUCTOR WAFER AND PROCESSING METHOD THEREFOR - A semiconductor wafer and a method which are capable of reducing chippings or cracks generated during the die sawing process. The semiconductor wafer comprises a plurality of dies formed on the semiconductor wafer in row and column directions and separated from each other by scribe lane areas, and a passivation layer formed on the plurality of dies and the scribe lane areas, wherein a groove structure is formed in the passivation layer. The groove structure includes grooves formed along the scribe lane areas, and corners of the passivation layer at intersections of the grooves being removed. | 03-21-2013 |
| 20130069206 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view. | 03-21-2013 |
| 20130075869 | Chip Comprising a Fill Structure - A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge. | 03-28-2013 |
| 20130087891 | SEMICONDUCTOR CHIP AND FABRICATING METHOD THEREOF - Disclosed is a method of fabricating a semiconductor chip. The method includes forming a silicon layer; forming a first layer formed on the silicon layer and including a first seal ring surrounding a first chip area and a second seal ring surrounding a second chip area; and forming a second layer formed on the first layer and including a metal interconnection connecting one of the first and second chip areas and an external terminal. | 04-11-2013 |
| 20130105949 | LAMINATED SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME | 05-02-2013 |
| 20130113083 | RESIN COMPOSITION, RESIN FILM, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREOF - A resin composition which can be formed into a film for use in molding a large diameter thin film wafer is provided. The composition comprises components (A) a silicone resin containing repeating units represented by the following formulae (1-1), (1-2), and (1-3) and having a weight average molecular weight as measured by GPC in terms of polystyrene of 3,000 to 500,000, | 05-09-2013 |
| 20130119520 | CHIPS WITH HIGH FRACTURE TOUGHNESS THROUGH A METAL RING - A microelectronic element is disclosed that includes a semiconductor chip and a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces of the semiconductor chip and extending onto the front surface. The semiconductor chip may have front and rear opposed surfaces and a plurality of contacts at the front surface and edge surfaces extending between the front and rear surfaces. The semiconductor chip may also embody at least an active device or a passive device. | 05-16-2013 |
| 20130127018 | Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure - A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer. | 05-23-2013 |
| 20130134559 | Chip-on-Wafer Structures and Methods for Forming the Same - A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level. | 05-30-2013 |
| 20130147018 | Structure for Reducing Integrated Circuit Corner Peeling - A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers. | 06-13-2013 |
| 20130147019 | Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die - A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. | 06-13-2013 |
| 20130154062 | Die Structure and Method of Fabrication Thereof - A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate. | 06-20-2013 |
| 20130161795 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, PROCESSING METHOD OF SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER - A disclosed method of manufacturing a semiconductor device includes forming a groove on a first surface of a semiconductor wafer along an outer periphery of the semiconductor wafer, forming a semiconductor device on the first surface, forming an adhesive layer on the first surface to cover the semiconductor device, bonding a support substrate to the first surface by the adhesive layer, grinding after the adhering of the support substrate a second surface of the semiconductor wafer opposite to the first surface, and dicing after the grinding the semiconductor wafer into individual semiconductor chips. | 06-27-2013 |
| 20130168830 | SEMICONDUCTOR WAFER PLATING BUS - A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal. | 07-04-2013 |
| 20130168831 | LASER BEAM MACHINING METHOD AND SEMICONDUCTOR CHIP - An object to be processed | 07-04-2013 |
| 20130181329 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film. | 07-18-2013 |
| 20130207239 | Interconnect Crack Arrestor Structure and Methods - A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers. | 08-15-2013 |
| 20130207240 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure. | 08-15-2013 |
| 20130214388 | Semiconductor Wafer Adapted to Support Transparency in Partial Wafer Processing - A semiconductor wafer is adapted to support partial wafer processing generally transparently to a facility capable of processing a full wafer. The wafer has provided thereon a plurality of semiconductor dice and a plurality of visible reference features. The reference features are positioned among the dice to support a predetermined partitioning of the wafer into partial wafers. The positioning of the reference features may render each partial wafer uniquely visually distinguishable from every other partial wafer. Each partial wafer may contain at least one of the reference features, with the position of each reference feature identified in accordance with a coordinate system of an electronic wafer map. The positioning of the reference features may provide a visual indication of where to cut the wafer to effect the partitioning. | 08-22-2013 |
| 20130221493 | SEMICONDUCTOR PACKAGE - Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end. | 08-29-2013 |
| 20130249061 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND SUBSTRATE - According to an embodiment, a semiconductor device includes a substrate provided with a first region including an active element, the substrate including a second region containing boron with a density of 2Ć10 | 09-26-2013 |
| 20130256839 | SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE - A semiconductor wafer may include: a disk-shaped wafer body made of silicon; and an identification trench section having at least one trench and provided at a periphery section of the wafer body, wherein the trench is opened in the periphery of the wafer body, and has a depth less than a thickness of the wafer body. | 10-03-2013 |
| 20130256840 | Semiconductor Device and Method of Forming Protective Coating Material Over Semiconductor Wafer to Reduce Lamination Tape Residue - A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer. | 10-03-2013 |
| 20130277806 | LASER SUBMOUNTS FORMED USING ETCHING PROCESS - A wafer is formed having a plurality of laser-to-slider submount features on a first surface. An etching process is used to form scribe lines between the submounts on the first surface of the wafer. The wafer is separated at the scribe lines to form the submounts. | 10-24-2013 |
| 20130292803 | CHIP STRUCTURE AND WAFER STRUCTURE - A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate. | 11-07-2013 |
| 20130299947 | PASSIVATED TEST STRUCTURES TO ENABLE SAW SINGULATION OF WAFER - A wafer having a die area and a scribe street is formed. The die area comprises die circuitry and a plurality of bond pads, and the scribe street comprises a test structure. Circuitry of the test structure is probed, and then a passivation layer overlying the surface of the wafer is formed, the passivation layer overlying the plurality of bond pads and overlying the test structure. Openings in the regions of the passivation layer overlying the plurality of bond pads are then formed to expose the plurality of bond pads while retaining the regions of the passivation layer overlying the test structure until singulation of the wafer. Pad metallizations are formed at the plurality of bond pads via the openings in the regions of the passivation layer and the wafer is singulated. The resulting dies may be packaged and the resulting IC packages may be implemented in electronic devices. | 11-14-2013 |
| 20130299948 | SEMICONDUCTOR DEVICE - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. | 11-14-2013 |
| 20130307124 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT, AND ELECTRONIC APPARATUS - A method for manufacturing an electronic component includes mounting a vibrating element on each singulation region of a base substrate, joining the surface of a lid substrate where grooves are arranged to the base substrate via low-melting glass so as to cover a functional element in each singulation region, thereby obtaining a laminate, and performing singulation in each singulation region by breaking the laminate along grooves. | 11-21-2013 |
| 20130328172 | WAFER-LEVEL FLIP CHIP DEVICE PACKAGES AND RELATED METHODS - In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon. | 12-12-2013 |
| 20130334668 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an integrated circuit device having a device contact surface, a device lateral side, and a device backside opposite the device contact surface; forming a device shell, having a shell lip, contiguous with the device backside and the device lateral side, the shell lip adjacent to and coplanar with the device contact surface; attaching a substrate to the integrated circuit device, the device shell between the integrated circuit device and the substrate; and forming an encapsulation on the substrate and covering the integrated circuit device and the device shell. | 12-19-2013 |
| 20130341764 | METHOD FOR MANUFACTURING A DIODE, AND A DIODE - In a method for manufacturing a diode, a semiconductor crystal wafer is used to produce a p-n or n-p junction, which extends in planar fashion across the top side of a semiconductor crystal wafer. Separation edges form perpendicularly to the top side of the semiconductor crystal wafer, which edges extend across the p-n or n-p junction. The separation of the semiconductor crystal wafer is achieved in that, starting from a disturbance, a fissure is propagated by local heating and local cooling of the semiconductor crystal wafer. The separation fissure thus formed extends along crystal planes of the semiconductor crystal, which avoids the formation of defects in the area of the p-n or n-p junction. | 12-26-2013 |
| 20140015110 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor device includes a plurality of semiconductor chips connected through a scribe lane; a plurality of through electrodes formed in each of the plurality of semiconductor chips; a heat dissipation member formed in the scribe lane; and heat transfer members connecting the through electrodes with the heat dissipation member. | 01-16-2014 |
| 20140015111 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface. | 01-16-2014 |
| 20140015112 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam. | 01-16-2014 |
| 20140015113 | Laser Processing Method and Semiconductor Device - A laser processing method which can reliably form a modified region within an object to be processed along a desirable part in a line to cut is provided. | 01-16-2014 |
| 20140015114 | ELECTRONIC DEVICE MANUFACTURING METHOD, ELECTRONIC DEVICE, AND CHIP ASSEMBLY - An electronic device manufacturing method includes a cutting step at which a wafer is cut to obtain chips before pattern formation and a polishing step at which cut surfaces of the obtained chips are subjected in one batch to barrel polishing. The method further includes an aligning step at which the polished chips are aligned so that front surfaces thereof face in an upward direction. The method further includes a bonding step at which the cut surfaces of the aligned chips are bonded together with an adhesive to thereby form a chip assembly. The method further includes a pattern forming step at which a circuit pattern is formed on each of the chips of the chip assembly and a melting step at which the adhesive on the chip assembly is melted to thereby separate the chip assembly into chips after pattern formation. | 01-16-2014 |
| 20140035106 | MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS - A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit. | 02-06-2014 |
| 20140035107 | DOUBLE SEAL RING - A double seal ring for an integrated circuit, the double seal ring includes a first seal ring surrounding the integrated circuit and a second seal ring spaced from the first seal ring. The double seal ring further includes two connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop. A method of forming a double seal ring for an integrated circuit includes forming a first seal ring surrounding the integrated circuit and forming a second seal ring spaced from the first seal ring. The method further includes forming two connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop. | 02-06-2014 |
| 20140035108 | SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME - A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion. | 02-06-2014 |
| 20140054749 | SEMICONDUCTOR DEVICE - The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented. | 02-27-2014 |
| 20140054750 | Scribe line structure for wafer dicing and method of making the same - A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing path and the metal vias on the dicing path have a lower metal density than the metal vias not on the dicing path. | 02-27-2014 |
| 20140061864 | SEMICONDUCTOR SUBSTRATE HAVING CRACK PREVENTING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor substrate having a crack preventing structure, the semiconductor substrate including: a plurality of wiring layers and a plurality of insulating layers sequentially stacked on a device divided into integrated circuit device areas and a cutting area separating the device areas from each other; opening parts formed to spatially separate the insulating layers in the device areas and the insulating layers in the cutting area from each other; and chamfering parts formed at outer sides of the insulating layers in the device areas contacting the opening parts, wherein the plurality of wiring layers are formed between the insulating layers in the cutting area and the device. | 03-06-2014 |
| 20140061865 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a semiconductor device including a semiconductor layer, a protective layer including a transparent material, and a transparent resin layer that seals a gap between the semiconductor layer and the protective layer. A chip prevention member with a higher Young's modulus than the transparent resin layer is formed to come into contact with the semiconductor layer in a dicing portion of a layer structure before fragmentation, and dicing is performed in the dicing portion for the fragmentation. | 03-06-2014 |
| 20140070374 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines. | 03-13-2014 |
| 20140077341 | INTEGRATED CIRCUIT AND SEAL RING - An integrated circuit (IC) and a seal ring thereof are provided. The IC includes a first seal ring. The first seal ring is disposed in the IC. The first seal ring includes at least one stagger structure. The at least one stagger structure includes at least one stagger unit. The at least one stagger unit makes staggered connection with another neighboring stagger unit. | 03-20-2014 |
| 20140084425 | PERIMETER TRENCH SENSOR ARRAY PACKAGE - One embodiment of a perimeter trench sensor array package can include a thinned substrate device that includes a perimeter trench formed near the edges of the device that can be configured to be thinner than a central portion of the thinned substrate device. The perimeter trench can include bond pads that can couple to electrical elements included in the thinned substrate device. The thinned substrate device can be attached to a core layer that can in turn support one or more resin layers. The core layer and the resin layers can form a printed circuit board assembly, a flex cable assembly or a stand-alone module. | 03-27-2014 |
| 20140084426 | SUBSTRATE MEMBER AND METHOD OF MANUFACTURING CHIP - A substrate member includes a substrate and a plurality of chip regions formed on the substrate across a scribe line. Each of the plurality of chip regions includes a first region that has contact with the scribe line and in which a plurality of first pattern elements are formed, and a second region that is surrounded by the first region and in which a plurality of second pattern elements are formed. A minimum value of a size of the first pattern elements is greater than a minimum value of a size of the second pattern elements and/or a minimum value of an interval between adjacent first pattern elements is greater than a minimum value of an interval between adjacent second pattern elements. | 03-27-2014 |
| 20140084427 | MULTI-CORE DIES PRODUCED BY RETICLE SET MODIFICATION - A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus. | 03-27-2014 |
| 20140091437 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. | 04-03-2014 |
| 20140103495 | WAFER AND METHOD FOR PROCESSING A WAFER - A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening. | 04-17-2014 |
| 20140103496 | SEAL RING STRUCTURES WITH REDUCED MOISTURE-INDUCED RELIABILITY DEGRADATION - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 04-17-2014 |
| 20140117505 | Chip Having Backside Metal and Method for Manufacturing Same - A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing. | 05-01-2014 |
| 20140124899 | INTEGRATED BONDLINE SPACERS FOR WAFER LEVEL PACKAGED CIRCUIT DEVICES - A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer. | 05-08-2014 |
| 20140131840 | WAFER AND METHOD OF MANUFACTURING THE SAME - A wafer includes a first die, a second die, and a scribe lane located between the first die and the second die. The scribe lane includes a first doped silicon region, and does not directly contact the first die and the second die. | 05-15-2014 |
| 20140167225 | Crack Stop Barrier and Method of Manufacturing Thereof - A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier. | 06-19-2014 |
| 20140167226 | Wafer and a Method of Dicing a Wafer - A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width. | 06-19-2014 |
| 20140175613 | Chip Positioning in Multi-Chip Package - Embodiments of the present invention include a substrate package, a method for multi chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment. | 06-26-2014 |
| 20140183704 | SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a semiconductor substrate having first and second surfaces and a peripheral edge, the first and second surfaces being opposite to each other, includes forming an inter-layer insulator having a guard ring on the first surface, adjacent to the peripheral edge, forming a first groove on the second surface and adjacent to the peripheral edge, and forming a through electrode that penetrates the second surface to the inter-layer insulator near the first groove and on an opposite side of the groove with respect to the peripheral edge. | 07-03-2014 |
| 20140203410 | DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS - Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer. | 07-24-2014 |
| 20140203411 | PRODUCTION METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE - A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dicing line groove that is formed in a front side surface of the semiconductor wafer, that surrounds the surface electrode with the insulating layer therebetween, of which height from the front side surface of the semiconductor wafer is lower than that of the insulating layer, and that extends to a perimeter of the semiconductor wafer; in which the insulating layer is formed with a communication passage that extends from a side of the surface electrode to the dicing line groove. | 07-24-2014 |
| 20140210056 | SEMICONDUCTOR DEVICE - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. | 07-31-2014 |
| 20140217556 | METHODS FOR DICING A COMPOUND SEMICONDUCTOR WAFER, AND DICED WAFERS AND DIE OBTAINED THEREBY - Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device. | 08-07-2014 |
| 20140217557 | Method and Apparatus for a Seal Ring Structure - A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers. | 08-07-2014 |
| 20140217558 | SEMICONDUCTOR ELEMENT - A semiconductor element includes a substrate and a semiconductor layer. The substrate has a first main face and a second main face. The semiconductor layer is formed on a side of one of the first main face and the second main face of the substrate. The substrate has a plurality of isolated processed portions and an irregularity face that runs from the processed portions at least to the first main face of the substrate and links adjacent ones of the processed portions. | 08-07-2014 |
| 20140239455 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER - To improve reliability of a semiconductor device obtained through a dicing step. | 08-28-2014 |
| 20140239456 | SEMICONDUCTOR WAFER AND ITS MANUFACTURE METHOD, AND SEMICONDUCTOR CHIP - A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between said first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including an lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of said first semiconductor chip area relative to said outer side wall of the lower metal layer. | 08-28-2014 |
| 20140252560 | SUBMOUNT ASSEMBLY INTEGRATION - In accordance with one embodiment, an apparatus is disclosed that comprises a submount operable to integrate with a laser as a laser submount assembly; a predetermined portion of the submount configured to bond with the laser; a bonding pad positioned on the predetermined portion of the submount for integrating the laser with the submount. | 09-11-2014 |
| 20140264766 | System and Method for Film Stress Release - Disclosed herein is a method of forming a stress relieved film stack, the method comprising forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 Ī¼m after the creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide. | 09-18-2014 |
| 20140264767 | Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip - A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench arranged between the crack stop structure and the dicing area. The crack stop structure includes an extended layer extending beyond the crack stop structure towards the dicing area. | 09-18-2014 |
| 20140264768 | Die Preparation for Wafer-Level Chip Scale Package (WLCSP) - Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded. | 09-18-2014 |
| 20140264769 | PACKAGING MECHANISMS FOR DIES WITH DIFFERENT SIZES OF CONNECTORS - Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package. | 09-18-2014 |
| 20140264770 | METHOD OF FORMING THROUGH SUBSTRATE VIAS (TSVS) AND SINGULATING AND RELEASING DIE HAVING THE TSVS FROM A MECHANICAL SUPPORT SUBSTRATE - Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate. | 09-18-2014 |
| 20140264771 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure. | 09-18-2014 |
| 20140284771 | Method for Manufacturing a Plurality of Chips - A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing. | 09-25-2014 |
| 20140291814 | INSULATING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - An insulating substrate includes: a transparent insulating layer; a first metal layer that is provided on a first face of the transparent insulating layer; and a second metal layer that is provided on a second face of the transparent insulating layer that is opposite from the first face. The first face of the transparent insulating layer is formed with an exposed section that is an area not provided with the first metal layer. The second metal layer includes an area that is overlapped with the exposed section when seen in an orthogonal direction to the first face. | 10-02-2014 |
| 20140312465 | Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device - A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area allowing the die seal area to he disregarded for purposes of calculating a process window. | 10-23-2014 |
| 20140312466 | INTEGRATED CIRCUIT SEALING SYSTEM WITH BROKEN SEAL RING - The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating a wide seal ring with a channel having offset ingress and egress portions. | 10-23-2014 |
| 20140327115 | MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS - A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit. | 11-06-2014 |
| 20140339682 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a semiconductor device in which abrasive grain marks are formed in a surface of a semiconductor substrate, a dopant diffusion region has a portion extending in a direction which forms an angle included in a range of ā5Ā° to +5Ā° with a direction in which the abrasive grain marks extend, and the dopant diffusion region is formed by diffusing a dopant from a doping paste placed on one surface of the semiconductor substrate; and a method for manufacturing the semiconductor device. | 11-20-2014 |
| 20140339683 | Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die - A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. | 11-20-2014 |
| 20140346641 | WAFER DICING WITH WIDE KERF BY LASER SCRIBING AND PLASMA ETCHING HYBRID APPROACH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, approaches for wafer dicing with wide kerf by using a laser scribing and plasma etching hybrid approach are described. For example, a method of dicing a semiconductor wafer including a plurality of integrated circuits separated by dicing streets involves forming a mask above the semiconductor wafer, the mask having a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide a patterned mask having a pair of parallel gaps for each dicing street, exposing regions of the semiconductor wafer between the integrated circuits. Each gap of each pair of parallel gaps is separated by a distance. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits. | 11-27-2014 |
| 20140346642 | SURFACE MOUNTABLE ELECTRONIC COMPONENT - A surface mountable electronic component free of connecting wires comprises a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at the underside of the component. The component comprises at least one recess is formed in the region of the edges bounding the underside; and in that the recess is covered with an insulating layer. A method for the manufacture of such a component comprises the formation of corresponding recesses. | 11-27-2014 |
| 20140346643 | INTEGRATED BONDLINE SPACERS FOR WAFER LEVEL PACKAGED CIRCUIT DEVICES - A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer. | 11-27-2014 |
| 20140346644 | Exclusion Zone for Stress-Sensitive Circuit Design - A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length. | 11-27-2014 |
| 20140367835 | Die Seal Ring and Method of Forming the Same - A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring. | 12-18-2014 |
| 20140367836 | SEMICONDUCTOR APPARATUS AND SUBSTRATE - A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall. | 12-18-2014 |
| 20150035125 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view. | 02-05-2015 |
| 20150061079 | Wafer Level Dicing Method - Disclosed herein is a method for dicing a wafer, the method comprising forming a molding compound layer over each of one or more dies disposed on a wafer, the one or more dies separated by scribe lines, the molding compound layer having gaps over the respective scribe lines. The wafer is separated into individual dies along the gaps of the molding compound in the scribe lines. Separating the wafer into individual dies comprises cutting at least a portion of the substrate with a laser. Forming the molding compound layer comprises applying a stencil over the one or more dies and using the stencil to form the molding compound layer. | 03-05-2015 |
| 20150061080 | GUARD RING STRUCTURE OF SEMICONDUCTOR APPARATUS - A guard ring structure of a semiconductor apparatus includes a base wiring layer located above a semiconductor substrate, a first guard ring configured as a wiring stacked structure of two or more layers adjacent to the side of the device forming region above the base wiring layer, and a second guard ring configured to be stacked with the same number of layers as the first guard ring and separated from the first guard ring, the second guard ring formed adjacent to the side of a scribe lane above the base wiring layer. | 03-05-2015 |
| 20150061081 | CRACK DEFLECTOR STRUCTURE FOR IMPROVING SEMICONDUCTOR DEVICE ROBUSTNESS AGAINST SAW-INDUCED DAMAGE - An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal. | 03-05-2015 |
| 20150069577 | REMOVAL OF ELECTROSTATIC CHARGES FROM INTERPOSER FOR DIE ATTACHMENT - A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network. | 03-12-2015 |
| 20150069578 | COMBINATION GRINDING AFTER LASER (GAL) AND LASER ON-OFF FUNCTION TO INCREASE DIE STRENGTH - Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil. | 03-12-2015 |
| 20150076665 | ALIGNMENT MARK STRUCTURE - A conductive structure includes a wafer having a scribe line defined thereon, at least a first wiring layer formed in the scribe line, and at least a via layer disposed in the scribe line and under the wiring layer. The first wiring layer includes a main pattern and the via layer includes a closed frame pattern corresponding to the main pattern of the first wiring layer. | 03-19-2015 |
| 20150084164 | SEMICONDUCTOR DEVICE - The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented. | 03-26-2015 |
| 20150091138 | Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device - A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window. | 04-02-2015 |
| 20150097271 | SELF-HEALING CRACK STOP STRUCTURE - A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an active region of an integrated circuit chip. The crack stop comprises self healing material which, upon propagation of a crack, is structured to seal the crack and prevent further propagation of the crack. | 04-09-2015 |
| 20150097272 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a carrier, several dies disposed on a surface of the carrier and several scribing lines defined on the surface of the carrier. The scribing lines include several continuous lines along a first direction and several discontinuous lines along a second direction. Further, a method of dies singulation includes providing a carrier, disposing several dies on a surface of the carrier according to several scribing lines including several continuous lines along a first direction and several discontinuous lines along a second direction, cutting the carrier according to the continuous lines along the first direction, and cutting the carrier according to the discontinuous lines along the second direction. | 04-09-2015 |
| 20150102467 | METHOD OF DICED WAFER TRANSPORTATION - Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape. | 04-16-2015 |
| 20150108611 | SEMICONDUCTOR INTEGRATED DEVICE FOR DISPLAY DRIVE - In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer. | 04-23-2015 |
| 20150108612 | METHOD FOR THINNING, METALIZING, AND DICING A SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE MADE USING THE METHOD - There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines. | 04-23-2015 |
| 20150108613 | SEMICONDUCTOR CHIP WITH SEAL RING AND SACRIFICIAL CORNER PATTERN - A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner. | 04-23-2015 |
| 20150115411 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A method of producing a semiconductor device includes forming an insulating film on a substrate on which a semiconductor layer is formed; removing a part of the insulating film by etching to form an opening in the insulating film; supplying steam with a temperature greater than or equal to 200Ā° C. and less than or equal to 600Ā° C. to the opening formed in the insulating film; after supplying the steam, applying a solution including a silicon compound to a side surface or the insulating film defining the opening; and forming a hydrophobic film on the side surface of the insulating film defining the opening by polymerizing the silicon compound. | 04-30-2015 |
| 20150130028 | METHOD OF MANUFACTURING SEMICONDUCTOR CHIP, SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions. | 05-14-2015 |
| 20150137322 | Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die - A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections. | 05-21-2015 |
| 20150294954 | MULTIPLE DIE LAYOUT FOR FACILITATING THE COMBINING OF AN INDIVIDUAL DIE INOTO A SINGLE DIE - An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die. | 10-15-2015 |
| 20150303112 | METHOD FOR SINGULATING AN ASSEMBLAGE INTO SEMICONDUCTOR CHIPS, AND SEMICONDUCTOR CHIP - A method for singulating an assemblage ( | 10-22-2015 |
| 20150311166 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN SYSTEM - In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval. | 10-29-2015 |
| 20150325531 | THROUGH CRACK STOP VIA - A semiconductor device includes an active inner region and a crack stop region. The active inner region includes a semiconductor substrate, an integrated circuit (IC) device layer formed upon the semiconductor substrate, and a wiring layer formed upon the IC device layer. The IC device layer includes an integrated circuit device and the wiring layer includes wiring in electrical contact with the integrated circuit device. The crack stop region limits the propagation of cracks and delamination into the active inner region and includes semiconductor material surrounding a crack stop via (CSV) extending through the crack stop region. A lower surface of the CSV may be coplanar with lower surfaces of the crack stop layer and the active inner layer. An upper surface of the CSV may be coplanar with upper surfaces of the crack stop layer and the active inner layer. | 11-12-2015 |
| 20150364376 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate and a bump. The substrate includes a first surface and a second surface. A notch is at the second surface and at a sidewall of the substrate. A depth of the notch is smaller than about half the thickness of the substrate. The bump is disposed on the first surface of the substrate. | 12-17-2015 |
| 20150364510 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor device is provided. The method includes forming a passivation film on a substrate including a first element region, a second element region adjacent to the first element region in a first direction, a third element region adjacent to the first region in a second direction, and a first scribe region extending to the first direction between the first element region and the third element region, forming a first trench in the passivation film between the first scribe region and the first element region, forming a second trench in the passivation film between the third element region and the first scribe region, and forming a film on the passivation film where the trenches have been formed by coating. The each of trenches is formed continuously along the first and the second element region. | 12-17-2015 |
| 20150364514 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor device is provided. The method includes forming a passivation film on a substrate including a plurality of element regions and a scribe region, forming a trench in the passivation film in a region of the scribe region along an outer edge of each of the element regions, and forming a film on the passivation film in which the trench has been formed by coating. A depth of a first section in a first position of the trench is shallower than a depth of a second section in a second position of the trench. A width of the first section is wider than a width of the second section. | 12-17-2015 |
| 20150371902 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a semiconductor layer having a first main surface and a second main surface located opposite to the first main surface and epitaxial layer formed on the first main surface, forming a trench having a sidewall passing through the epitaxial layer and reaching the semiconductor layer and a bottom portion continuing to the sidewall and located in the semiconductor layer, decreasing a thickness of the semiconductor layer by grinding the second main surface, forming an electrode layer on the ground second main surface, achieving ohmic contact between the second main surface and the electrode layer by laser annealing, and obtaining individual substrates by forming a cubing portion along the trench and dividing the semiconductor substrate along the cutting portion. | 12-24-2015 |
| 20150371957 | DIE EDGE SEAL EMPLOYING LOW-K DIELECTRIC MATERIAL - A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing. | 12-24-2015 |
| 20150371966 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device according to the present invention includes a mount substrate, an adhesive applied to the mount substrate, and a device having its lower surface bonded to the mount substrate with the adhesive. The surface roughness of a side surface upper portion of the device is lower than that of a side surface lower portion of the device. | 12-24-2015 |
| 20160005655 | METHOD OF FORMING A SEMICONDUCTOR DIE - In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer. | 01-07-2016 |
| 20160027742 | PORTABLE APPARATUS, IC PACKAGING STRUCTURE, IC PACKAGING OBJECT, AND IC PACKAGING METHOD THEREOF - A portable apparatus, an IC packaging structure, an IC packaging object, and an IC packaging method thereof are disclosed. The IC packaging structure includes an IC packaging object and a substrate. The packaging object includes a die and a metallurgy layer. The die has a contact portion, a saw reserved portion, and a seal ring. The seal ring is disposed between the contact portion and the saw reserved portion. The metallurgy layer is disposed on the contact portion. At least a part of the metallurgy layer overlaps the seal ring. The metallurgy layer includes a solderable layer coated by a solder paste. The substrate includes a solder pad. The solder pad is coupled to the solderable layer coated by the solder paste. | 01-28-2016 |
| 20160027744 | METHOD OF FORMING AN INTEGRATED CRACKSTOP - A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer. | 01-28-2016 |
| 20160035560 | Carrier System For Processing Semiconductor Substrates, and Methods Thereof - In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier. | 02-04-2016 |
| 20160035828 | COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SAME, AND RESIN-SEALED TYPE SEMICONDUCTOR DEVICE - In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture. | 02-04-2016 |
| 20160049333 | DESIGN METHOD OF TIP SHAPE OF CUTTING MEMBER, SEMICONDUCTOR CHIP MANUFACTURING METHOD, CIRCUIT BOARD, AND ELECTRONIC APPARATUS - A design method includes a process of preparing plural cutting members having different degrees of taper in a tip portion thereof, a process of preparing plural grooves on a front surface side having the same shape, a process of confirming a breakage status when a groove on a rear surface side is formed by the plural cutting members, and a process of selecting, when it is confirmed that both of a cutting member that causes breakage and a cutting member that does not cause the breakage are included, the degree of taper of the cutting member that does not cause the breakage as a tip shape of a cutting member to be used in a mass production process. | 02-18-2016 |
| 20160049348 | SEMICONDUCTOR BORDER PROTECTION SEALANT - A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads on the active circuitry layer, which are configured to be connected to corresponding external conductive connectors. The semiconductor package also includes a protective sealant coating filling grooved edges of the active circuitry layer. The protective sealant coating contains an exterior wafer-singulated surface. | 02-18-2016 |
| 20160064338 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate comprising a front surface, side surfaces, a back surface, and a recessed edge between the side surfaces and either the front surface or the back surface, the front surface comprising an active region, the active region comprising at least one contact pad, a polymeric member disposed and contacted with the recessed edge of the substrate, a mold disposed over the front surface of the substrate and the polymeric member, and an interface between the mold and the polymeric member. | 03-03-2016 |
| 20160071767 | METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP AND CIRCUIT BOARD AND ELECTRONIC APPARATUS INCLUDING SEMICONDUCTOR CHIP - A method for manufacturing a semiconductor chip includes forming at least a portion of a front-side groove by anisotropic dry etching from a front surface of a substrate along a cutting region; forming a modified region in the substrate along the cutting region by irradiating the inside of the substrate with a laser along the cutting region; and dividing the substrate along the cutting region by applying stress to the substrate. | 03-10-2016 |
| 20160079183 | SEMICONDUCTOR DEVICE ARRANGEMENT AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE ARRANGEMENT - A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side. | 03-17-2016 |
| 20160093534 | Method for Separating Chips from a Wafer - The invention relates to a method for producing chips ( | 03-31-2016 |
| 20160104682 | Crack Stop Barrier and Method of Manufacturing Thereof - A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier. | 04-14-2016 |
| 20160118352 | SEMICONDUCTOR DEVICE - To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade. | 04-28-2016 |
| 20160133580 | SCRIBE SEALS AND METHODS OF MAKING - A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer. | 05-12-2016 |
| 20160141209 | DEVICE MANUFACTURING METHOD AND DEVICE - A device manufacturing method according to an embodiment includes forming a film on the second surface side of a substrate having a first surface and the second surface, forming a trench in part of the substrate from the first surface side, while leaving the film to remain, and injecting a substance onto the film from the second surface side, to remove the film at the portion on the second surface side of the trench. | 05-19-2016 |
| 20160148842 | DICING OF LOW-K WAFERS - Consistent with an example embodiment, there is a method for sawing a wafer substrate, the wafer substrate having a front-side surface containing active devices separated by saw lanes and a back-side surface having undergone back grinding, the saw lanes having process control monitor (PCM) devices present therein. The method comprises: with a blade of a first kerf, sawing the back-side surface in tracks corresponding to the saw lanes, to a first depth; laser grooving (LG) the saw lanes, to an LG depth, on the front-side surface of the wafer substrate until PCM devices are substantially removed, the LG having a preset beam diameter; and with a blade of a second kerf, the second kerf less than the first kerf, sawing the front-side surface of the wafer substrate about the center of the saw lanes until the active devices are separated from one another. | 05-26-2016 |
| 20160148875 | SEMICONDUCTOR ELEMENT SUBSTRATE, AND METHOD FOR PRODUCING SAME - A diffusion time when forming an isolation region is shortened without deteriorating strength against wafer cracks. A plurality of circular holes | 05-26-2016 |
| 20160172263 | METHOD AND STRUCTURE FOR WAFER-LEVEL PACKAGING | 06-16-2016 |
| 20160181210 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 06-23-2016 |
| 20160190070 | Multiple Edge Enabled Patterning - Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance. | 06-30-2016 |
| 20160204032 | METHOD FOR DIVIDING A COMPOSITE INTO SEMICONDUCTOR CHIPS, AND SEMICONDUCTOR CHIP | 07-14-2016 |
| 20160204071 | SEMICONDUCTOR DIE AND DIE CUTTING METHOD | 07-14-2016 |
| 20160254160 | Method of Manufacturing Semiconductor Device and Semiconductor Device | 09-01-2016 |
| 20160254232 | Combined wafer production method with laser treatment and temperature-induced stresses | 09-01-2016 |
| 20160379884 | Method of Dicing a Wafer - A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer. | 12-29-2016 |
| 20170236771 | Method of Forming a Reliable and Robust Electrical Contact | 08-17-2017 |
| 20170236830 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELLS ARRANGED THREE-DIMENSIONALLY AND METHOD OF MANUFACTURING THE SAME | 08-17-2017 |
| 20190148217 | Method for Manufacturing a Semiconductor Device | 05-16-2019 |
| 20220139780 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - The following are performed in this method for producing a semiconductor device: a step for forming multiple surface electrode metals joined to a surface of a semiconductor layer on a wafer on which multiple semiconductor devices are attached; a step for excavating a semiconductor layer outside an outer edge of the surface electrode metal to form an outermost edge trench of the semiconductor device; a dicing step for cutting out individual semiconductor devices from the wafer; and a kerf check performed after the dicing step by checking the distance from the outermost edge trench to the chip outline position of the semiconductor device. | 05-05-2022 |
