Class / Patent application number | Description | Number of patent applications / Date published |
257617000 | INCLUDING REGION CONTAINING CRYSTAL DAMAGE | 61 |
20080197454 | METHOD AND SYSTEM FOR REMOVING IMPURITIES FROM LOW-GRADE CRYSTALLINE SILICON WAFERS - Techniques are here disclosed for a solar cell pre-processing. The method and system remove impurities from low-grade crystalline semiconductor wafers and include forming a low-grade semiconductor wafer having a substrate having high impurity content. The process and system damage at least one surface of the semiconductor wafer either in the semiconductor wafer forming step or in a separate step to form a region on the surface that includes a plurality of gettering centers. The gettering centers attract impurities from the substrate during subsequent processing. The subsequent processes include diffusing impurities from the substrate using a phosphorus gettering process that includes impregnating the surface with a phosphorus material for facilitating the formation of impurity clusters associated with the gettering centers. Then, the process and system remove from the a portion having the impregnated phosphorus material and the impurity clusters, thereby yielding a semiconductor wafer having a substrate having a generally reduced impurity content. | 08-21-2008 |
20080224269 | Gettering structures and methods and their application - An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation. | 09-18-2008 |
20080315364 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME - After introducing oxygen into an N | 12-25-2008 |
20090108408 | Method for Trapping Implant Damage in a Semiconductor Substrate - A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap atoms and emitted interstitial atoms. | 04-30-2009 |
20090256241 | THIN SILICON WAFER AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a thin silicon wafer by slicing a silicon single crystal includes: a thinning step S | 10-15-2009 |
20090267191 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics. | 10-29-2009 |
20090315152 | DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF - A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions. | 12-24-2009 |
20090321883 | SILICON SUBSTRATE FOR SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - This method for manufacturing a silicon substrate for a solid-state imaging device, includes: a carbon compound layer forming step of forming a carbon compound layer on the surface of a silicon substrate; an epitaxial step of forming a silicon epitaxial layer on the carbon compound layer; and a heat treatment step of subjecting the silicon substrate having the epitaxial layer formed thereon to a heat treatment at a temperature of 600 and 800° C. for 0.25 to 3 hours so as to form gettering sinks that are complexes of carbon and oxygen below the epitaxial layer. This silicon substrate for a solid-state imaging device is manufactured by the above-mentioned method and includes: n epitaxial layer positioned on the surface of a silicon substrate; and a gettering layer which is positioned below the epitaxial layer and includes BMDs having a size of 10 to 100 nm at a concentration of 1.0×10 | 12-31-2009 |
20090321884 | METHOD OF FABRICATING AN EPITAXIALLY GROWN LAYER - A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion. | 12-31-2009 |
20100038755 | SILICON WAFER WITH CONTROLLED DISTRIBUTION OF EMBRYOS THAT BECOME OXYGEN PRECIPITATES BY SUCCEEDING ANNEALING AND ITS MANUFACTURING METHOD - A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility. | 02-18-2010 |
20100059861 | SEMICONDUCTOR WAFER COMPOSED OF MONOCRYSTALLINE SILICON AND METHOD FOR PRODUCING ITo - Semiconductor wafers composed of monocrystalline silicon and doped with nitrogen contain an OSF region and a PV region, wherein the OSF region extends from the center radially toward the edge of the wafer as far as the P | 03-11-2010 |
20100078767 | SILICON WAFER AND FABRICATION METHOD THEREOF - Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10 % over the bulk area. | 04-01-2010 |
20100084743 | METHOD FOR REDUCING CRYSTAL DEFECT OF SIMOX WAFER AND SIMOX WAFER - The method includes: a first step of colliding ions implanted from a surface of a SIMOX wafer into a silicon layer underneath a BOX layer against crystal defects to destroy the crystal defects; and a second step of heating the wafer obtained in the first step to recrystallize the silicon layer. If the ions to be implanted into the silicon layer are oxygen ions, then the first step initiates ion implantation with the temperature of the SIMOX wafer being 50° C. or lower, and sets an ion dose to 5×10 | 04-08-2010 |
20100090314 | FINAL POLISHING METHOD FOR SILICON SINGLE CRYSTAL WAFER AND SILICON SINGLE CRYSTAL WAFER - The present invention provides a final polishing method for a silicon single crystal wafer that performs final polishing with a polishing rate being set to 10 nm/min or below at a final polishing step as a final step among a plurality of polishing steps for polishing the silicon single crystal wafer with a polishing slurry being interposed between the silicon single crystal wafer and a polishing pad, and a silicon single crystal wafer subjected to final polishing by this method. Hereby, there can be provided the final polishing method that can obtain a silicon single crystal wafer with less PIDs (Polishing Induced Defects) and the silicon single crystal wafer subjected to final polishing by this method. | 04-15-2010 |
20100140746 | IMPROVED PROCESS FOR PREPARING CLEANED SURFACES OF STRAINED SILICON - The present invention relates to a method of treating wafers comprising at least one surface layer of silicon-germanium (SiGe) and a layer of strained silicon (sSi) in contact with the SiGe layer, the sSi layer being exposed by etching of the SiGe layer, the method comprising the steps of: (a) a first selective etch of the SiGe layer, optionally followed by an oxidative cleaning step; (b) a rinsing step using deionized water; (c) drying; and (d) a second selective etch step. The present invention relates to a wafer comprising at least one surface layer of strained silicon (sSi), said surface layer of sSi having a thickness of at least 5 nanometres and at most 100 μm of at most 200 defects per wafer. | 06-10-2010 |
20100148310 | Semiconductor wafer, semiconductor device using the same, and method and apparatus for producing the same - A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about −70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more. | 06-17-2010 |
20100155903 | Annealed wafer and method for producing annealed wafer - An annealed wafer having enhanced gettering effects for Cu is produced by heating a silicon substrate containing a nitrogen concentration of 5×10 | 06-24-2010 |
20100164071 | Silicon wafer and method for producing the same - Silicon wafers having excellent voltage resistance characteristics of an oxide film and high C-mode characteristics are derived from single crystal silicon ingots doped with nitrogen and hydrogen, characterized in that a plurality of voids constituting a bubble-like void aggregates are present ≧50% relative to total voids; a V1 region having a void density of over 2×10 | 07-01-2010 |
20100200956 | COMPOUND SEMICONDUCTOR SUBSTRATE, PROCESS FOR PRODUCING COMPOUND SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing the compound semiconductor substrate having a reduced dislocation density at an interface between a Si substrate. Contaminants, such as organic matter and metal, on a surface of a Si substrate are removed whereby a flat oxide film is formed. The oxide film on the surface is removed by using an aqueous hydrogen fluoride solution, whereby hydrogen termination treatment is performed. Immediately after being subjected to the hydrogen termination treatment the temperature of the Si substrate is raised in a vacuum apparatus. If the substrate temperature is raised without any operation, the termination hydrogen is released. Before the hydrogen is released, pre-irradiation with As is performed. Thus, an interface between the Si substrate and the compound semiconductor layer is prepared. Several minutes later, irradiation with Ga and As is performed. Thereby, the compound semiconductor is formed. | 08-12-2010 |
20100252914 | OPTICAL SEMICONDUCTOR DEVICE WITH A CONCENTRATION OF RESIDUAL SILICON - In a crystal growth reactor, a source material having an etching action and a crystal growth source material are simultaneously supplied to a semiconductor wafer surface, so that residual impurities can be eliminated in an efficient manner by balancing etching rate and crystal growth rate. | 10-07-2010 |
20100283126 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate that is made of either of silicon carbide (SiC) and gallium nitride (GaN), and has a defect region containing a crystal defect; a first insulating film that coats the defect region and is arranged on the semiconductor substrate; and a conductor film that electrically connects to a principal surface of the semiconductor substrate, the principal surface being exposed to a region that is not coated with the first insulating film. | 11-11-2010 |
20110001219 | SILICON SINGLE CRYSTAL WAFER, METHOD FOR PRODUCING SILICON SINGLE CRYSTAL OR METHOD FOR PRODUCING SILICON SINGLE CRYSTAL WAFER, AND SEMICONDUCTOR DEVICE - The present invention is a silicon single crystal wafer grown by the Czochralski method, the silicon single crystal wafer in which an wafer entire plane is an N region located outside OSFs which are generated in the form of a ring when thermal oxidation treatment is performed and contains no defect region detected by the RIE process. As a result, a silicon single crystal wafer which belongs to none of a vacancy-rich V region, an OSF region, a Dn region in an Nv region, the Dn region in which a defect detected by the Cu deposition process is generated, and an interstitial silicon-rich I region and can improve the TDDB characteristic which is the time dependent breakdown characteristic of an oxide film more reliably than a known silicon single crystal wafer is provided, and the silicon single crystal wafer is provided under stable production conditions. | 01-06-2011 |
20110049679 | METHOD OF PROCESSING OF NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR WAFER, METHOD OF PRODUCING NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 μm-10 μm thick edge process-induced degradation layer. | 03-03-2011 |
20110062558 | SEMICONDUCTOR WAFER FOR SEMICONDUCTOR COMPONENTS AND PRODUCTION METHOD - A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms. | 03-17-2011 |
20110079881 | INTEGRATED CIRCUIT CHIP PROTECTED AGAINST LASER ATTACKS - An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 μm from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 10 | 04-07-2011 |
20110079882 | Wafer and a Method for Manufacturing a Wafer - A wafer includes a wafer frontside and a region adjacent to the device surface, wherein the region includes vacancy-oxygen complexes and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property. | 04-07-2011 |
20110089538 | LOW ETCH PIT DENSITY (EPD) SEMI-INSULATING III-V WAFERS - Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density. | 04-21-2011 |
20110115056 | GETTER HAVING TWO ACTIVATION TEMPERATURES AND STRUCTURE COMPRISING THIS GETTER - The structure comprises a closed cavity under a controlled atmosphere in which a monoblock getter with a first getter layer is arranged. The first getter layer presents at least first and second getter areas which have different activation temperatures. The second getter area is formed on an adjustment sub-layer of the getter material activation temperature. | 05-19-2011 |
20110140243 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects. | 06-16-2011 |
20110156215 | Silicone Wafer and Production Method Therefor - A silicon wafer includes BMDs with a diagonal length of from 10 nm to 50 nm, and has a density of BMD which exists at a depth of 50 μm and deeper from the surface of the silicon wafer which is greater than or equal to 1×10 | 06-30-2011 |
20110156216 | Silicon Wafer and Method For Producing The Same - Silicon wafers doped with nitrogen, hydrogen and carbon, have a plurality of voids, wherein 50% or more of the total number of voids are bubble-like shaped aggregates of voids;
| 06-30-2011 |
20110175202 | Method For Producing Semiconductor Wafers Composed Of Silicon Having A Diameter Of At Least 450 mm, and Semiconductor Wafer Composed Of Silicon Having A Diameter of 450 mm - Silicon semiconductor wafers are produced by:
| 07-21-2011 |
20110175203 | INTEGRATED CIRCUIT WITH IMPROVED INTRINSIC GETTERING ABILITY - An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×10 | 07-21-2011 |
20110233731 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device, in which a plurality of crystal defects for controlling the life time of carries are distributed in a silicon substrate, is characterized in that the total number of the crystal defects that cause a trap level that differs from the energy level of the center of the band gap by less than 0.2 eV, is less than the number of the crystal defects that cause the trap level that is the closest to the energy level of the center of the band gap among trap levels that differ from the energy level of the center of the band gap by 0.2 eV or more. | 09-29-2011 |
20110309478 | SEMICONDUCTOR WAFER PRE-PROCESS ANNEALING AND GETTERING METHOD AND SYSTEM FOR SOLAR CELL FORMATION - Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered. Multicrystalline semiconductor wafers having grain boundaries with impurities may also undergo the annealing and gettering of dispersed defects to the grain boundaries, further increasing the semiconductor substrate purity levels. | 12-22-2011 |
20120001301 | ANNEALED WAFER, METHOD FOR PRODUCING ANNEALED WAFER AND METHOD FOR FABRICATING DEVICE - An annealed wafer obtained by performing rapid thermal annealing on a silicon single crystal wafer sliced from a silicon single crystal ingot in which an entire plane is an OSF region, an N region outside an OSF region, or a mixed region thereof, the silicon single crystal ingot being grown by the Czochralski method, in which RIE defects do not exist in a region having at least a depth of 1 μm from a surface, a good chip yield of a TDDB characteristic is 80% or more, and a depth of a region where an oxygen concentration is decreased due to outward diffusion is within 3 μm from the surface, and a method for producing an annealed wafer. | 01-05-2012 |
20120074526 | DETACHABLE SUBSTRATE AND PROCESSES FOR FABRICATING AND DETACHING SUCH A SUBSTRATE - The invention relates to a detachable substrate for the electronics, optics or optoelectronics industry, that includes a detachable layer resting on a buried weakened region. This substrate is remarkable in that this buried weakened region consists of a semiconductor material that is denser in the liquid state than in the solid state and that contains in places precipitates of naturally volatile impurities. The invention also relates to a process for fabricating and detaching a detachable substrate. | 03-29-2012 |
20120080775 | METHOD OF POLISHING SILICON WAFER AS WELL AS SILICON WAFER - This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. | 04-05-2012 |
20120168912 | METHOD FOR QUANTITATIVELY EVALUATING CONCENTRATION OF ATOMIC VACANCIES EXISTING IN SILICON WAFER, METHOD FOR MANUFACTURING SILICON WAFER, AND SILICON WAFER MANUFACTURED BY THE METHOD FOR MANUFACTURING SILICON WAFER - A quantitative evaluation method, a method for manufacturing a silicon wafer, and a silicon wafer manufactured by the method, enabling more efficient evaluation of the concentration of atomic vacancies existing in a silicon wafer. The quantitative evaluation method includes steps of: oscillating, in a state in which an external magnetic field is applied to a silicon wafer ( | 07-05-2012 |
20120241912 | THERMAL TREATMENT METHOD OF SILICON WAFER AND SILICON WAFER - There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer. | 09-27-2012 |
20130069203 | GETTERING METHOD FOR DIELECTRICALLY ISOLATED DEVICES - A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps. | 03-21-2013 |
20130075868 | METHODS OF TRANSFERRING LAYERS OF MATERIAL IN 3D INTEGRATION PROCESSES AND RELATED STRUCTURES AND DEVICES - Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods. | 03-28-2013 |
20130175672 | LOW TEMPERATURE LAYER TRANSFER PROCESS USING DONOR STRUCTURE WITH MATERIAL IN RECESSES IN TRANSFER LAYER, SEMICONDUCTOR STRUCTURES FABRICATED USING SUCH METHODS - Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods. | 07-11-2013 |
20130193559 | CAST SILICON ingot prepared BY DIRECTIONAL SOLIDIFICATION - A cast silicon crystalline ingot comprises two major generally parallel surfaces, one of which is the front surface and the other of which is the back surface; a perimeter surface connecting the front surface and the back surface; and a bulk region between the front surface and the back surface; wherein the cast silicon crystalline ingot has no transverse dimension less than about five centimeters; the cast silicon crystalline ingot has a dislocation density of less than 1000 dislocations/cm | 08-01-2013 |
20130264685 | METHOD FOR MANUFACTURING SILICON SINGLE CRYSTAL WAFER AND ANNEALED WAFER - The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×10 | 10-10-2013 |
20140103492 | SILICON WAFER AND METHOD FOR PRODUCING THE SAME - The present invention provides a method for producing a silicon wafer from a defect-free silicon single crystal grown by a CZ method, the method comprising: preparing a silicon wafer obtained by slicing the defect-free silicon single crystal and subjected to mirror-polishing; then performing a heat treatment step of subjecting the mirror-polished silicon wafer to heat treatment at a temperature of 500° C. or higher but 600° C. or lower for 4 hours or more but 6 hours or less; and performing a repolishing step of repolishing the silicon wafer after the heat treatment step such that a polishing amount becomes 1.5 μm or more. Therefore, it is an object to provide a method by which a silicon wafer can be produced at a high yield, the silicon wafer in which LPDs are reduced to a minimum, the silicon wafer with a low failure-incidence rate in an inspection step and a shipment stage. | 04-17-2014 |
20140103493 | ARRANGEMENT AND METHOD FOR MANUFACTURING A CRYSTAL FROM A MELT OF A RAW MATERIAL AND SINGLE CRYSTAL - An arrangement for manufacturing a crystal of the melt of a raw material comprises: a furnace having a heating device with one or more heating elements, which are configured to generate a gradient temperature field directed along a first direction, a plurality of crucibles for receiving the melt, which are arranged within the gradient temperature field side by side, and a device for homogenizing the temperature field within a plane perpendicular to the first direction in the at least two crucibles. The arrangement further has a filling material inserted within a space between the crucibles wherein the filling shows an anisotropic heat conductivity. Additionally or alternatively, the arrangement may comprise a device for generating magnetic migration fields, both the filling material having the anisotropic heat conductivity and the device for generating magnetic migration fields being suited to compensate or prevent the formation of asymmetric phase interfaces upon freezing of the raw melt. | 04-17-2014 |
20140124897 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ANTENNA SWITCH MODULE - Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer. | 05-08-2014 |
20140191370 | SILICON SINGLE CRYSTAL WAFER, MANUFACTURING METHOD THEREOF AND METHOD OF DETECTING DEFECTS - A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected. | 07-10-2014 |
20140246755 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Hydrogen atoms and crystal defects are introduced into an n− semiconductor substrate by proton implantation. The crystal defects are generated in the n− semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current. | 09-04-2014 |
20140264756 | STACKED INTEGRATED CIRCUIT - The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers). | 09-18-2014 |
20140264757 | METAL STRUCTURES AND METHODS OF USING SAME FOR TRANSPORTING OR GETTERING MATERIALS DISPOSED WITHIN SEMICONDUCTOR SUBSTRATES - Embodiments of the present invention provide metal structures for transporting or gettering materials disposed on or within a semiconductor substrate. A structure for transporting a material disposed on or within a semiconductor substrate may include a metal structure disposed within the semiconductor substrate and at a spaced distance from the material. The metal structure is configured to transport the material through the semiconductor substrate and to concentrate the material at the metal structure. The material may include a contaminant disposed within the semiconductor substrate, e.g., that originates from electronic circuitry on the substrate. | 09-18-2014 |
20140327112 | METHOD TO DELINEATE CRYSTAL RELATED DEFECTS - Process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device. | 11-06-2014 |
20140346639 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR SUBSTRATE OBTAINED - The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number. | 11-27-2014 |
20150145105 | HIGH-RESISTIVE SILICON SUBSTRATE WITH A REDUCED RADIO FREQUENCY LOSS FOR A RADIO-FREQUENCY INTEGRATED PASSIVE DEVICE - The application relates to a high-resistivity silicon substrate ( | 05-28-2015 |
20150325433 | SEMICONDUCTOR WAFER COMPOSED OF SILICON AND METHOD FOR PRODUCING SAME - Monocrystalline silicon semiconductor wafers have a front side and a rear side, and a denuded zone which extends from the front side to the rear side as far as a depth which between a center and an edge of the semiconductor wafer on average is not less than 8 μm and not more than 18 μm, and having a region adjoining the denuded zone having BMDs whose density at a distance of 30 μm from the front side is not less than 2×10 | 11-12-2015 |
20150325661 | SUBSTRATE FOR MOLECULAR BEAM EPITAXY (MBE) HGCDTE GROWTH - A semiconductor structure having a first semiconductor body having an upper surface with a non <211>crystallographic orientation and a second semiconductor body having a surface with a <211>crystallographic orientation, the surface of the second semiconductor body being bonded to a bottom surface of the first semiconductor body. A layer comprising CdTe is epitaxially disposed on the upper surface of the second semiconductor body. The second semiconductor body is CZ silicon, has a thickness less than 10 microns and has a diameter of at least eight inches. A getter having micro-cavities has a bottom surface formed on an upper surface of the first semiconductor body and has an upper surface bonded to a bottom surface of the second semiconductor body. | 11-12-2015 |
20160005622 | METHOD FOR REDUCING NONUNIFORMITY OF FORWARD VOLTAGE OF SEMICONDUCTOR WAFER - There is provided a method for reducing the nonuniformity of forward voltage Vf of an N-type semiconductor wafer in which density of impurities included in an N-layer is nonuniformly distributed in a plane view of the semiconductor wafer. The method reduces the nonuniformity of forward voltage, by irradiating charged particles to the N-type semiconductor wafer, and generating defects in the N-layer to reduce the nonuniformity of forward voltage. In one aspect of the method, charged particles are irradiated so that a reaching positon in a depth direction or an irradiation density may differ according to the density of impurities in the N-layer in the plane view of the semiconductor wafer. | 01-07-2016 |
20160042949 | METHOD OF FORMING HIGH-RESISTIVITY REGION IN Ga2O3-BASED SINGLE CRYSTAL, AND CRYSTAL LAMINATE STRUCTURE AND SEMICONDUCTOR ELEMENT - A method of forming a high-resistivity region in a Ga | 02-11-2016 |
20160042974 | EPITAXIAL SILICON WAFER AND METHOD FOR MANUFACTURING SAME - An epitaxial silicon wafer cut from a silicon single crystal grown by the Czochralski method, and having a diameter of 300 mm or more. In this epitaxial silicon wafer, the time required to cool every part of the silicon single crystal during the growth from 800° C. down to 600° C. is set to 450 minutes or less, the interstitial oxygen concentration is from 1.5×10 | 02-11-2016 |
20220140091 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Provided is a semiconductor device including a semiconductor substrate; a hydrogen donor that is provide inside the semiconductor substrate in a depth direction, has a doping concentration that is higher than a doping concentration of a dopant of the semiconductor substrate, has a doping concentration distribution peak at a first position that is a predetermined distance in the depth direction of the semiconductor substrate away from one main surface of the semiconductor substrate, and has a tail of the doping concentration distribution where the doping concentration is lower than at the peak, farther on the one main surface side than where the first position is located; and a crystalline defect region having a crystalline defect density center peak at a position shallower than the first position, in the depth direction of the semiconductor substrate. | 05-05-2022 |