| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257616000 | Containing germanium, Ge | 51 |
| 20080237802 | STRUCTURES INCLUDING PASSIVATED GERMANIUM - A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide material. The germanium carbide material may be formed by microwave-plasma enhanced chemical vapor deposition by exposing the germanium material to a microwave generated plasma that is formed from a carbon-containing source gas and hydrogen. The source gas may be a carbon-containing gas selected from the group consisting of ethylene, acetylene, ethanol, a hydrocarbon gas having from one to ten carbon atoms per molecule, and mixtures thereof. The resulting germanium carbide material may be amorphous and hydrogenated. The germanium material may be carburized without forming a distinct boundary at an interface between the germanium material and the germanium carbide material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the germanium carbide material, are also disclosed. | 10-02-2008 |
| 20080246120 | REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SiGe CONTAINING SUBSTRATES - A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided. | 10-09-2008 |
| 20080265375 | Methods for the single-sided polishing of semiconductor wafers and semiconductor wafer having a relaxed Si1-x GEx Layer - Single-sided polishing of semiconductor wafers provided with a relaxed Si | 10-30-2008 |
| 20080290468 | STRUCTURE OF FLEXIBLE ELECTRONICS AND OPTOELECTRONICS - A method for producing a flexible electronic device is provided. The method comprises steps of providing a flexible substrate, forming an inorganic film on the flexible substrate and etching the inorganic film to obtain an electronic element of the electronic device. In another aspect, a flexible electronic device is provided. The flexible electronic device comprises a flexible substrate and an inorganic film disposed on the flexible substrate and having an electronic element, wherein the electronic element is formed by etching the inorganic film. | 11-27-2008 |
| 20090026582 | DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above. | 01-29-2009 |
| 20090085167 | Methods for Forming Metal-Germanide Layers and Devices Obtained Thereby - The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO | 04-02-2009 |
| 20090236695 | Semiconductor Wafer With A Heteroepitaxial Layer And A Method For Producing The Wafer - A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate. | 09-24-2009 |
| 20090236696 | Semiconductor Wafer With A Heteroepitaxial Layer and A Method For Producing The Wafer - A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate. | 09-24-2009 |
| 20090302426 | Method for the Selective Deposition of Germanium Nanofilm on a Silicon Substrate and Semiconductor Devices Made Therefrom - A process is provided for fabricating a semiconductor device having a germanium nanofilm layer that is selectively deposited on a silicon substrate in discrete regions or patterns. A semiconductor device is also provided having a germanium film layer that is disposed in desired regions or having desired patterns that can be prepared in the absence of etching and patterning the germanium film layer. A process is also provided for preparing a semiconductor device having a silicon substrate having one conductivity type and a germanium nanofilm layer of a different conductivity type. Semiconductor devices are provided having selectively grown germanium nanofilm layer, such as diodes including light emitting diodes, photodetectors, and like. The method can also be used to make advanced semiconductor devices such as CMOS devices, MOSFET devices, and the like. | 12-10-2009 |
| 20090309190 | SEMICONDUCTOR PROCESSING - A semiconductor product comprises an insulator layer and a SOI (Silicon On Insulator) layer on the insulator layer, wherein the SOI layer contains implanted Germanium (Ge) at or near the interface with the insulator layer so as to form gettering sites. The semiconductor product can be manufactured by ion implanting Germanium (Ge) into silicon material and bonding the silicon material onto a handle so as to form a SOI substrate. | 12-17-2009 |
| 20100044836 | PROCESS FOR PRODUCING LOCALISED Ge0I STRUCTURES, OBTAINED BY GERMANIUM CONDENSATION - The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer. | 02-25-2010 |
| 20100052104 | METHOD FOR FABRICATING A LOCALLY PASSIVATED GERMANIUM-ON-INSULATOR SUBSTRATE - The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention. | 03-04-2010 |
| 20100123218 | METHOD OF FORMING OF A SEMICONDUCTOR FILM, METHOD OF MANUFACTURE OF A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - This invention provides a method of forming semiconductor films on dielectrics at temperatures below 400° C. Semiconductor films are required for thin film transistors (TFTs), on-chip sensors, on-chip micro-electromechanical systems (MEMS) and monolithic 3D-integrated circuits. For these applications, it is advantageous to form the semiconductor films below 400° C. because higher temperatures are likely to destroy any underlying devices and/or substrates. This invention successfully achieves low temperature growth of germanium films using diboran. First, diboran gas is supplied into a reaction chamber at a temperature below 400° C. The diboran decomposes itself at the given temperature and decomposed boron is attached to the surface of a dielectric, for e.g., SiO | 05-20-2010 |
| 20100244198 | CMOS SIGE CHANNEL PFET AND SI CHANNEL NFET DEVICES WITH MINIMAL STI RECESS - Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions. | 09-30-2010 |
| 20100301455 | METHOD FOR PRODUCING A BONDED SUBSTRATE - A method for producing a bonded substrate having a Si | 12-02-2010 |
| 20110006398 | PROCESS, APPARATUS, AND MATERIAL FOR MAKING SILICON GERMANIUM CORE FIBER - A process and apparatus for making silicon or silicon/germanium core fiber is described, which uses a plasma process with reducing agent to make preform. The process also makes the recommendations in selecting the adequate cladding tube for better fiber properties. An improved fiber drawing apparatus is also disclosed in order to draw this new type of preforms. | 01-13-2011 |
| 20110006399 | SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER MANUFACTURING METHOD - A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising a single-crystal Si wafer; an insulating layer that has an open region and that is formed on the wafer; a Ge layer that is epitaxially grown on the wafer in the open region; and a GaAs layer that is epitaxially grown on the Ge layer, wherein the Ge layer is formed by (i) placing the wafer in a CVD reaction chamber that can create an ultra-high vacuum low-pressure state, (ii) performing a first epitaxial growth at a first temperature at which raw material gas can thermally decompose, (iii) performing a second epitaxial growth at a second temperature that is higher than the first temperature, (iv) performing a first annealing, at a third temperature that is loss than a melting point of Ge, on epitaxial layers formed by the first and second epitaxial growths, and (v) performing a second annealing at a fourth temperature that is lower than the third temperature. The Ge layer may he formed by repeating the first annealing and the second annealing a plurality of times, and the insulating layer may be a silicon oxide layer. | 01-13-2011 |
| 20110062557 | 3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME - A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array. | 03-17-2011 |
| 20110180905 | GeSbTe MATERIAL INCLUDING SUPERFLOW LAYER(S), AND USE OF Ge TO PREVENT INTERACTION OF Te FROM SbXTeY AND GeXTeY RESULTING IN HIGH Te CONTENT AND FILM CRYSTALLINITY - A multilayer film stack containing germanium, antimony and tellurium that can be annealed to form a GST product material of homogeneous and smooth character, wherein at least one antimony-containing layer is isolated from a tellurium-containing layer by an intervening germanium layer, and the multilayer film stack comprises at least two intervening germanium layers. The multilayer film stack can be formed by vapor deposition techniques such as chemical vapor deposition or atomic layer deposition. The annealable multilayer film stack can be formed in high aspect ratio vias to form phase change memory devices of superior character with respect to the stoichiometric and morphological characteristics of the GST product material. | 07-28-2011 |
| 20110198729 | Methods and Compositions for Preparing Tensile Strained Ge on Ge1-ySNy Buffered Semiconductor Substrates - The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge | 08-18-2011 |
| 20110227199 | METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND REACTION APPARATUS - There is provided a method of producing a semiconductor wafer by thermally processing a base wafer having a portion to be thermally processed that has a single-crystal layer and is to be subjected to thermal processing and a portion to be protected that is to be protected from heal, to be added during the thermal processing. The method comprises a step of forming, above the portion to be protected, a protective layer for protecting the portion to be protected from an electromagnetic wave to be applied to the base wafer, and a step of annealing the portion to be thermally processed, by applying the electromagnetic wave to the entire base wafer. | 09-22-2011 |
| 20120018848 | HIGH SURFACE DOPANT CONCENTRATION SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING - The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer. | 01-26-2012 |
| 20120119332 | PROCESS FOR PRODUCING A SEMICONDUCTOR-ON-SAPPHIRE ARTICLE - A process for producing a semiconductor-on-sapphire article, including: forming a barrier layer and a semiconductor layer on a sapphire substrate, the barrier layer being disposed between the sapphire substrate and the semiconductor layer to inhibit at least one of aluminium from the sapphire and extended defects arising from the sapphire-semiconductor interface from entering the semiconductor layer; wherein the semiconductor is at least one of silicon and a silicon-germanium alloy. | 05-17-2012 |
| 20120161290 | Black GE Based on Crystalline/Amorphous Core/Shell Nanoneedle Arrays - Direct growth of black Ge on low-temperature substrates, including plastics and rubber is reported. The material is based on highly dense, crystalline/amorphous core/shell Ge nanoneedle arrays with ultrasharp tips (˜4 nm) enabled by the Ni catalyzed vapor-solid-solid growth process. Ge nanoneedle arrays exhibit remarkable optical properties. Specifically, minimal optical reflectance (<1%) is observed, even for high angles of incidence (˜75°) and for relatively short nanoneedle lengths (˜1 μm). Furthermore, the material exhibits high optical absorption efficiency with an effective band gap of ˜1 eV. The reported black Ge can have important practical implications for efficient photovoltaic and photodetector applications on nonconventional substrates. | 06-28-2012 |
| 20120175741 | Method for Direct Deposition of a Germanium Layer - The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a non-reactive carrier gas and a higher order germanium precursor gas, i.e. of higher order than germane (GeH | 07-12-2012 |
| 20120181664 | SUBSTRATE STRUCTURE FOR SEMICONDUCTOR DEVICE FABRICATION AND METHOD FOR FABRICATING THE SAME - The present invention proposes a strip plate structure and a method of manufacturing the same. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing, each of said strip plates including a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets, each strip sheet alternately abutting either the first surfaces or the second surfaces of two adjacent strip plates. | 07-19-2012 |
| 20120217618 | Silicon-Germanium Hydrides and Methods for Making and Using Same - The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds. | 08-30-2012 |
| 20120299156 | WAFER PROCESSING METHOD - A wafer processing method includes the steps of: (a) annealing a silicon wafer at a temperature higher than 650° C.; (b) after step (a), depositing a silicon-germanium layer on the silicon wafer; (c) after step (b), implanting oxygen ions into the silicon wafer; and (d) after step (c), annealing the silicon wafer at a temperature higher than 650° C. to form a silicon oxide layer underneath the silicon-germanium layer. | 11-29-2012 |
| 20120306054 | METHOD OF FORMING HIGH GROWTH RATE, LOW RESISTIVITY GERMANIUM FILM ON SILICON SUBSTRATE - A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium. | 12-06-2012 |
| 20120306055 | METHOD OF FORMING HIGH GROWTH RATE, LOW RESISTIVITY GERMANIUM FILM ON SILICON SUBSTRATE - A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium. | 12-06-2012 |
| 20130020682 | WAFER BACKSIDE DEFECTIVITY CLEAN-UP UTILIZING SLECTIVE REMOVAL OF SUBSTRATE MATERIAL - A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices. | 01-24-2013 |
| 20130082357 | PREFORMED TEXTURED SEMICONDUCTOR LAYER - A base layer of a semiconductor material is formed with a naturally textured surface. The base layer may be incorporated within a photovoltaic structure. A controlled spalling technique, in which substrate fracture is propagated in a selected direction to cause the formation of facets, is employed. Spalling in the [110] directions of a (001) silicon substrate results in the formation of such facets of the resulting base layer, providing a natural surface texture. | 04-04-2013 |
| 20130256838 | METHOD OF EPITAXIAL DOPED GERMANIUM TIN ALLOY FORMATION - A method for forming germanium tin layers and the resulting embodiments are described. A germanium precursor and a tin precursor are provided to a chamber, and an epitaxial layer of germanium tin is formed on the substrate. The germanium tin layer is selectively deposited on the semiconductor regions of the substrate and can include thickness regions of varying tin and dopant concentrations. The germanium tin layer can be selectively deposited by either alternating or concurrent flow of a halide gas to etch the surface of the substrate. | 10-03-2013 |
| 20130264684 | Methods and Apparatus of Wafer Level Package for Heterogeneous Integration Technology - Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections. | 10-10-2013 |
| 20130270680 | METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION - A method for forming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors. | 10-17-2013 |
| 20140035104 | GERMANIUM ON INSULATOR APPARATUS - In an implementation, a Germanium on insulator apparatus is fabricated by forming a patterned masking layer on a Silicon on insulator (SOI) layer that leaves a portion of the SOI layer exposed, implanting Germanium onto the exposed portion of the SOI layer to form a Silicon-Germanium island, depositing amorphous Germanium over the Silicon-Germanium island and the patterned masking layer, removing the patterned masking layer and the amorphous Germanium that was deposited onto the patterned masking layer to produce a Silicon-Germanium composite stripe, and annealing the Silicon-Germanium composite stripe to crystallize the amorphous Germanium in the Silicon-Germanium composite stripe. | 02-06-2014 |
| 20140061862 | SEMICONDUCTOR FIN ON LOCAL OXIDE - A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer. | 03-06-2014 |
| 20140077339 | DELTA DOPING AT Si-Ge INTERFACE - A IV or III-V device is fabricated on a germanium template on a silicon substrate and includes a thin layer of Ge epitaxially grown on a silicon substrate. The thin layer includes Ge delta doped with Sn at the silicon substrate. A single crystal layer of Ge is epitaxially grown on the thin layer of Ge doped with Sn. A structure including one of IV material and III-V material is epitaxially grown on the single crystal layer of Ge. | 03-20-2014 |
| 20140167223 | Semiconductor Cooling Device - A system and a method of self-cooling a semiconductor package are described. A cell is formed, which contains a thermally conductive and electrically insulative material, sandwiched between a first thermally conductive plate and a second thermally conductive plate. A plurality of integrated circuits are formed by combinatorial processing. The plurality of integrated circuits are interconnected into a semiconductor integrated circuit package. The cell is thermally bonded to the semiconductor integrated circuit package. The first thermally conductive plate is electrically connected to the semiconductor integrated circuit package. A current is supplied to the second thermally conductive plate by an electrical lead from a supply voltage. Power is provided in series to the semiconductor integrated circuit package and through the cell. | 06-19-2014 |
| 20140217554 | CRYSTAL LAMINATE STRUCTURE AND METHOD FOR PRODUCING SAME - A crystal laminate structure, in which crystals can be epitaxially grown on a β-Ga | 08-07-2014 |
| 20140252555 | SUBSTRATE FOR FORMING ELEMENTS, AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a substrate for forming elements includes a substrate; an insulating film provided on the substrate; and a Ge layer or an SiGe layer bonded to the substrate via the insulating film. The insulating film is a laminated structure comprising a plurality of films including an oxide film, a high-dielectric constant insulating film, and a compound insulating film including a metal element and Ge. | 09-11-2014 |
| 20140264755 | STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER - Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer. | 09-18-2014 |
| 20140284769 | METHOD OF FORMING A STRAINED SILICON LAYER - The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer. | 09-25-2014 |
| 20150028454 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS - Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer. | 01-29-2015 |
| 20150048485 | METHODS OF FORMING FILMS INCLUDING GERMANIUM TIN AND STRUCTURES AND DEVICES INCLUDING THE FILMS - Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein. | 02-19-2015 |
| 20150102465 | Material quality, suspended material structures on lattice-mismatched substrates - Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality. | 04-16-2015 |
| 20150318351 | MULTIPLE EPITAXIAL HEAD RAISED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME - A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures. | 11-05-2015 |
| 20160035562 | SILICON-CONTAINING SUBSTRATE CLEANING PROCEDURE - A method for cleaning a substrate, such as a silicon substrate, a silicon-germanium substrate, or other silicon-containing substrate is disclosed. The method includes exposing the substrate to a first plasma configured to attack a sub-oxide on the substrate. The method also includes exposing the substrate to a second plasma configured to attack the native oxide on the substrate. The method further includes exposing the substrate to a gas containing at least one of molecular chlorine or a chlorine compound. The gas may be configured to remove at least some of the remaining native oxide and sub-oxide. After the cleaning process, the substrate may be further processed. Further processing steps may include, for example, an epitaxial growth process. An epitaxial growth process performed on a substrate cleaned according to the methods disclosed herein will exhibit few defects. | 02-04-2016 |
| 20160155636 | DEPOSITION METHOD FOR PLANAR SURFACES | 06-02-2016 |
| 20160181095 | SILICON-GERMANIUM FIN OF HEIGHT ABOVE CRITICAL THICKNESS | 06-23-2016 |
| 20160254145 | METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH CONDENSED SILICON GERMANIUM LAYER | 09-01-2016 |
