| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257544000 | With pn junction isolation | 64 |
| 20080197451 | High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications - Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV | 08-21-2008 |
| 20080246116 | Symmetrical programmable crossbar structure - A crossbar structure includes a first layer or layers including first p-type regions and first n-type regions, a second layer or layers including second p-type regions and second n-type regions, and a resistance programmable material formed between the first layer(s) and the second layer(s), wherein the first layer(s) and the second layer(s) include first and second intersecting wiring portions forming a crossbar array. | 10-09-2008 |
| 20090039468 | N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE - A semiconductor memory device that has an isolated area comprised of one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are comprised of the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells. | 02-12-2009 |
| 20090243040 | Micro-heater arrays and pn-junction devices having micro-heater arrays, and methods for fabricating the same - Example embodiments include micro-heater arrays including first and second micro-heaters disposed perpendicular to or parallel with each other on a substrate and methods of fabricating pn junctions between first and second heating portions using the heat generated from the first and second heating portions, respectively, when applying a voltage to the micro-heater array. Accordingly, when forming pn junctions using micro-heaters, a high-quality pn junction may be fabricated on a glass substrate over a large area. | 10-01-2009 |
| 20100052101 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an impurity region when impurities in the impurity region are thermally diffused in a semiconductor substrate. A second photoresist is formed on an insulation film. The second photoresist is formed to have second openings K | 03-04-2010 |
| 20100065945 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening K | 03-18-2010 |
| 20100078764 | Reducing shunt currents in a semiconductor body - A description is given of a concept for reducing shunt currents in a semiconductor body. | 04-01-2010 |
| 20110089533 | SEMICONDUCTOR DEVICE - An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through then epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region. | 04-21-2011 |
| 20110175197 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a plurality of data holding circuits; and a plurality of wells. The plurality of data holding circuits is provided in a substrate of a first conductive type. Each of the plurality of data holding circuits includes a first well of the first conductive type and a second well of a second conductive type different from the first conductive type. The plurality of wells is arranged in two directions for the each of the plurality of data holding circuits. | 07-21-2011 |
| 20110241171 | Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device fabricated using the method - Provided are a method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated using the method. The method includes: forming a mask film, which exposes a portion of a substrate, on the substrate; forming a first buried impurity layer, which contains impurities of a first conductivity type and of a first concentration, in a surface of the exposed portion of the substrate by using the mask film; removing the mask film; forming a second buried impurity layer, which contains impurities of a second conductivity type and of a second concentration, using blank implantation; and forming an epitaxial layer on the substrate having the first and second buried impurity layers, wherein the first concentration is higher than the second concentration. | 10-06-2011 |
| 20110291241 | SEMICONDUCTOR DEVICE - A semiconductor device that has a reduced size and exhibits a superior blocking voltage capability. A semiconductor device includes an edge termination structure between an active region and an isolation region, the edge termination structure being composed of an edge termination structure for a forward bias section and an edge termination structure for a reverse bias section. A plurality of field limiting rings (FLRs) and a plurality of field plates (FPs) are provided in the edge termination structure for the forward bias section and the edge termination structure for the reverse bias section. A first forward FP that is the nearest of the plurality of FPs to the edge termination structure for the reverse bias section is formed to extend towards the isolation region side. A first reverse FP that is the nearest of the plurality of FPs to the edge termination structure for the forward bias section is formed to extend towards the active region side. The first reverse FP stops the depletion layer expanding from the active region on application of a forward voltage. The first forward FP stops the depletion layer expanding from the isolation region on application of a reverse voltage. | 12-01-2011 |
| 20120056304 | Wafer, Fabricating Method Of The Same, And Semiconductor Substrate - A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface. | 03-08-2012 |
| 20120161285 | Reducing High-Frequency Signal Loss in Substrates - An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region. | 06-28-2012 |
| 20120241910 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void. | 09-27-2012 |
| 20120319242 | Dopant Implantation Hardmask for Forming Doped Isolation Regions in Image Sensors - Forming a doped isolation region in a substrate during manufacture of an image sensor. A method of an aspect includes forming a hardmask layer over the substrate, and forming a photoresist layer over the hardmask layer. An opening is formed in the photoresist layer over an intended location of the doped isolation region. An opening is etched in the hardmask layer by exposing the hardmask layer to one or more etchants through the opening. The opening in the hardmask layer may have a width of less than 0.4 micrometers. The doped isolation region may be formed in the substrate beneath the opening in the hardmask layer by performing a dopant implantation that introduces dopant through the opening in the hardmask layer. The method of an aspect may include forming sidewall spacers on sidewalls of the opening in the hardmask layer and using the sidewall spacers as a dopant implantation mask. | 12-20-2012 |
| 20130313682 | Isolated Through Silicon Via and Isolated Deep Silicon Via Having Total or Partial Isolation - Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction. | 11-28-2013 |
| 20140061857 | PARTIALLY-BLOCKED WELL IMPLANT TO IMPROVE DIODE IDEALITY WITH SiGe ANODE - A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction. | 03-06-2014 |
| 20140203406 | ISOLATION STRUCTURE OF HIGH-VOLTAGE DRIVING CIRCUIT - An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area. | 07-24-2014 |
| 20140239450 | GUARD STRUCTURE FOR SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING GUARD LAYOUT PATTERN FOR SEMICONDUCTOR LAYOUT PATTERN - A guard structure for a semiconductor structure is provided. The guard structure includes a first guard ring, a second guard ring and a third guard ring. The first guard ring has a first conductivity type. The second guard ring has a second conductivity type, and surrounds the first guard ring. The third guard ring has the first conductivity type, and surrounds the second guard ring, wherein the first, the second and the third guard rings are grounded. A method of forming a guard layout pattern for a semiconductor layout pattern is also provided. | 08-28-2014 |
| 20140291807 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first well of a first conductivity type formed within the substrate, a second well of a second conductivity type formed underneath the first well within the substrate and a third well of the second conductivity type formed horizontally to the first well within the substrate, and including a first region formed to a first depth from a surface of the substrate, and a second region formed to a second depth greater than the first depth from the surface of the substrate and connected to the second well. | 10-02-2014 |
| 20140312461 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 10-23-2014 |
| 257545000 | With means to control isolation junction capacitance (e.g., lightly doped layer at isolation junction to increase depletion layer width) | 3 |
| 20090283861 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND POWER AMPLIFIER ELEMENT - A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial layer with a low concentration impurity provided on the semiconductor substrate, where a trench coupled to the semiconductor substrate is provided in the epitaxial layer with the low concentration impurity. And the semiconductor device further includes a high concentration impurity region of the first type conductivity having the same type conductivity as the type of the semiconductor substrate formed in at least the epitaxial layer with the low concentration impurity along an inner wall of the trench and coupled to the semiconductor substrate with the high concentration impurity of a first type conductivity, and contacts formed on the high concentration impurity region of the first type conductivity. | 11-19-2009 |
| 20110089534 | Semiconductor Integrated Circuit Devices Having Conductive Patterns that are Electrically Connected to Junction Regions - A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern. | 04-21-2011 |
| 20160254347 | LOW COST AND MASK REDUCTION METHOD FOR HIGH VOLTAGE DEVICES | 09-01-2016 |
| 257546000 | With structural means to protect against excess or reversed polarity voltage | 22 |
| 20080290462 | PROTECTIVE STRUCTURE - A protective structure is produced by providing a semiconductor substrate with a doping of a first conductivity type. A semiconductor layer with a doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, wherein the buried layer is produced at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone with a doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone with a doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first region and the second region of the semiconductor layer. A common connection device is formed for the first dopant zone and the second dopant zone. | 11-27-2008 |
| 20100072575 | LAYOUT PATTERNS FOR DEEP WELL REGION TO FACILITATE ROUTING BODY-BIAS VOLTAGE - Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors. | 03-25-2010 |
| 20100327411 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate, a semiconductor region, a first and second electrodes. The semiconductor region is provided on the semiconductor substrate via an insulating film. The semiconductor region includes a protection diode. An overvoltage causes breakdown of the protection diode. A PN junction of the protection diode is exposed at an end face of the semiconductor region. A first and second electrodes are provided distally to the exposed end face of the PN junction. The first and second electrodes are connected to the semiconductor region to provide a current to the protection diode. | 12-30-2010 |
| 20110001218 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM LSI INCLUDING THE SAME - A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL>tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact. Thus, convergence of the current at the contact holes of the diffusion layer of the anode is reduced, so that the reliability of the diode element improves. | 01-06-2011 |
| 20110079880 | SEMICONDUCTOR DEVICE - A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC | 04-07-2011 |
| 20110084362 | Active Diode Having No Gate and No Shallow Trench Isolation - An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed. | 04-14-2011 |
| 20110227197 | SEMICONDUCTOR INTEGRATED CIRCUIT COMPRISING ELECTRO STATIC DISCHARGE PROTECTION ELEMENT - An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed. | 09-22-2011 |
| 20110260291 | Semiconductor Structure - A semiconductor structure. The semiconductor comprises a substrate, a first deep well, a diode and a transistor. The first deep well is formed in the substrate. The diode is formed in the first deep well. The transistor is formed in the first deep well. The diode is connected to a first voltage, the transistor is connected to a second voltage, and the diode and the transistor are cascaded. | 10-27-2011 |
| 20110298092 | DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING - An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed. | 12-08-2011 |
| 20110309476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device including a protection diode for preventing electrostatic breakdown employing a low capacitance protection diode, an occupation area of a Zener diode as a voltage limiting element is not needed on a front surface of a semiconductor substrate. A P+ type embedded diffusion layer is formed in a P+ type semiconductor substrate. This is then covered by a non-doped first epitaxial layer. A high resistivity N type second epitaxial layer is then formed on the first epitaxial layer. The second epitaxial layer is divided by a P+ isolation layer into a first protection diode forming region and a second protection diode forming region. An N+ type embedded layer extending from the front surface of the first epitaxial layer of the first protection diode forming region to the first epitaxial layer and the second epitaxial layer, and so on are then formed. A Zener diode is formed by a P+ type upward diffusion layer extending from the P+ type embedded diffusion layer and the N+ type embedded layer. | 12-22-2011 |
| 20120025350 | VERTICAL TRANSIENT VOLTAGE SUPPRESSORS - A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region. | 02-02-2012 |
| 20120153437 | ESD PROTECTION STRUCTURE FOR 3D IC - An electrostatic discharge (ESD) protection structure for a 3D IC is provided. The ESD protection structure includes a first active layer, a through-silicon via (TSV) device and a second active layer. The TSV is disposed in the first active layer, and the second active layer is stacked with the first active layer. The second active layer includes a substrate and an ESD protection device, wherein the ESD protection device having a doping area embedded in the substrate, and the ESD protection device electrically connects the TSV device. | 06-21-2012 |
| 20130175669 | ELECTRICAL OVERSTRESS PROTECTION USING THROUGH-SILICON-VIA (TSV) - A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications. | 07-11-2013 |
| 20130285208 | FINFET DIODE WITH INCREASED JUNCTION AREA - A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer. | 10-31-2013 |
| 20140001600 | Diode String | 01-02-2014 |
| 20140175610 | ELECTROSTATIC DISCHARGE DEVICES FOR INTEGRATED CIRCUITS - A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth. | 06-26-2014 |
| 20140191368 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal. | 07-10-2014 |
| 20140197521 | SEMICONDUCTOR DEVICE HAVING TWO-WAY CONDUCTION CHARACTERISTICS, AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT INCORPORATING THE SAME - A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage. | 07-17-2014 |
| 20140252552 | SEMICONDUCTOR DIES HAVING SUBSTRATE SHUNTS AND RELATED FABRICATION METHODS - Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device. | 09-11-2014 |
| 20140312462 | SEMICONDUCTOR DEVICE - A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region. | 10-23-2014 |
| 20140339676 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material. | 11-20-2014 |
| 20160079224 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal. | 03-17-2016 |
| 257547000 | With structural means to control parasitic transistor action or leakage current | 9 |
| 20100164069 | Reducing High-Frequency Signal Loss in Substrates - An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region. | 07-01-2010 |
| 20100320570 | SEMICONDUCTOR DEVICE - The present invention includes a memory cell area that includes a plurality of transistors, and a core area that is arranged adjacent to the memory cell area. The memory cell area and the core area include a semiconductor layer, and an n-type well region and a first p-type well region formed above the semiconductor layer. The memory cell area further includes a second p-type well region formed under the n-type well region and the first p-type well region in the semiconductor layer. The second p-type well region contacts to at least the first p-type well region. | 12-23-2010 |
| 20120211869 | Low Leakage Diodes - A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode. | 08-23-2012 |
| 20130168818 | DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS - Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic. | 07-04-2013 |
| 20130200492 | OPTO-ELECTRONIC DEVICE - The present invention provides a current blocking structure for electronic devices, preferably optoelectronic devices. The current blocking structure comprises a semiconductor material arrangement comprising an n-type ruthenium doped indium phosphide (Ru—InP) layer and a first p-type semiconductor material layer wherein the n-type Ru—InP layer is less than 0.6 μm thick. The semiconductor material arrangement and p-type semiconductor material layer form a current blocking p-n junction. The current blocking structure may further comprise other n-type layers and/or multiple n-type Ru—InP layers and/or intrinsic/undoped layers wherein the n-type Ru—InP layers may be thicker than 0.6 μm. | 08-08-2013 |
| 20130285209 | Low Leakage Diodes - A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode. | 10-31-2013 |
| 20140001601 | METHOD OF REDUCING CURRENT LEAKAGE IN A DEVICE AND A DEVICE THEREBY FORMED | 01-02-2014 |
| 20140159205 | Low OFF-State Leakage Current Field Effect Transistors - A method is presented to decrease the OFF-state leakage current of the Field Effect Transistors (FETs). The presented method comprises of the placement of dopants underneath or anywhere adjacent to the channel which causes an increase in the band barrier at the source edge of the semiconductor of gate region at the OFF state, providing for less leakage current. Compared with the conventional method of increasing the channel doping to decrease the OFF state leakage current and achieve more scalability, a lower channel doping concentration is needed to achieve the same OFF state leakage current. This provides for less impurity scattering and higher mobility which results in larger ON state currents, higher yields and faster devices. | 06-12-2014 |
| 20140306319 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well, and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well. | 10-16-2014 |
| 257548000 | At least three regions of alternating conductivity types with dopant concentration gradients decreasing from surface of semiconductor (e.g., "triple-diffused" integrated circuit) | 3 |
| 20090057831 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor. | 03-05-2009 |
| 20090243041 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece. | 10-01-2009 |
| 20110018101 | SEMICONDUCTOR DEVICE - A semiconductor device | 01-27-2011 |
| 257552000 | With bipolar transistor structure | 6 |
| 20090065899 | SEMICONDUCTOR DEVICE - The invention is directed to providing a technique for increasing a hold voltage of an electrostatic breakdown protection device having a bipolar transistor structure more than conventional and reducing the size of the device. A base region (a P impurity layer) is formed on a front surface of an epitaxial layer, an emitter region (an N+ impurity layer) is formed on the front surface of the P impurity layer, and the epitaxial layer and an N+ impurity layer form a collector region. A connected portion of a base electrode and the base region (the P impurity layer) is located between the end of the base region (the P impurity layer) on a collector electrode side and the emitter region (the N+ impurity layer). It means that the electrodes for the collector, the base and the emitter are formed in this order. The base electrode and the emitter electrode are connected through a wiring (not shown). A P+ isolation layer for dividing the epitaxial layer into a plurality of island regions is further formed. | 03-12-2009 |
| 20100102418 | BIPOLAR DEVICE HAVING IMPROVED CAPACITANCE - The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns. | 04-29-2010 |
| 20110049677 | Buried Layer of An Integrated Circuit - Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed. | 03-03-2011 |
| 20110198726 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region | 08-18-2011 |
| 20120326276 | Buried Layer of An Integrated Circuit - Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed. | 12-27-2012 |
| 20180026226 | DISPLAY APPARATUS HAVING A LARGER DISPLAY REGION AND MOISTURE IMPERMEABILITY | 01-25-2018 |
