| Entries |
| Document | Title | Date |
|---|
| 20080217740 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An object of the invention is to provide a resistor element whose contact area is self-alignedly formed to reduce the contact area size and contact resistance variation and which can be formed finely and with high precision at low cost. A thin metal film is deposited on a substrate surface covered with an insulation film on which wirings are formed. The thin metal film is anisotropically etched to leave a desired portion such that the desired portion straddles between wirings, self-alignedly connecting the thin metal film to be a resistor and the wirings. | 09-11-2008 |
| 20080237797 | ELECTRICALLY TUNABLE RESISTOR AND RELATED METHODS - An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor. | 10-02-2008 |
| 20080237798 | MEMORY CELL AND PROCESS FOR MANUFACTURING THE SAME - A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively. | 10-02-2008 |
| 20080237799 | SEMICONDUCTOR DEVICE CAPABLE OF DECREASING VARIATIONS IN SIZE OF METAL RESISTANCE ELEMENT - A semiconductor device is provided wherein a foundation insulating film is formed over a semiconductor substrate, a metal resistance element is formed on the foundation insulating film, and contacts are formed at both ends of the metal resistance element in a longitudinal direction of the metal resistance element and connected to the metal resistance element. The foundation insulating film comprises a single upwardly concave curved surface constituting not less than about 40 percent of an upper surface of the metal resistance element between the contacts in the longitudinal direction thereof. The curved surface of the foundation insulating film causes the metal resistance element to comprise a single upwardly concave curved surface constituting not less than about 40 percent of upper and lower surfaces of the metal resistance element between the contacts in the longitudinal direction thereof. | 10-02-2008 |
| 20080272460 | THIN FILM RESISTORS INTEGRATED AT TWO DIFFERENT METAL INTERCONNECT LEVELS OF SINGLE DIE - An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor. A fifth interconnect conductor extends through an opening in the first dielectric layer to contact a circuit element. | 11-06-2008 |
| 20080272461 | Capture of residual refractory metal within semiconductor device - There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area. | 11-06-2008 |
| 20080290460 | Chip Resistor, and Its Manufacturing Method - A chip resistor includes: a pair of upper surface electrodes formed at opposing side portions of a rectangular substrate as opposed to each other with respect to a center line of the rectangular substrate extending in a direction connecting the side portions; a resistive element formed on the rectangular substrate to be electrically connected with the upper surface electrode pair; and a pair of end surface electrodes formed on end surfaces of the opposing side portions of the rectangular substrate and electrically connected with the upper surface electrode pair. The chip resistor further includes dummy electrodes formed individually at the opposing side portions of the rectangular substrate at positions corresponding to the upper surface electrode pair in the direction connecting the side portions. | 11-27-2008 |
| 20080290461 | DEEP TRENCH ISOLATION FOR POWER SEMICONDUCTORS - An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the reverse breakdown voltage characteristics such as voltage level, reliability and stability can be improved for a given area of device, or for a given complexity of device, and avalanche breakdown at weaknesses in isolation structures can be reduced or avoided. | 11-27-2008 |
| 20090014836 | Memory Array with a Selector Connected to Multiple Resistive Cells - An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug. | 01-15-2009 |
| 20090014837 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method of manufacturing the same. A high-resistance silicon wafer is manufactured in such a manner that a large-sized silicon wafer manufactured by the Czochralski method is irradiated with neutrons, and high-resistance and low-resistance elements are simultaneously formed on the high-resistance silicon wafer. Thus, the manufacturing cost can be remarkably saved, and the reliability of products can be enhanced. | 01-15-2009 |
| 20090051008 | Semiconductor device having a resistor and methods of forming the same - In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure. | 02-26-2009 |
| 20090057830 | Semidoncudtor device and method of manufacturing the same - On a surface of a semiconductor substrate, an epitaxial layer of a conductivity type opposite to a conductivity type of the semiconductor substrate is formed, trenches are formed in portions other than a portion serving as a resistor, and the trenches are filled with an insulating film to three-dimensionally form U-shaped resistors which are separated from each other. | 03-05-2009 |
| 20090065898 | INTEGRATED BEOL THIN FILM RESISTOR - In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers. | 03-12-2009 |
| 20090140387 | HIGH-DENSITY 3-DIMENSIONAL RESISTORS - Interconnect, i.e., BEOL structures comprising at least one thin film resistor that is located at the same level as that of a neighboring conductive interconnect are provided. The present invention also provides a method of fabricating such interconnect structures utilizing processing steps that are compatible with current interconnect processing. Moreover, the inventive method of the present invention provides better technology extendibility in terms of higher density than prior art schemes. | 06-04-2009 |
| 20090160024 | VERTICAL RESISTORS AND BAND-GAP VOLTAGE REFERENCE CIRCUITS - A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias. | 06-25-2009 |
| 20090174032 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a semiconductor substrate; a three dimensional cell array formed by a plurality of unit cell array blocks of two dimensional arrangement on the semiconductor substrate, the unit cell array block being formed by stacking a plurality of unit cell arrays including a first wiring, a second wiring crossing with the first wiring, and a variable resistance element connected at an intersection of the both wirings; a reading/writing/driving circuit formed on the semiconductor substrate under the three dimensional cell array; a first via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the first wiring in each layer to the reading/writing/driving circuit is formed; and a second via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the second wiring in each layer to the reading/writing/driving circuit is formed. When the first wiring is longer than the second wiring, the number of via arrangements in the first via region is set larger than that in the second via region. | 07-09-2009 |
| 20090184395 | INPUT/OUTPUT (I/O) BUFFER - An I/O buffer including an I/O circuit, a pad and a pulling resistant device. The I/O circuit is for inputting or outputting a signal. The pulling resistant device has a plurality of resistant elements electrically connected between the I/O circuit and the pad, for forming a resistance value. | 07-23-2009 |
| 20090184396 | Resistive random access memories and methods of manufacturing the same - Provided are resistive random access memories (RRAMs) and methods of manufacturing the same. A RRAM includes a storage node including a variable resistance layer, a switching device connected to the storage node, and a protective layer covering an exposed part of the variable resistance layer. The protective layer includes at least one of aluminum oxide and titanium oxide. The variable resistance layer is a metal oxide layer. | 07-23-2009 |
| 20090184397 | NONVOLATILE MEMORY DEVICE AND PROCESSING METHOD - A method of processing a nonvolatile memory device includes forming a first electrode, depositing a layer of sol-gel solution on the first electrode, hydrolyzing the layer of sol-gel solution to form a layer of variable electric resistance material, and forming a second electrode on the layer of variable electric resistance material. | 07-23-2009 |
| 20090200640 | VARIABLE RESISTIVE ELEMENT, AND ITS MANUFACTURING METHOD - A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element. | 08-13-2009 |
| 20090230512 | Nonvolatile Memory Devices that Use Resistance Materials and Internal Electrodes, and Related Methods and Processing Systems - A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes. | 09-17-2009 |
| 20090321878 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode. | 12-31-2009 |
| 20100013050 | Compensation Of Field Effect On Polycrystalline Resistors - A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment. | 01-21-2010 |
| 20100025819 | PROGRAMMABLE PRECISION RESISTOR AND METHOD OF PROGRAMMING THE SAME - A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor. | 02-04-2010 |
| 20100072574 | Semiconductor Device and Manufacturing Method Thereof - A resistor whose characteristic value can be changed without requiring a photolithography process again is provided. The resistor includes a plurality of first resistor units which is connected serially to each other and a second resistor unit which is connected in parallel to part of the first resistor units. Then, after the measurement of a semiconductor integrated circuit, the second resistor unit is electrically disconnected as necessary. The first resistor units may be either a unit including a single resistor or may be a unit including a plurality of resistors. | 03-25-2010 |
| 20100084741 | Integrated Circuit - According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element. | 04-08-2010 |
| 20100109125 | SEMICONDUCTOR DEVICE - The semiconductor device includes a resistor cell that includes a diffused layer resistor, a P-well contact and an N-well contact. The diffused layer resistor is arranged on a semiconductor substrate and is formed by a diffused layer. The P-well contact surrounds an outer rim of the diffused layer resistor and is formed by another diffused layer. The N-well contact is arranged surrounding the outer rim of the P-well contact and is formed by a further diffused layer. Both the P-well and N-well contacts are partitioned into contact portions. Control electrode layer portions are arranged between neighboring contact sections of the P-well contact so the contact sections of the P-well contact and the control electrode layer portions alternate. Control electrode layer portions are arranged between neighboring contact sections of the N-well contact so that the contact sections of the N-well contact and the control electrode layer portions alternate with one another. | 05-06-2010 |
| 20100123217 | SEMICONDUCTOR DEVICE - A semiconductor package includes a semiconductor chip having an integrated circuit, a functional element electrically coupled with the integrated circuit, and an array of contact elements connected with the integrated circuit and the functional element. The functional element is configured to protect the integrated circuit from transient voltage. | 05-20-2010 |
| 20100176488 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region. | 07-15-2010 |
| 20100181648 | LOCALIZED SYNTHESIS AND SELF-ASSEMBLY OF NANOSTRUCTURES - Systems and methods for local synthesis of silicon nanowires and carbon nanotubes, as well as electric field assisted self-assembly of silicon nanowires and carbon nanotubes, are described. By employing localized heating in the growth of the nanowires or nanotubes, the structures can be synthesized on a device in a room temperature chamber without the device being subjected to overall heating. The method is localized and selective, and provides for a suspended microstructure to achieve the thermal requirement for vapor deposition synthesis, while the remainder of the chip or substrate remains at room temperature. Furthermore, by employing electric field assisted self-assembly techniques according to the present invention, it is not necessary to grow the nanotubes and nanowires and separately connect them to a device. Instead, the present invention provides for self-assembly of the nanotubes and nanowires on the devices themselves, thus providing for nano- to micro-integration. | 07-22-2010 |
| 20100193908 | FUSION BONDING PROCESS AND STRUCTURE FOR FABRICATING SILICON-ON-INSULATION (SOI) SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 500 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the first semiconductor wafer through the about 500 angstrom thick oxide layer; providing a second semiconductor wafer having an oxide thereover; and, bonding the first semiconductor wafer oxide to the second semiconductor wafer oxide at an elevated temperature. | 08-05-2010 |
| 20100200951 | Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) - A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. | 08-12-2010 |
| 20100224962 | INTEGRATED CIRCUIT RESISTIVE DEVICES INCLUDING MULTIPLE INTERCONNECTED RESISTANCE LAYERS - A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common. | 09-09-2010 |
| 20100237467 | Interconnect Structures, Methods for Fabricating Interconnect Structures, and Design Structures for a Radiofrequency Integrated Circuit - Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature. | 09-23-2010 |
| 20100258909 | Longitudinal link trimming and method for increased link resistance and reliability - A resistor ( | 10-14-2010 |
| 20100289121 | Chip-Level Access Control via Radioisotope Doping - A mechanism for changing the doping profile of semiconductor devices over time using radioisotope dopants is disclosed. This mechanism can be used to activate or deactivate a device based on the change in doping profile over time. The disclosure contains several possible dopants for common semiconductor substrates and discusses several simple devices which could be used to actuate a circuit. The disclosure further discloses a means for determining the optimal doping profile to achieve a transition in bulk electrical properties of a semiconductor at a specific time. | 11-18-2010 |
| 20100308436 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device including a resistor which achieves reduction of a chip size and variations in resistance value, and a manufacturing method thereof. The semiconductor device includes: a resistor which is linearly formed above the silicon substrate, and made mainly of silicon; contact forming areas each of which (i) is formed in contact with one end of the resistor, and (ii) has a surface made of metal silicide; and contact plugs each of which electrically connects an associated one of the contact forming areas to a metal wire formed on the interlayer insulating film. An in-plane pattern of each of the contact forming areas is bent at least twice in a planar direction with respect to a linear direction of the resistor, so that a part of the contact forming area is formed in parallel with the resistor. | 12-09-2010 |
| 20110012231 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication. | 01-20-2011 |
| 20110042786 | INTEGRATION OF PASSIVE DEVICE STRUCTURES WITH METAL GATE LAYERS - A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions. | 02-24-2011 |
| 20110049676 | METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER - A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output. | 03-03-2011 |
| 20110062553 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - The semiconductor device ( | 03-17-2011 |
| 20110062554 | HIGH VOLTAGE FLOATING WELL IN A SILICON DIE - In one embodiment, a graded n-doped region surrounding a well, and a spiral resistor connected to the well and to a p-doped region surrounding the graded n-doped region. | 03-17-2011 |
| 20110084361 | SEMICONDUCTOR DEVICES HAVING RESISTORS - A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole. | 04-14-2011 |
| 20110089532 | INTEGRATED CIRCUIT WITH ESD STRUCTURE - An integrated circuit includes a semiconductor body of a first conductivity type. The semiconductor body includes a first semiconductor zone of a second conductivity type opposite the first conductivity type. The first semiconductor zone extends to a surface of the semiconductor body. A second semiconductor zone of the first conductivity type is embedded in the first semiconductor zone and extends as far as the surface. A third semiconductor zone of the second conductivity type at least partly projects from the first semiconductor zone along a lateral direction running parallel to the surface. A contact structure provides an electrical contact with the first and second semiconductor zones at the surface. The second semiconductor zone is arranged, along the lateral direction, between the part of the third semiconductor zone which projects from the first semiconductor zone and a part of the contact structure in contact with the first semiconductor zone. | 04-21-2011 |
| 20110115053 | RESISTOR IN AN INTEGRATED CIRCUIT - A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes. | 05-19-2011 |
| 20110163417 | METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE - A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging. | 07-07-2011 |
| 20110163418 | Mounting structures for integrated circuit modules - A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits. | 07-07-2011 |
| 20110180901 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device having a structure free from variations in resistance even when a stress is applied thereto; and a manufacturing method of the device. The semiconductor device has a metal resistor layer in a region between a passivation film and an uppermost level aluminum interconnect. This makes it possible to realize a high-precision resistor having few variations in resistance due to a mold stress that occurs in a packaging step or thereafter and therefore, makes it possible to form a high-precision analog circuit. | 07-28-2011 |
| 20110204481 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION - The present invention provides a semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween. | 08-25-2011 |
| 20110204482 | Method and Electronic Device for a Simplified Integration of High Precision Thinfilm Resistors - The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR. | 08-25-2011 |
| 20120056303 | Resistor Array And Semiconductor Device Including The Same - A resistor array includes a semiconductor substrate, a plurality of isolation regions, a plurality of dummy active regions and a plurality of unit resistors. The plurality of isolation regions are formed in the semiconductor substrate. The plurality of dummy active regions are formed in the semiconductor substrate between the plurality of isolation regions. The plurality of unit resistors are formed on the plurality of dummy active regions. | 03-08-2012 |
| 20120068308 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION METHOD - A semiconductor device includes a semiconductor substrate, a heat generating device, and a heat radiating part. The heat generating device is provided on the semiconductor substrate, and the heat radiating part is provided above the heat generating device. The heat radiating part is thermally coupled with the semiconductor substrate through at least one contact part. | 03-22-2012 |
| 20120126370 | THIN FILM RESISTORS AND METHODS OF MANUFACTURE - A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor. | 05-24-2012 |
| 20120146186 | THERMALLY CONTROLLED REFRACTORY METAL RESISTOR - A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors. | 06-14-2012 |
| 20120181663 | COMPACT THERMALLY CONTROLLED THIN FILM RESISTORS UTILIZING SUBSTRATE CONTACTS AND METHODS OF MANUFACTURE - A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner. | 07-19-2012 |
| 20120228740 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, an insulation film being embedded into the substrate and having multiple openings, multiple dummy diffusion layers formed in the substrate and located in the openings, multiple resistance elements being formed over the insulation film so as not to overlap the dummy diffusion layers in a plan view in a resistance element forming region and extending in a first direction, and multiple dummy resistance elements being formed over the insulation film and the dummy diffusion layers and extending in the first direction in the resistance element forming region, in which each of the dummy resistance elements overlaps at least two dummy diffusion layers aligning in a second direction perpendicular to the first direction in a plane horizontal to the substrate in a plan view. | 09-13-2012 |
| 20120280360 | Semiconductor Device and Method for Low Resistive Thin Film Resistor Interconnect - The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction. | 11-08-2012 |
| 20120292739 | INTEGRATED CIRCUIT HAVING SILICON RESISTOR AND METHOD OF FORMING THE SAME - An embodiment of the disclosure includes a method of forming an integrated circuit. A substrate having an active region and a passive region is provided. A plurality of trenches is formed in the passive region. A root mean square of a length and a width of each trench is less than 5 μm. An isolation material is deposited over the substrate to fill the plurality of trenches. The isolation material is planarized to form a plurality of isolation structures. A plurality of silicon gate stacks and at least one silicon resistor stack are formed on the substrate in the active region and on the plurality of isolation structures respectively. | 11-22-2012 |
| 20120292740 | HIGH VOLTAGE RESISTANCE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A HIGH VOLTAGE RESISTANCE SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate, a lateral semiconductor diode, a field insulation structure, and a polysilicon resistor. The diode is formed in a surface region of the semiconductor substrate, and includes a cathode electrode and an anode electrode. The field insulation structure is disposed between the cathode and anode electrodes. The polysilicon resistor is formed over the field insulation structure, and between the cathode and anode electrodes. The polysilicon resistor is electrically connected to the cathode electrode, and electrically insulated from the anode electrode. | 11-22-2012 |
| 20120292741 | INTERCONNECT STRUCTURES AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT - Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature. | 11-22-2012 |
| 20130049167 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device including a metal dummy pattern and a thin film resistor. In detail, a semiconductor device includes a semiconductor substrate, a thin film resistor, and a metal dummy pattern. The thin film resistor disposed over the semiconductor substrate and extending in a first direction relative to the semiconductor substrate. The metal dummy pattern disposed between the semiconductor substrate and the thin film resistor, the metal dummy pattern including a reflective pattern extending in the first direction semiconductor substrate and spatially corresponding to a periphery of the thin film resistor. | 02-28-2013 |
| 20130093054 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first insulation layer on or over a semiconductor substrate, metal patterns on or over the first insulation layer, a thin film resistor pattern disposed on or over the metal patterns, and an anti-reflection layer between the thin film resistor pattern and the metal patterns. | 04-18-2013 |
| 20130093055 | Semiconductor Device and Manufacturing Method of the Same - Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a metal head pattern on the first insulation layer, the metal head pattern including an inclined side surface, a thin film resistor pattern on the metal head pattern, a second insulation layer on the metal head pattern and the thin film resistor pattern, an upper metal line on the second insulation layer, a first via connecting the lower metal line to the upper metal line, and a second via connecting the metal head pattern to the upper metal line. | 04-18-2013 |
| 20130093056 | Semiconductor Device and Method of Manufacturing the Same - Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a second insulation layer on the first insulation layer, the second insulation layer including a metal head pattern, a thin film resistor pattern on the metal head pattern, a third insulation layer on the thin film resistor pattern, an upper metal line on the third insulation layer, a first via passing through the first, second, and third insulation layers to connect the lower metal line to the upper metal line, and a second via passing through the third insulation layer and the thin film resistor pattern to connect the metal head pattern to the upper metal line. | 04-18-2013 |
| 20130134558 | Self Aligned Silicide Device Fabrication - A method for fabricating a device includes forming a silicide layer on a substrate, forming a conductive layer over exposed portions of the substrate and the silicide layer, patterning and removing exposed portions of the conductive layer and the silicide layer with a first process, and patterning and removing exposed portions of the conductive layer with a second process. | 05-30-2013 |
| 20130147016 | Semiconductor Package Having Internal Shunt and Solder Stop Dimples - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 06-13-2013 |
| 20130154058 | HIGH SURFACE AREA FILLER FOR USE IN CONFORMAL COATING COMPOSITIONS - A high surface area filler, a conformal coating composition, and an apparatus. The high surface area filler comprises an amorphous silicon dioxide powder and a phosphine compound bonded to the amorphous silicon dioxide powder. The conformal coating composition comprises a conformal coating and the high surface area filler. The apparatus includes an electronic component mounted on a substrate and metal conductors electrically connecting the electronic component. The conformal coating composition overlies the metal conductors and comprises a conformal coating and the high surface area filler. Accordingly, the conformal coating composition is able to protect the metal conductors from corrosion caused by sulfur components (e.g., elemental sulfur, hydrogen sulfide, and/or sulfur oxides) in the air. | 06-20-2013 |
| 20130168815 | TEMPERATURE SWITCH WITH RESISTIVE SENSOR - The present disclosure is directed to a device and a method for forming a precision temperature sensor switch with a Wheatstone bridge configuration of four resistors and a comparator. When the temperature sensor detects a temperature above a threshold, the switch will change states. The four resistors in the Wheatstone bridge have the same resistance, with three of the resistors having a low temperature coefficient of resistance and the fourth resistor having a high temperature coefficient of resistance. As the temperature increases, the resistance of the fourth resistor will change. The change in resistance of the fourth resistor will change a voltage across the bridge. The voltage across the bridge is coupled to the comparator and compares the voltage with the threshold temperature, such that when the threshold temperature is exceeded, the comparator switches the output off. | 07-04-2013 |
| 20130168816 | RESISTOR AND FABRICATION METHOD THEREOF - The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler. | 07-04-2013 |
| 20130207234 | SEMICONDUCTOR APPARATUS, SIGNAL TRANSMISSION SYSTEM AND SIGNAL TRANSMISSION METHOD - A slew rate of a signal transmitted between a semiconductor device having a small load capacitance and a semiconductor device having a large load capacitance is improved. When a signal is transmitted to the semiconductor device (for example, a memory device) having the large load capacitance, pre-emphasis is performed, and when a signal is transmitted to the semiconductor device (for example, a memory controller) having the small load capacitance, pre-emphasis is not performed or is slightly performed. By this, when the signal is transmitted to the memory device, blunting in signal rising due to the load capacitance is suppressed, and when the signal is transmitted to the memory controller, ringing due to the reflection of the signal is suppressed, and the slew rate of the data transmission is improved. | 08-15-2013 |
| 20130221487 | METHOD OF FORMING RESISTOR OF SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE THEREOF - A resistor in a semiconductor memory device is formed by the steps of, inter alia: forming a first helical resistor extending from a first point toward a center in a clockwise or counterclockwise direction, forming a second helical resistor extending from the center to a second point in an opposite direction, wherein the first and second helical resistors are connected to each other at the center, and wherein the first and second helical resistors do not overlap. | 08-29-2013 |
| 20130234292 | THIN FILM RESISTOR STRUCTURE - A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD. | 09-12-2013 |
| 20130241037 | Semiconductor Devices Having Metal Oxide Patterns - Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided. | 09-19-2013 |
| 20130249056 | METHOD AND ELECTRONIC DEVICE FOR A SIMPLIFIED INTEGRATION OF HIGH PRECISION THINFILM RESISTORS - The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR. | 09-26-2013 |
| 20130270678 | INTEGRATED CIRCUIT INCLUDING THERMAL GATE, RELATED METHOD AND DESIGN STRUCTURE - An integrated circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; an insulation layer over the substrate; a resistor over the insulation layer; a thermal gate over the resistor; and a heat sink connected to the thermal gate via a substrate contact, the heat sink adapted to receive thermal energy from the resistor via the thermal gate. | 10-17-2013 |
| 20130334662 | Current Sensing Using a Metal-on-Passivation Layer on an Integrated Circuit Die - A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a flip-chip semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are electrically connected to a first leadframe portion and a second leadframe portion of the semiconductor package where the first leadframe portion and the second leadframe portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor. | 12-19-2013 |
| 20130334663 | METAL-ON-PASSIVATION RESISTOR FOR CURRENT SENSING IN A CHIP-SCALE PACKAGE - A current sense resistor integrated with an integrated circuit die housed in a chip-scale semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are to be electrically connected to a first conductive electrode and a second conductive electrode external to the chip-scale semiconductor package where the first conductive electrode and the second conductive electrode are physically separated from each other by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second conductive electrodes. In some embodiments, a semiconductor device including an integrated circuit die housed in a chip-scale semiconductor package includes a current sense resistor formed in a metal layer formed over a passivation layer of the integrated circuit die. | 12-19-2013 |
| 20130341760 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second wells formed side by side as impurity diffusion regions of a first conductive type in a semiconductor substrate, below an intermediate dielectric film that covers a major surface of the substrate. A conductive layer formed above the intermediate dielectric film is held at a potential. A first resistive layer is formed on the intermediate dielectric film and is electrically connected to the first well. A second resistive layer is formed on the intermediate dielectric film and is electrically connected to the second well. The first resistive layer and first well form a first resistance element. The second resistive layer and second well form a second resistance element. | 12-26-2013 |
| 20140001599 | METHOD FOR FORMING THIN FILM RESISTOR AND TERMINAL BOND PAD SIMULTANEOUSLY | 01-02-2014 |
| 20140015103 | Large Bit-Per-Cell Three-Dimensional Mask-Programmable Read-Only Memory - A large bit-per-cell three-dimensional mask-programmable read-only memory (3D-MPROM | 01-16-2014 |
| 20140048908 | SEMICONDUCTOR SUBSTRATE ASSEMBLY - A semiconductor substrate assembly is proposed. The semiconductor interposer comprises a substrate having a first surface and a second surface opposite to the first surface, a first conductive pad, a second conductive pad and a conductive pillar. The first conductive pad is formed at a predetermined location of the first surface of the substrate. The second conductive pad is formed at a predetermined location of the second surface of the substrate as compared with the position of the first conductive pad. The conductive pillar is formed in the substrate and contacts with one of the first conductive pad and the second conductive pad. | 02-20-2014 |
| 20140054746 | RESISTANCE STRUCTURE, INTEGRATED CIRCUIT, AND METHOD OF FABRICATING RESISTANCE STRUCTURE - A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer. | 02-27-2014 |
| 20140159203 | Substrate Pad Structure - A structure comprises a first pad protruding over a top surface of a package substrate, wherein the first pad is of a first elongated shape, a second pad embedded in the package substrate, wherein the second pad is of a second elongated shape and a via coupled between the first pad and the second pad. | 06-12-2014 |
| 20140159204 | ARRAY SUBSTRATE, FABRICATION METHOD THEREOF AND DISPLAY DEVICE - Embodiments of the present invention provide an array substrate, a fabrication method thereof and a display device. The array substrate comprises a driver IC and pixel units, wherein each port of the driver IC is connected to a plurality of pixel units through a connecting structure, each connecting structure comprises a connecting line connected between a port of the driver IC and a plurality of pixel units, at least some of the connecting structures also comprise resistance regulating units for changing the total resistance values of the connecting structures, and the resistance regulating units are connected in series with the respective connecting lines; and/or the resistance regulating units are connected in parallel with parts of the respective connecting lines, so that the differences among resistance values of connecting structures can be reduced, and in turn the display effect of a display panel is improved. | 06-12-2014 |
| 20140197520 | RESISTOR AND RESISTOR FABRICATION FOR SEMICONDUCTOR DEVICES - In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor. | 07-17-2014 |
| 20140203405 | METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE - A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging. | 07-24-2014 |
| 20140217550 | METAL FILM RESISTOR STRUCTURE AND MANUFACTURING METHOD - A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect. | 08-07-2014 |
| 20140231960 | POLYSILICON RESISTOR FORMATION - Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region). | 08-21-2014 |
| 20140239449 | THREE PRECISION RESISTORS OF DIFFERENT SHEET RESISTANCE AT SAME LEVEL - An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks. | 08-28-2014 |
| 20140264752 | DUAL THREE-DIMENSIONAL (3D) RESISTOR AND METHODS OF FORMING - Various embodiments include dual three-dimensional (3D) resistor structures and methods of forming such structures. In some embodiments, a dual 3D resistor structure includes: a dielectric layer having a first set of trenches extending in a first direction through the dielectric layer; and a second set of trenches overlayed on the first set of trenches, the second set of trenches extending in a second direction through the dielectric layer, the second set of trenches and the first set of trenches forming at least one dual 3D trench; and a resistor material overlying the dielectric layer and at least partially filling the at least one dual 3D trench along the first direction and the second direction. | 09-18-2014 |
| 20140264753 | Novel Structure of W-Resistor - A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal. | 09-18-2014 |
| 20140361405 | ARRAY TYPE CHIP RESISTOR AND METHOD OF MANUFACTURING THEREOF - There is provided an array type chip resistor including: a chip body, four pairs of lower electrodes disposed on both sides of a lower surface of the chip body and formed so as to be extended to edges of the chip body, side electrodes formed so that the lower electrodes are extended to sides of the chip body, and a resistor interposed between the lower electrodes on the lower surface of the chip body and electrically connected to the lower electrode through a contact portion, wherein when a width of the side electrode is defined as d1, a distance between adjacent side electrodes is defined as d2, and a height of the side electrode is defined as h, in the case in which d1/d2 is 0.5 to 1.5, a value of h is 4,300/d1 μm or above and is 0.24d2+87.26 μm or less. | 12-11-2014 |
| 20150014815 | Semiconductor Device and a Method for Manufacturing a Semiconductor Device Having a Semi-Insulating Region - A semiconductor device and a method for forming a semiconductor device are provided. The semiconductor device includes a semiconductor body including a diode-structure with a pn-junction, and an edge-termination structure arranged in a peripheral area of the semiconductor body. The edge-termination structure includes an insulating region partially arranged in the semiconductor body adjacent the pn-junction and a semi-insulating region arranged on the insulating region and spaced apart from the semiconductor body. The semi-insulating region forms a resistor connected in parallel with the diode-structure. | 01-15-2015 |
| 20150035120 | Wafer Scale Package for High Power Devices - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages arc mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 02-05-2015 |
| 20150115410 | SEMICONDUCTOR DEVICE - A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer. | 04-30-2015 |
| 20150303107 | SEMICONDUCTOR DEVICE, RESISTOR AND MANUFACTURING METHOD OF THE SAME - A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer. | 10-22-2015 |
| 20150303143 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device including an oscillator and a manufacturing method thereof, in which cost is low and design flexibility is high. The semiconductor device includes a wiring structure region and an oscillator region. The semiconductor device also includes, in the oscillator region, a metal resistive element as the same layer as a conducting film over uppermost metal wiring in the wiring structure region. | 10-22-2015 |
| 20150364398 | MOL RESISTOR WITH METAL GRID HEAT SHIELD - An semiconductor structure, method of fabrication therefor, and design structure therefor is provided. A thermal grid is formed over at least a portion of a substrate. An insulating layer is formed over at least a portion of the thermal grid. A resistor is formed over at least a portion of the insulating layer. A buried interconnect is connected to the thermal grid via at least one contact. The buried interconnect is adapted to receive thermal energy from the thermal grid via the at least one contact. | 12-17-2015 |
| 20160181239 | MULTI-LAYERED INTEGRATED CIRCUIT WITH SELECTIVE TEMPERATURE COEFFICIENT OF RESISTANCE | 06-23-2016 |
| 20160204103 | SEMICONDUCTOR DEVICE STRUCTURE | 07-14-2016 |
| 20160254344 | LOW TEMPERATURE FABRICATION OF LATERAL THIN FILM VARISTOR | 09-01-2016 |
| 20180026091 | Resistor Structure | 01-25-2018 |
| 20190148293 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME | 05-16-2019 |
