| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257535000 | Both terminals of capacitor isolated from substrate | 17 |
| 20080203531 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved. | 08-28-2008 |
| 20080217739 | Semiconductor packaging substrate structure with capacitor embedded therein - The present invention relates to a semiconductor packaging substrate structure with a capacitor embedded therein, which includes an inner circuit board, a patterned buffer layer, a high dielectric material layer, and a patterned metal layer. The buffer layer is disposed on at least one surface of the inner circuit board to expose the inner electrode layer of the internal board. The high dielectric material layer is located on the buffer layer and the inner electrode layer. The metal layer is placed on the high dielectric material layer including an outer circuit layer capable of electrical connection to the inner circuit layer, and an outer electrode layer corresponding to the inner electrode layer to form a capacitor. Owing to the assistance of the buffer layer, the structure can enhance the transmission and the quality of the products. | 09-11-2008 |
| 20080258262 | SEMICONDUCTOR DEVICE WITH IMPROVED PADS - A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above the semiconductor substrate and connected to the multilevel wiring structure. The pad electrode structure includes pad wiring patterns and pad via conductors interconnecting the pad wiring patterns, the uppermost pad wiring pattern includes a pad pattern and a sealing pattern surrounding the pad pattern in a loop shape. Another pad wiring pattern has continuous extended pad pattern of a size overlapping the sealing pattern. The pad via conductors include a plurality of columnar via conductors disposed in register with the pad pattern and a loop-shaped wall portion disposed in register with the sealing pattern. | 10-23-2008 |
| 20090014835 | Semiconductor device including MIM element and method of manufacturing the same - A semiconductor device includes a first wiring layer which is provided above a semiconductor substrate and includes a first insulating film and a wiring buried in the first insulating film, a second insulating film provided above the first wiring layer, a third insulating film provided on the second insulating film, and a capacitor element provided on the third insulating film. The wiring includes an upper surface having a protruding portion. The capacitor element includes a lower electrode provided on the third insulating film, a capacitor insulating film provided on the lower electrode, and an upper electrode provided on the capacitor insulating film. | 01-15-2009 |
| 20090146257 | Capacitor and semiconductor device including the same - A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode. | 06-11-2009 |
| 20090256239 | Capacitor, Chip Comprising the Capacitor, and Method for Producing the Capacitor - A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of a first capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating layer is arranged between each of the plurality of the trenches and the doped area for electrically insulating the trenches from the doped area. At least one substrate contact structure electrically connects the doped area, wherein the doped area comprises first open areas and at least one second open area arranged between neighboring trenches of the plurality of trenches, wherein the at least one open area is arranged below the at least one substrate contact. A shortest first distance between neighboring trenches is separated by the first open areas and is shorter than a shortest second distance between neighboring trenches separated by the at least one second open area. | 10-15-2009 |
| 20090267187 | METHOD FOR MANUFACTURING AN ENERGY STORAGE DEVICE AND STRUCTURE THEREFOR - An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than the surface area of the insulating material and the surface area of the insulating material is greater than the surface area of the top electrode. The top electrode and the insulating layer have edges that are laterally within and spaced apart from edges of the bottom electrode. A protective layer covers the top electrode, the edges of the top electrode, and the portions of the insulating layer that are uncovered by the top electrode. The protective layer serves as an etch mask during the formation of the bottom electrode. | 10-29-2009 |
| 20090294907 | SEMICONDUCTOR COMPONENT WITH MIM CAPACITOR - A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode. | 12-03-2009 |
| 20100052099 | CAPACITOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices. | 03-04-2010 |
| 20120104552 | Capacitors in Integrated Circuits and Methods of Fabrication Thereof - In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line. | 05-03-2012 |
| 20130093053 | TRENCH TYPE PIP CAPACITOR, POWER INTEGRATED CIRCUIT DEVICE USING THE CAPACITOR, AND METHOD OF MANUFACTURING THE POWER INTEGRATED CIRCUIT DEVICE - A trench-type PIP capacitor having a small step at the end part of the capacitor without increasing manufacturing cost, and a power integrated circuit device that uses such a trench-type PIP capacitor are disclosed. A method of manufacturing the power integrated circuit device also is disclosed. A trench-type PIP capacitor has a construction, in the surface region of a semiconductor substrate, comprising an isolating insulation layer formed on an inner wall of a trench and a first polysilicon that fills the trench through the isolating insulation layer and becomes a lower electrode. Since this construction has a small step formed at the end region of the capacitor, a metal layer for wiring does not need to be made excessively thick, allowing a fine structure of the metal layer. Therefore, the power IC provided with such a trench-type PIP capacitor can have a fine structure. | 04-18-2013 |
| 20140117501 | DIFFERENTIAL MOSCAP DEVICE - A differential MOS capacitor structure includes two capacitor sections coupled to different gates and operating using different signals. The respective signals may be 180° out of phase. The capacitor sections of the differential capacitor each include two or more upper capacitor plates disposed over a single common lower capacitor plate which serves as a common node thereby preventing parasitic capacitance. The upper capacitor plates of a first capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates of a second capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates are formed of a plurality of stacked conductive layers in some embodiments. | 05-01-2014 |
| 20140145307 | Seal Ring Structure with Metal-Insulator-Metal Capacitor - A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring. | 05-29-2014 |
| 20150091135 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating layer formed on a substrate, and a capacitor including first and second electrodes formed in the insulating layer, wherein a lower surface of the first electrode is formed to have a greater depth than a lower surface of the second electrode in the insulating layer. | 04-02-2015 |
| 20150102464 | CAPACITOR WITH HOLE STRUCTURE AND MANUFACTURING METHOD THEREOF - Disclosed herein are a capacitor with a hole structure and a manufacturing method thereof. A capacitor with a hole structure includes: a substrate layer having a plurality of through-holes formed therein; a lower electrode layer including a first conductive layer having a low specific resistance and a second conductive layer having a specific resistance higher than that of the first conductive layer, the first conductive layer being formed on an inner wall of the through-hole and the second conducive layer being formed on the first conductive layer; a thin film dielectric layer formed on the lower electrode layer; and an upper electrode layer including a third conductive layer and a fourth conductive layer having a specific resistance lower than that of the third conductive layer, the third conductive layer being formed on the thin film dielectric layer and the fourth conductive layer being formed on the third conductive layer. | 04-16-2015 |
| 20150115409 | SEMICONDUCTOR ARRANGEMENT HAVING CAPACITOR SEPARATED FROM ACTIVE REGION - A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region. | 04-30-2015 |
| 20160197071 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME | 07-07-2016 |
