| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257533000 | Combined with resistor to form RC filter structure | 21 |
| 20080258261 | Split Chip - This Invention is a design method and a system for a miniaturized silicon circuit whereby the circuit is split into two pieces. This process is known to the Inventor as a bifurcated circuit or disintegrated circuit and is titled the “Split Chip” by the Inventor. The Split Chip contemplates an RFID enabled consumer oriented tracking system which protects consumer privacy. The goal of this Invention is accomplished by splitting the RFID transponder circuit into a retained piece and a detached piece. Each piece is contained on a separate wafer of silicon. The two pieces are electrically connected by a fine piece of conductive material. Each piece is dependent upon the other in order to disgorge data. The electrical connection between the two pieces can be severed by the consumer. This is accomplished by tearing the fine piece of conductive material at a designated spot on the substrate. The result of the tear is that the Split Chip is now moribund. Upon the circumstance of a return or refund consumer item the original data can be recovered through a laser guidance system which connects the retained piece and its alpha numeric identifier to a back end host computer administration network. | 10-23-2008 |
| 20090236692 | RC FILTERING DEVICE HAVING AIR GAP CONSTRUCTION FOR OVER VOLTAGE PROTECTION - The present invention relates to a RC filtering device, consists of: a lower substrate, a first intermediate substrate, a second intermediate substrate and an upper substrate. On top surface of the lower substrate is a cross form electrode layer. At both ends of the electrode layer in one direction forms a pair of air gaps to function as over voltage protection. The first intermediate substrate is formed above the lower substrate also has a pair of grooves corresponding to said air gaps, and on the top surface of the second intermediate layer, there is a transmission wire. The said transmission wire is formed with metallic layer at its both ends and the metallic oxide layer made with electrical resistance, this transmission wire and the electrode layer on the lower substrate form an RC filtering device. | 09-24-2009 |
| 20090267186 | SEMICONDUCTOR STRUCTURE INCLUDING TRENCH CAPACITOR AND TRENCH RESISTOR - A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material at a periphery of the resistor trench and a resistor material at a central portion of the resistor trench. | 10-29-2009 |
| 20090273059 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING POLYSILICON MEMBERS - A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix. | 11-05-2009 |
| 20100117198 | INTEGRATED PROCESS FOR THIN FILM RESISTORS WITH SILICIDES - The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed. | 05-13-2010 |
| 20110254131 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device including a digital circuit region in which a digital circuit is formed, and an analog circuit region in which an analog circuit is formed, the analog circuit region is separated into an active element region in which an active element of the analog circuit is formed, and a resistive and capacitive element region in which a resistor or a capacitor of the analog circuit is formed, the resistive and capacitive element region is arranged in a region adjacent to the digital circuit region, and the active element region is arranged in a region separated from the digital circuit region. | 10-20-2011 |
| 20120012982 | CAPACITORS AND METHODS OF FORMING - Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate. A top contact may be formed laterally spaced from the trenched area by patterning laterally extended portions of one or more of the dielectric, polysilicon and top metal contact layers. | 01-19-2012 |
| 20130093052 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A RESISTOR AND METHOD OF FORMING THE SAME - The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures. | 04-18-2013 |
| 20130292798 | DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - A resistor and capacitor are provided in respective shallow trench isolation structures. The method includes forming a first and second trench in a substrate and forming a first insulator layer within the first and second trench. The method includes forming a first electrode material within the first and second trench, on the first insulator layer, and forming a second insulator layer within the first and second trench and on the first electrode material. The method includes forming a second electrode material within the first and second trench, on the second insulator layer. The second electrode material pinches off the second trench. The method includes removing a portion of the second electrode material and the second insulator layer at a bottom portion of the first trench, and filling in the first trench with additional second electrode material. The additional second electrode material is in electrical contact with the first electrode material. | 11-07-2013 |
| 20130341759 | Integration of Precision MIM Capacitor and Precision Thin Film Resistor - An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate. | 12-26-2013 |
| 20140124893 | Varactor Diode, Electrical Device and Method for Manufacturing Same - An electrical device includes a semiconductor material. The semiconductor material includes a first region of the semiconductor material having a first conductivity type, a second region of the semiconductor material having a second conductivity type complementary to the first conductivity type and an intermediate region of the semiconductor material between the first region and the second region. The first and second regions lie next to each other the intermediate region so as to form a diode structure. A shape of the intermediate region tapers from the first region to the second region. | 05-08-2014 |
| 20140239447 | METHODS AND APPARATUS RELATED TO CAPACITANCE REDUCTION OF A SIGNAL PORT - In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type. The region of the first conductivity type can be configured to be coupled to a first node having a first voltage, and the region of the second conductivity type can be configured to be coupled to a second node having a second voltage different than the first voltage. | 08-28-2014 |
| 20140264750 | Resistor and Metal-Insulator-Metal Capacitor Structure and Method - A passive circuit device incorporating a resistor and a capacitor and a method of forming the circuit device are disclosed. In an exemplary embodiment, the circuit device comprises a substrate and a passive device disposed on the substrate. The passive device includes a bottom plate disposed over the substrate, a top plate disposed over the bottom plate, a spacing dielectric disposed between the bottom plate and the top plate, a first contact and a second contact electrically coupled to the top plate, and a third contact electrically coupled to the bottom plate. The passive device is configured to provide a target capacitance and a first target resistance. The passive device may also include a second top plate disposed over the bottom plate and configured to provide a second target resistance, such that the second target resistance is different from the first target resistance. | 09-18-2014 |
| 20140264751 | METAL-INSULATOR-METAL (MIM) CAPACITOR - In one embodiment, a chip comprises a capacitor and a resistor. The capacitor comprises a first capacitor terminal, a second capacitor terminal, and a dielectric layer between the first and second capacitor terminals. The second capacitor terminal and the resistor are both fabricated from a resistor metal layer. | 09-18-2014 |
| 20150084161 | MIXED MODE RC CLAMPS - A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant. | 03-26-2015 |
| 20150108607 | INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above. | 04-23-2015 |
| 20150318340 | INTEGRATED THINFILM RESISTOR AND MIM CAPACITOR WITH A LOW SERIAL RESISTANCE - An electronic device comprising a semiconductor structure having a back end capacitor and a back end thin film resistor and a method of manufacturing the same. The semiconductor structure includes a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. The bottom plate and the resistor body are laterally spaced apart portions of the same thin film layer. The bottom plate further includes a conductive layer overlying the thin film layer. A second dielectric layer is disposed on the conductive layer of the bottom plate of the capacitor. A top plate of the capacitor is disposed on the second dielectric layer. | 11-05-2015 |
| 20150348908 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device ( | 12-03-2015 |
| 20150357400 | SEMICONDUCTOR DEVICE - A semiconductor device having a capacitor, which provides enhanced reliability. A wiring and a capacitor are formed over an interlayer insulating film overlying a semiconductor substrate and another interlayer insulating film is formed over the interlayer insulating film so as to cover the wiring and capacitor. The capacitor includes a lower electrode overlying the interlayer insulating film, an upper electrode overlying the interlayer insulating film to cover the lower electrode at least partially, and a capacitive insulating film interposed between the lower and upper electrodes. The upper electrode and the wiring are formed from a conductive film pattern in the same layer. A plug is located under, and electrically coupled to, the lower electrode and another plug is located over the upper electrode's portion not overlapping the lower electrode in plan view and electrically coupled to the upper electrode. Another plug is located over, and electrically coupled to, the wiring. | 12-10-2015 |
| 20160111365 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line. | 04-21-2016 |
| 20160141283 | INTEGRATED THINFILM RESISTOR AND MIM CAPACITOR WITH A LOW SERIAL RESISTANCE - An electronic device comprising a semiconductor structure having a back end capacitor and a back end thin film resistor and a method of manufacturing the same. The semiconductor structure includes a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. The bottom plate and the resistor body are laterally spaced apart portions of the same thin film layer. The bottom plate further includes a conductive layer overlying the thin film layer. A second dielectric layer is disposed on the conductive layer of the bottom plate of the capacitor. A top plate of the capacitor is disposed on the second dielectric layer. | 05-19-2016 |
