| Entries |
| Document | Title | Date |
|---|
| 20080203526 | Semiconductor device equipped with thin-film circuit elements - A plurality of wirings, column-shaped electrodes, sealing films, and soldering balls, are provided on a third upper-layer insulating film formed on a silicon substrate. A spirally configured thin-film inductive element is disposed beneath the bottom surface of a ground insulating film formed beneath the silicon substrate. The inner and outer end portions of the thin-film inductive element are respectively connected to the wirings via a vertical conductor disposed in the silicon substrate. In this case, it is not required to secure a certain area otherwise needed for the formation of the thin-film inductive element over the surface of the third upper-layer insulating film that accommodates the wirings. Hence, even when the thin-film inductive element has been provided, it is possible to evade a feasibility to incur restraint on the distribution of the wirings formed over the surface of the third upper-layer insulating film. | 08-28-2008 |
| 20080203527 | Semiconductor device having gate electrode connection to wiring layer - A semiconductor device includes a semiconductor substrate having an electrode formed above a surface thereof; a first insulating resin layer that is provided over the semiconductor substrate and has a first opening defined at a position corresponding to the electrode; a first wiring layer that is provided on the first insulating resin layer and is connected to the electrode through the first opening; a second insulating resin layer provided over the first insulating resin layer and the first wiring layer, the second insulating resin layer having a second opening that is defined at a position different from the position of the first opening in a direction of the surface of the semiconductor substrate; and a second wiring layer that is provided on the second insulating resin layer and is connected to the first wiring layer through the second opening, wherein the second wiring layer includes an induction element, and a sum of a thickness of the first insulating resin layer and a thickness of the second insulating resin layer is not less than 5 μm and not more than 60 μm. | 08-28-2008 |
| 20080224262 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having a high-frequency interconnect, first dummy conductor patterns, an interconnect, and second dummy conductor patterns. The first dummy conductor patterns are arranged in the vicinity of the high-frequency interconnect, and the second dummy conductor patterns are arranged in the vicinity of the interconnect. The minimum value of distance between the high-frequency interconnect and the first dummy conductor patterns is larger than the minimum value of distance between the interconnect and the second dummy conductor patterns. | 09-18-2008 |
| 20080237789 | INTEGRATED CIRCUIT STUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM - Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M | 10-02-2008 |
| 20080237790 | Composite semiconductor device - The electrode of a thin-type capacitor is connected to the rear surface of a p-type semiconductor substrate which is brought to a ground potential, by a conductive DAF (Die Attach Film) or by a conductive adhesive, and the electrodes of the front surface of the p-type semiconductor substrate are respectively connected with and stacked on the terminals of a thin-type inductor by bumps, whereby manufacturing costs can be reduced while the occurrence of noise can be suppressed and packaging area can be made small. | 10-02-2008 |
| 20080246114 | INTEGRATED PASSIVE DEVICE WITH A HIGH RESISTIVITY SUBSTRATE AND METHOD FOR FORMING THE SAME - According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) ( | 10-09-2008 |
| 20080265367 | Magnetically Alignable Integrated Circuit Device - An integrated circuit device includes a semiconductor chip having an active surface with a plurality of chip contact pads, a rewiring substrate and an electrically conductive inductor coil for magnetically aligning the semiconductor chip with the rewiring substrate. | 10-30-2008 |
| 20080272457 | Formation Of Dummy Features And Inductors In Semiconductor Fabrication - A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions. | 11-06-2008 |
| 20080272458 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer. | 11-06-2008 |
| 20080277758 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate that has an integrated circuit and an electrode, the electrode being electrically coupled to the integrated circuit; a resin layer that is formed on the semiconductor substrate, the resin layer having an upper surface and a lower surface, the upper surface and the lower surface opposing each other, the lower surface facing the substrate; and a spiral inductor that is formed on the upper surface of the resin layer with a spiral wiring line, the spiral inductor being electrically coupled to the electrode. The wiring line has both ends in a width direction intersecting an axial line spirally extending and a mid-portion between the both ends. At least a part of the mid-portion makes contact with the upper surface of the resin layer, and at least the both ends are positioned apart from the upper surface of the resin layer. | 11-13-2008 |
| 20080277759 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer. | 11-13-2008 |
| 20080290457 | BONDING PAD STRUCTURE DISPOSED IN SEMICONDUCTOR DEVICE AND RELATED METHOD - The present invention discloses a bonding pad structure disposed in a semiconductor device and a method for forming the bonding pad structure. The semiconductor device includes a substrate. The bonding pad structure includes a connection structure and an induction structure. The connection structure allows for a direct connection with a bonding wire. The induction structure is coupled with the connection structure and lowers an effective capacitance between the bonding wire and the substrate. | 11-27-2008 |
| 20080290458 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad. | 11-27-2008 |
| 20080303117 | Integrated circuit with multi-stage matching circuit - An integrated circuit with a multi-stage matching circuit with an inductive conductive structures with a first end and a second end in the integrated circuit and a capacitor structure in the integrated circuit connected to a tap between the ends of the inductive conductive structure between the inductive conductive structure and a reference potential. | 12-11-2008 |
| 20080315356 | Semiconductor die with backside passive device integration - According to an exemplary embodiment, a semiconductor die includes a backside surface opposite an active surface. The active surface includes at least one active device. The semiconductor die includes at least one passive device situated on the backside surface. The semiconductor die further includes an interconnect region situated over the active surface. The semiconductor die further includes at least one through-wafer via, where the at least one through-wafer via electrically connects the at least one passive device to the interconnect region. The interconnect region can include a number of solder bump pads or a number of bond pads. | 12-25-2008 |
| 20090001509 | CIRCUIT SYSTEM WITH CIRCUIT ELEMENT - A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode. | 01-01-2009 |
| 20090001510 | AIR GAP IN INTEGRATED CIRCUIT INDUCTOR FABRICATION - In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via. | 01-01-2009 |
| 20090001511 | High performance system-on-chip using post passivation process - The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface. | 01-01-2009 |
| 20090014830 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including at least one of the following steps: Forming an insulating film having at least one trench on and/or over a semiconductor substrate. Forming a metal film on and/or over a surface of an insulating film, including inside the trench. Forming a metal seed layer on and/or over the metal film inside the trench. Forming a metal plating layer on and/or over the metal seed layer to fill the trench. | 01-15-2009 |
| 20090051004 | Surface Mount Components Joined Between a Package Substrate and a Printed Circuit Board - A microelectronic package and a method of forming the package. The package includes a first level package mounted to a carrier. The first level package includes a package substrate having a die side and a carrier side; and a microelectronic die mounted on the package substrate at the die side thereof. The carrier has a substrate side, and the first level package is mounted on the carrier at the substrate side thereof. A rigid body is attached to the carrier side of the substrate at an attachment location of the substrate and to the substrate side of the carrier at an attachment location of the carrier, the attachment location of the carrier being electrically unconnected, the rigid body being configured and disposed to provide structural support between the substrate and the carrier. | 02-26-2009 |
| 20090051005 | METHOD OF FABRICATING INDUCTOR IN SEMICONDUCTOR DEVICE - A method of fabricating an inductor in a semiconductor device is disclosed. Embodiments include forming a first metal wire in a trench formed by etching a layer of a semiconductor substrate, forming an insulating layer over the substrate including the first metal wire, forming a via hole by etching the insulating layer to expose a portion of the first metal wire, forming a plated layer by electroplating to partially fill the via hole with the plated layer, and forming a second metal wire over the insulating layer including the plated layer. | 02-26-2009 |
| 20090057822 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a leadframe, a discrete passive circuit element, and an active circuit element. The discrete passive circuit element such as, for example, a discrete ferrite core inductor, is mounted either laterally or vertically adjacent to the leadframe. A semiconductor chip is attached to the discrete ferrite core inductor. Bond pads on the semiconductor chip may be electrically coupled to leads from the leadframe or to the discrete ferrite core inductor by wire bonds. The leadframe, discrete ferrite core inductor, semiconductor chip, and wire bonds are protected by an encapsulant such as a mold compound. Other passive circuit elements may be mounted to the discrete ferrite core inductor before encapsulation in the mold compound. | 03-05-2009 |
| 20090057823 | Semiconductor Structure with a Discontinuous Material Density for Reducing Eddy Currents - A semiconductor structure includes an inductor; and a semiconductor substrate underlying the inductor, having a discontinuous material density across a plane underneath and in parallel with the inductor, thereby reducing eddy currents induced by an electrical current flowing through the inductor. | 03-05-2009 |
| 20090057824 | INDUCTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An inductor of a semiconductor device and a method for manufacturing the same are disclosed. The inductor has a spiral structure, and includes a semiconductor substrate formed with a sub-structure. At least one metal line layer may be formed over the semiconductor substrate. At least one inductor line layer may be formed over the metal line layer. A space layer may be formed between the inductor line layer and the semiconductor substrate. | 03-05-2009 |
| 20090057825 | Semiconductor Device and a Method for Fabricating the Same - A semiconductor device including an inductor and a fabricating method thereof are provided. The semiconductor device can include a connection wiring provided on a semiconductor substrate; a metal wiring provided on an insulating layer in a spiral shape and electrically connected to the connection wiring; and holes provided in the insulating layer and between the metal wiring and the silicon substrate. | 03-05-2009 |
| 20090085155 | METHOD AND APPARATUS FOR PACKAGE-TO-BOARD IMPEDANCE MATCHING FOR HIGH SPEED INTEGRATED CIRCUITS - A method of package-to-board impedance matching for high speed integrated circuits (ICs). Multiple solder balls are attached to an IC package. The IC package includes multiple conductive interconnect layers, where one of the conductive interconnect layers is coupled to one or more of the multiple solder balls. Multiple vias are coupled between different conductive interconnect layers. An inductive element is coupled between an interconnect lead and a via land in the conductive interconnect layer within the IC package. The physical layout dimensions of the inductive element are configured such that the inductive element provides an inductance value that is sufficient to offset a parasitic capacitance provided by the conductive interconnect layers and the solder balls. The inductive element may be a bond wire, an inductive interconnect, or a spiral interconnect. | 04-02-2009 |
| 20090090995 | On-chip inductors with through-silicon-via fence for Q improvement - A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground, wherein the plurality of through-silicon-vias provide isolations for the one or more on-chip inductors. | 04-09-2009 |
| 20090096061 | Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure - A semiconductor device includes, a metal wiring, which functions as an inductor or transformer, formed on a first portion of a semiconductor substrate, a plurality of first dummy layers formed in a first density on the first portion of the semiconductor substrate, a plurality of second dummy layers formed in a second density on a second portion of the semiconductor substrate, the second portion surrounding the first portion, and a plurality of third dummy layers formed in a third density higher than the first and second densities on a third portion of the semiconductor substrate, the third portion surrounding the second portion. | 04-16-2009 |
| 20090115022 | SEMICONDUCTOR DEVICE - A semiconductor device | 05-07-2009 |
| 20090127654 | Fully Differential, High Q, On-Chip, Impedance Matching Section - An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors. | 05-21-2009 |
| 20090134489 | SYSTEM INCLUDING AN INTER-CHIP COMMUNICATION SYSTEM - A system including an inter-chip communication system is disclosed. One embodiment includes a base chip including a base chip transceiver network. At least one chip is stacked on the base chip, the at least one stacked chip including a substrate, a cavity formed in the substrate, a first surface, and a stacked chip transceiver network disposed on the first surface adjacent to the cavity. | 05-28-2009 |
| 20090134490 | ELECTRONIC COMPONENT MODULE - A ferrite substrate, a winding-embedded ferrite resin layer, and an IC-embedded ferrite resin layer are laminated, the ferrite substrate has a ferrite first protruding part that protrudes into the ferrite resin layer from the surface thereof, the winding inside the ferrite resin layer is arranged winding around the first protruding part, and the IC overlaps the first protruding part in the resin layer. According to this configuration, high integration can be achieved, and the IC is arranged at a site where the ferrite first protruding part, the height of which fluctuates little as a result of thermal expansion, overlaps the ferrite resin layer, the thickness of which is thinned by the first protruding part and varies little as a result of thermal expansion, minimizing variations in the gap between the winding and the IC as a result of thermal expansion, and achieving greater stability of electrical characteristics. | 05-28-2009 |
| 20090140383 | METHOD OF CREATING SPIRAL INDUCTOR HAVING HIGH Q VALUE - A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided over which a spirally patterned conductor layer is formed to produce a planar spiral inductor. A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV). Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface thereof. | 06-04-2009 |
| 20090140384 | PROCESS FOR OBTAINING A THIN, INSULATING, SOFT MAGNETIC FILM OF HIGH MAGNETIZATION, CORRESPONDING FILM AND CORRESPONDING INTEGRATED CIRCUIT - A thin soft magnetic film combines a high magnetization with an insulating character. The film is formed by nitriding Fe-rich ferromagnetic nanograins immersed in an amorphous substrate. A selective oxidation of the amorphous substrate is then performed. The result is a thin, insulating, soft magnetic film of high magnetization. Many types of integrated circuits can be made which include a component using a membrane incorporating the above-mentioned thin film. | 06-04-2009 |
| 20090146252 | INTEGRATED INDUCTOR STRUCTURE - This invention provides an integrated inductor structure including a substrate, a metal coil layer on the substrate and a dielectric layer between the substrate and the metal coil layer. A well shielding structure for reducing eddy current is disposed in the substrate under the metal coil layer. The well shielding structure is chequered with a plurality of N wells and a plurality of P wells. The N wells and P wells are arranged in a chessboard-like manner. A P+ pickup ring is provided in the substrate to encompass the well shielding structure. A guard ring is formed directly on the P+ pickup ring. | 06-11-2009 |
| 20090146253 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Manufacturing an inductor includes forming a spiral metal wire on a semiconductor substrate; forming a connection hole exposing a portion of the metal wire by selectively etching a first dielectric film formed to bury the metal wire, and forming a first metal film on the first dielectric film on which the connection hole is formed; forming a second dielectric film on the first metal film; and forming a first photoresist film for forming a second metal wire corresponding to the spiral metal wire on the second dielectric film, and forming the second metal wire by selectively etching the second dielectric film and the first metal film using the first photoresist pattern as an etching mask; wherein the second dielectric film prevents an etching of the top of the second metal wire resulting from the difference in etch rate between the first photoresist pattern and first metal film. | 06-11-2009 |
| 20090152674 | Semiconductor device - A semiconductor device contains a semiconductor substrate, an insulating film formed on the semiconductor substrate, an inductor formed over the semiconductor substrate while placing a portion of the insulating film in between, and a guard ring surrounding the inductor in a plan view, and isolating the inductor from other regions, wherein the guard ring contains an annular impurity diffused layer provided in the surficial portion of the semiconductor substrate, and an annular electro-conductor connected to the impurity diffused layer, and extended across a plurality of interconnect layers, up to a layer having a level of height not lower than the layer having the inductor provided therein. | 06-18-2009 |
| 20090152675 | INDUCTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device having a first region formed with the inductor and a second region formed with transistors, the inductor includes a deep well region formed in the silicon substrate beneath the first and second regions, a well region formed on the deep well region in the second region, N type shield regions formed to have the same depth as the well region, and P type shield regions arranged to alternate with the N type shield regions, the transistors formed on the silicon substrate in the second region, an insulating film formed over an entire surface of the silicon substrate such that the insulating film covers the transistors, and a metal line formed on the insulating film in the first region such that the metal line corresponds to the N and P type shield regions. | 06-18-2009 |
| 20090152676 | ELECTRONIC DEVICE INCLUDING AN INDUCTOR - An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached to the conductive traces over the shock-absorbing layer. In another aspect, a process can be used to form the electronic device including the inductor. In still another aspect, an electronic device can a toroidal-shaped inductor that includes linear inductor segments that are connected in series. | 06-18-2009 |
| 20090160018 | INDUCTOR AND MANUFACTURING METHOD THREOF - An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part. | 06-25-2009 |
| 20090166804 | FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS - Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another. | 07-02-2009 |
| 20090212390 | INDUCTIVELY COUPLED INTEGRATED CIRCUIT AND METHODS FOR USE THEREWITH - A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die has a second circuit and a second inductive interface. The first inductive interface and the second inductive interface are aligned to magnetically communicate signals between the first circuit and the second circuit. | 08-27-2009 |
| 20090212391 | Micromodules Including Integrated Thin Film Inductors and Methods of Making the Same - Micromodules and methods of making them are disclosed. An exemplary micromodule includes a substrate having a thin film inductor, and a bumped die mounted on the substrate and over the thin film inductor. | 08-27-2009 |
| 20090218657 | INDUCTIVELY COUPLED INTEGRATED CIRCUIT WITH NEAR FIELD COMMUNICATION AND METHODS FOR USE THEREWITH - A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die includes a second circuit and a second inductive interface, wherein the first inductive interface and the second inductive interface are aligned to magnetically communicate first signals between the first circuit and the second circuit and wherein the second inductive interface is coupled to engage in near field communications with a remote device, wherein the near field communications include second signals. | 09-03-2009 |
| 20090236689 | INTEGRATED PASSIVE DEVICE AND METHOD WITH LOW COST SUBSTRATE - According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device ( | 09-24-2009 |
| 20090236690 | WIRE BOND AND REDISTRIBUTION LAYER PROCESS - A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip. | 09-24-2009 |
| 20090243034 | SEMICONDUCTOR DEVICE - A semiconductor device including a doped substrate of a first doping polarity and a doped semiconductor material of a second doping polarity. The semiconductor material is on, or in, the substrate, and the second doping polarity is opposite the first doping polarity such that the semiconductor material and the substrate form a diode. The semiconductor device further includes an inductor on or above the semiconductor material, and a pattern in the semiconductor material for reducing eddy currents. The pattern includes a doped semiconductor material of the first doping polarity and a least one trench within the doped semiconductor material of the first doping polarity, wherein, at least at a depth at which the trench is closest to the inductor, the doped semiconductor material of the first doping polarity fully surrounds the trench so that, at least at the depth, the trench does not touch the doped semiconductor material of the second doping polarity. | 10-01-2009 |
| 20090243035 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE - In a semiconductor device that is formed by joining two semiconductor elements together to oppose device layers to each other, inductor patterns for transmitting and receiving a signal and feeding a power and bumps for connecting electrically the semiconductor elements and for supporting the inductor patterns and the semiconductor elements being arranged opposedly in an electrically isolated state are provided on a surface of the device layer of at least one of semiconductor elements and an electrically insulating material is filled in a space between opposing surfaces of the semiconductor elements. | 10-01-2009 |
| 20090256236 | MEMS-topped integrated circuit with a stress relief layer and method of forming the circuit - The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices. | 10-15-2009 |
| 20090261452 | SEMICONDUCTOR DEVICE INCLUDING AN INDUCTOR ELEMENT - An inductor element is formed in a spiral shape so as to have a plurality of windings which cross each other three-dimensionally at least in one intersection on a substrate. Each of the plurality of windings is formed by a first wiring formed on the substrate with a first insulating film interposed therebetween and a second wiring formed on the first wiring with a second insulating film interposed therebetween. The first wiring and the second wiring are electrically connected to each other in a region other than the intersection of the plurality of windings through an opening formed in the second insulating film. A lower wire segment in the intersection is formed only by the first wiring by separating the second wiring in the intersection. An upper wire segment in the intersection is formed only by the second wiring by separating the first wiring in the intersection. | 10-22-2009 |
| 20090261453 | AIR GAP IN INTEGRATED CIRCUIT INDUCTOR FABRICATION - A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen. | 10-22-2009 |
| 20090267182 | METHOD OF INCREASING THE QUALITY FACTOR OF AN INDUCTOR IN A SEIMICONDUCTOR DEVICE - A method of fabricating an inductor ( | 10-29-2009 |
| 20090283854 | Design Structure and Method for Buried Inductors for Ultra-High Resistivity Wafers for SOI/RF SIGE Applications - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween. | 11-19-2009 |
| 20090283855 | SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME - An inductor having a helicoidal shape is provided on an insulation film formed on a semiconductor substrate. A conductive thin layer (a plating layer) is provided on a surface of the inductor. A conductivity of the conductive thin layer is higher than that of the inductor. According to the constitution, a Q value can be improved, and a large volume of current can be flowed. | 11-19-2009 |
| 20090302419 | METHOD OF MODIFYING SURFACE AREA AND ELECTRONIC DEVICE - In the method a first layer, particularly of amorphous silicon, is deposited on the surface of a substrate with trenches. Part of this surface is covered with a protective layer. The first layer is thereafter maskless removed with a dry etching treatment on the substrate surface while it is kept within the trench. | 12-10-2009 |
| 20090302420 | Semiconductor device - A multilayer wiring layer | 12-10-2009 |
| 20090309185 | INDUCTOR MODULE, SILICON TUNER MODULE AND SEMICONDUCTOR DEVICE - Disclosed herein is an inductor module including a substrate functioning as a printed wiring board or an interposer; an IC mounting part formed on a surface of the substrate; an inductor which is formed in the substrate at such a position as to overlap with the IC mounting part on a plan-view basis and which is connected to an IC mounted on the IC mounting part; and a magnetic body including a magnetic material selected from among a NiZn ferrite, a NiZnCu ferrite and a Ba ferrite, the magnetic body being disposed intermediately between the IC mounting part and the inductor. | 12-17-2009 |
| 20090321876 | SYSTEM WITH RADIO FREQUENCY INTEGRATED CIRCUITS - A semiconductor package comprises an integrated radio frequency circuit that may be provided in a semiconductor die. A ground plane may be attached to the semiconductor die. The ground plane is selectively patterned in a direction that is perpendicular to an inductor trace of an inductor of the radio frequency circuit. In some embodiments, the ground plane may be selectively patterned to allow an eddy current in the semiconductor package not to flow in opposite direction of a main current in the inductor. In one example, the ground plane may be a portion of the semiconductor package substrate or a die back metallization of the semiconductor die. | 12-31-2009 |
| 20100006977 | INDUCTOR AND FILTER - An inductor includes a first air-bridge section and a second air-bridge section. The first air-bridge unit extends in a floating location over a substrate between a plurality of support locations on the substrate. The second air-bridge unit extends in a floating location over the first air-bridge unit between a plurality of support locations on the first air-bridge unit. This arrangement enables the first and second air-bridge sections to be connected in parallel, thus branching a flowing current. Thus, the conductor loss in each of the first and second air-bridge sections is reduced. | 01-14-2010 |
| 20100006978 | CIRCUIT BOARD AND SEMICONDUCTOR DEVICE - A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated. | 01-14-2010 |
| 20100019346 | IC HAVING FLIP CHIP PASSIVE ELEMENT AND DESIGN STRUCTURE - IC and design structure including various ways of raising a passive element such as an inductor off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap. | 01-28-2010 |
| 20100038749 | Contact and VIA Interconnects Using Metal Around Dielectric Pillars - An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect. | 02-18-2010 |
| 20100052095 | INDUCTOR FOR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An inductor for semiconductor devices and a method of fabricating the same are disclosed. Through an improved electrical connection between a metal wiring and an inductor line, an improved Q-index and minimized energy loss in a substrate can be accomplished, and a parasitic capacitance can be minimized. For this, the inductor which may include a substrate and an insulating layer formed over the substrate and containing a metal wiring therein. A metal pad may be formed over the insulating layer. An inductor line may be formed over the insulating layer and connected to the metal pad. A pad contact, a metal layer and a via contact may be sequentially stacked within the insulating layer between the metal wiring and the metal pad. | 03-04-2010 |
| 20100052096 | STACKED-CHIP DEVICE - A stacked-chip device includes a first inductive chip having a first function, a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip, and a third inductive chip having the second function, which is stacked on the second inductive chip. Each of the first, second and third inductive chips has transmitting inductors which transmit data and receiving inductors which receive data. The transmitting inductors and the receiving inductors are disposed in line symmetry to an axis of symmetry. The axes of symmetry of the first, second and third inductive chips are overlapped. Each of the second and third inductive chips is disposed in upside-down or back to front to the first inductive chip. | 03-04-2010 |
| 20100065942 | Semiconductor Device and Method of Forming High-Frequency Circuit Structure and Method Thereof - A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to form a resistor and the first metal layer forms a first inductor. A wafer supporter is mounted over the IPD using an adhesive material and a third metal layer is deposited over the IPD. The third metal layer forms a second inductor that is electrically connected to the capacitor and the resistor by the TSVs of the IPD. An interconnect structure is connected to the IPD. | 03-18-2010 |
| 20100072572 | SEMICONDUCTOR DEVICE - One or more embodiments relate to a semiconductor device, comprising: a inductor coil including a winding; and a capacitor arrangement including at least one capacitor, the capacitor arrangement electrically coupled to the inductor coil, the footprint of the capacitor arrangement at least partially overlapping the footprint of the inductor coil. | 03-25-2010 |
| 20100078760 | INTEGRATED CIRCUIT MODULE WITH INTEGRATED PASSIVE DEVICE - A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP. | 04-01-2010 |
| 20100078761 | SEMICONDUCTOR TRANSFORMERS - A planar transformer structure, which can be constructed in an integrated semiconductor circuit without using traditional metallic windings. To avoid large thermal expansion of metallic spiral windings and associated mechanical stress on a metal-semiconductor interface, it is suggested that highly doped semiconductor materials with or without silicides and salicides can be used to form windings or conducting paths because their thermal expansion coefficients are similar to that of semiconductor material. The planar semiconductor transformer may find application for low-power and signal transfer that needs electrical isolation. | 04-01-2010 |
| 20100096725 | Semiconductor Package with Embedded Spiral Inductor - In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector. | 04-22-2010 |
| 20100102416 | Integrated Circuit Packages Incorporating an Inductor and Methods - Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed. | 04-29-2010 |
| 20100109123 | Method of Constructing Inductors and Transformers - An embodiment of the invention relates to an apparatus including a magnetic device and a related method. A multilayer substrate is constructed with a winding formed in a metallic layer, an electrically insulating layer above the metallic layer, and a via formed in the electrically insulating layer to couple the winding to a circuit element positioned on the multilayer substrate. A depression is formed in the multilayer substrate, and a polymer solution, preferably an epoxy, containing a ferromagnetic component such as nanocrystaline nickel zinc ferrite is deposited within a mold positioned on a surface of the multilayer substrate above the winding and in the depression. An integrated circuit electrically coupled to the winding may be located on the multilayer substrate. The multilayer substrate may be a semiconductor substrate or a printed wiring board, and the circuit element may be an integrated circuit formed on the multilayer substrate. | 05-06-2010 |
| 20100133652 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device capable of increasing the capacitance of a capacitor, while reducing an area occupied by the capacitor and inductor on a substrate. The semiconductor device includes a first line; an interlayer insulating film that is formed on the first line and has a recess formed at a location corresponding to the first line; and a second line formed in the recess of the interlayer insulating film. The first line, the second line, and an insulating film formed between the first line and the second line constitute a capacitor. At least one of the first line and the second line constitutes an inductor. | 06-03-2010 |
| 20100133653 | INTEGRATED CIRCUIT DEVICES INCLUDING PASSIVE DEVICE SHIELDING STRUCTURES AND METHODS OF FORMING THE SAME - Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part. The second longitudinally extending part extends at an angle from an end of the first longitudinally extending part. Ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship. | 06-03-2010 |
| 20100140739 | Semiconductor Device and Fabricating Method Thereof - Disclosed is a semiconductor device which includes a substrate having an air layer or void therein, an interlayer dielectric film above the substrate, and a metal wiring having a spiral structure on the interlayer dielectric film corresponding to or over the air layer. The semiconductor device exhibits reduced parasitic capacitance between the metal wiring (used as an inductor) and the substrate, thereby improving a self-resonance frequency as well as an applicable frequency band of the inductor. | 06-10-2010 |
| 20100148302 | CAPACITOR-EQUIPPED SEMICONDUCTOR DEVICE - A capacitor-equipped semiconductor device includes a semiconductor chip having a plurality of electrode terminals; a sheet-like substrate at least having a film capacitor; and a mounting substrate. The mounting substrate is provided on one side thereof with chip connection terminals and ground terminals. The chip connection terminals are disposed to correspond to the electrode terminals of the semiconductor chip. The ground terminals are disposed to correspond to the one electrode terminals of the film capacitor of the sheet-like substrate. The mounting substrate is provided on the other side thereof with external connection terminals connected to the chip connection terminals and the ground terminals and used to mount the mounting substrate on an external substrate. | 06-17-2010 |
| 20100148303 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor substrate; an interlayer insulating film formed on the semiconductor substrate; a first inductor interconnect layer having a spiral pattern, formed to be embedded in a top portion of the interlayer insulating film; a barrier insulating film formed to cover the interlayer insulating film and the first inductor interconnect layer, the barrier insulating film having at least one connecting groove running along the first inductor interconnect layer; and a second inductor interconnect layer formed on the barrier insulating film to run along the first inductor interconnect layer and fill the connecting groove to be electrically connected with the first inductor interconnect layer. The second inductor interconnect layer has at least one concave groove formed on the top to run along the length thereof. | 06-17-2010 |
| 20100155886 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a chip having a plurality of first power voltage terminals connected in common to a first power voltage line, a plurality of second power voltage terminals connected in common with a second power voltage line, a first connection terminal, a second connection terminal connected to the first power voltage line or the second power voltage line, and an on-die capacitor. The semiconductor device also includes a package having a plurality of third power voltage terminals connected to the first power voltage terminals through a first wire by wire bonding during a packaging process and a plurality of fourth power voltage terminals connected to the second power voltage terminals through a second wire by wire bonding during the packaging process, and configured to package the chip, wherein one end of the on-die capacitor is connected to the first connection terminal, and the first connection terminal is connected to the second connection terminal through a third wire by wire bonding during the packaging process. | 06-24-2010 |
| 20100164058 | CHIP PACKAGE WITH STACKED INDUCTORS - A semiconductor chip package with inductors includes a substrate, a semiconductor chip, an inductor and an insulator cover. The substrate has an active surface with a patterned circuit thereon. The inductor disposes on the active surface of the substrate. The semiconductor chip stacks over the inductor and electrically interconnects with the patterned circuit of the substrate and the inductor. The insulator cover encapsulates the inductor and the chip. | 07-01-2010 |
| 20100164059 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate; an insulating film formed over the semiconductor substrate, there being formed in the insulating film a trench that in a sectional view has a stepped shape; and a wiring formed in the trench, wherein the wiring includes, a main portion with a first thickness; and an extended portion with a second thickness that is thinner than the first thickness and that extends outward from a side of the main portion. | 07-01-2010 |
| 20100164060 | INDUCTOR FOR SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An inductor for a semiconductor device and a method for fabricating the same includes a wafer, a first metal pad formed on the wafer and having a surface exposed from the surface of the wafer, a second metal pad formed on the wafer and having a surface exposed from the surface of the wafer, a first inductor line formed in the wafer and extending from the first metal pad and having a plurality of branches with a surface exposed from the surface of the wafer, and a second inductor line formed in the wafer and extending from the second metal pad and having a plurality of branches with a surface exposed from the surface of the wafer. The plurality of branches of the first inductor line and the plurality of branches of the second inductor line are arranged in parallel in an alternating pattern. | 07-01-2010 |
| 20100171194 | Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate - A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. | 07-08-2010 |
| 20100176484 | ESD protection device, composite electronic component of the same, manufacturing method of composite substrate, and manufacturing method of ESD protection device - The present invention provides an ESD protection device and the like having improved durability against repeated use. The ESD protection device includes a base | 07-15-2010 |
| 20100193904 | INTEGRATED CIRCUIT INDUCTOR WITH DOPED SUBSTRATE - An integrated circuit inductor and a substrate with doped regions are provided. The substrate may be a p-type substrate and the substrate may have n-type doped regions. The n-type doped regions may include n-type wells, deep n-type wells, and n+ regions. The n-type doped regions may be formed in a pattern of strips such as a triangular comb pattern of strips or a series of L-shaped strips. The strips may be oriented perpendicular to the spiral of the inductor. A positive bias voltage may be applied to the n-type doped regions to create a depleted region in the substrate between the n-type doped regions. The depleted region may increase the effective distance between the inductor and the substrate, minimizing undesired coupling effects between the inductor and the substrate and increasing the effectiveness of the inductor. | 08-05-2010 |
| 20100193905 | Techniques for Placement of Active and Passive Devices Within a Chip - A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs). | 08-05-2010 |
| 20100224957 | MICROSCOPIC ELECTRO-MECHANICAL SYSTEMS, RADIO FREQUENCY DEVICES UTILIZING NANOCOILS AND SPRIAL PITCH CONTROL TECHNIQUES FOR FABRICATING THE SAME - Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include microscopic electro-mechanical systems (MEMS) devices including nanocoil mirrors, nanocoil actuators and nanocoil antenna arrays. Inductors or traveling wave tubes fabricated from nanocoils are also included. A method for fabricating nanocoils with a desired pitch includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed. | 09-09-2010 |
| 20100224958 | RF-IC PACKAGING METHOD AND CIRCUITS OBTAINED THEREBY - Typically, chips nowadays comprise a number of circuits as well as a number of inductors, often RF-inductors. These IC inductors are essential to realize the voltage controlled oscillators needed in the many fully integrated transceiver chips, serving a multitude of wireless communication protocols, that are provided to the market today. The present invention relates to an RF-IC packaging method, which virtually eliminates the long-range electromagnetic crosstalk between inductors and transmission lines of different parts of the circuitry. | 09-09-2010 |
| 20100230782 | SEMICONDUCTOR DEVICE - A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire. | 09-16-2010 |
| 20100230783 | SEMICONDUCTOR DEVICE - A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit. | 09-16-2010 |
| 20100230784 | Semiconductor Packaging with Integrated Passive Componentry - The invention provides advances in the arts with useful and novel integrated packaging having passive components included within packages also containing one or more ICs. The integrated passive components may include inductors, transformers, and capacitors, and are preferably constructed of leadframe materials. Typically, one or more magnetic field storage body is used in forming the coils in order to enhance the electrical performance characteristics of the passive component. | 09-16-2010 |
| 20100230785 | INDUCTIVELY COUPLED INTEGRATED CIRCUIT AND METHODS FOR USE THEREWITH - A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die has a second circuit and a second inductive interface. The first inductive interface and the second inductive interface are aligned to magnetically communicate signals between the first circuit and the second circuit. | 09-16-2010 |
| 20100237462 | Package Level Tuning Techniques for Propagation Channels of High-Speed Signals - Various semiconductor chip carrier substrate circuit tuning apparatus and methods are disclosed. In one aspect, a method of manufacturing is provided that includes assembling a semiconductor chip carrier substrate with a first input/output site adapted to electrically connect to an external component and a second input/output site adapted to electrically connect to an input/output site of a semiconductor chip. An inductor is placed in the semiconductor chip carrier substrate. The inductor is electrically connected between the first and second input/output sites. The inductor has a preselected inductance to reduce an impedance discontinuity between the first input/output site or the second input/output site due to coupling to a second conductor in the semiconductor chip carrier substrate. | 09-23-2010 |
| 20100244187 | ESD NETWORK CIRCUIT WITH A THROUGH WAFER VIA STRUCTURE AND A METHOD OF MANUFACTURE - The present invention generally relates to a circuit structure and a method of manufacturing a circuit, and more specifically to an electrostatic discharge (ESD) circuit with a through wafer via structure and a method of manufacture. An ESD structure includes an ESD active device and at least one through wafer via structure providing a low series resistance path for the ESD active device to a substrate. An apparatus includes an input, at least one power rail and an ESD circuit electrically connected between the input and the at least one power rail, wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate. A method, includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate. | 09-30-2010 |
| 20100244188 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device comprising: a semiconductor substrate in which an integrated circuit is formed; a first resin film provided over the semiconductor substrate; a second resin film provided over an upper surface of the first resin film except at least a peripheral portion of the first resin film; and a thin film inductor provided over the second resin film. | 09-30-2010 |
| 20100264515 | Semiconductor device - An interconnect substrate is placed over a first inductor of a semiconductor chip and a second inductor of another semiconductor chip. The interconnect substrate includes a third inductor and a fourth inductor. The third inductor is located above the first inductor. The distance from the first inductor to the third inductor is longer than the distance from the second inductor to the fourth inductor. | 10-21-2010 |
| 20100264516 | Method of Forming an Inductor on a Semiconductor Wafer - A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad. | 10-21-2010 |
| 20100270642 | Semiconductor device - A first inductor is connected to a transmission circuit. A second inductor is connected to a reception circuit, and is inductively coupled to the first inductor. At least part of the first inductor is formed with a first bonding wire. The first bonding wire has two ends connected to a first connecting terminal and a third connecting terminal. At least part of the second inductor is formed with a second bonding wire. The second bonding wire has two ends connected to a second connecting terminal and a fourth connecting terminal. | 10-28-2010 |
| 20100289118 | SEMICONDUCTOR DEVICE - A semiconductor device has an inductor. The inductor has a first metal interconnection layer formed in the insulation film to extend in a first direction which is parallel to a substrate face of the semiconductor substrate, and connected electrically at a first end part thereof to the first terminal; a first via interconnection formed in the insulation film to extend in a second direction perpendicular to the substrate face, and connected at a top part thereof to a second end part of the first metal interconnection layer; and a second metal interconnection layer formed in the insulation film to extend in the first direction under the first metal interconnection layer, facing to the first metal interconnection layer, insulated from the first metal interconnection layer by the insulation film, connected at a first end part thereof to a bottom part of the first via interconnection, and connected electrically at a second end part thereof to the second terminal. | 11-18-2010 |
| 20100295150 | SEMICONDUCTOR DEVICE WITH OXIDE DEFINE DUMMY FEATURE - A semiconductor device includes a substrate, an inductor wiring pattern on the substrate, and at least one oxide define (OD) dummy feature disposed in the substrate under the inductor wiring pattern. | 11-25-2010 |
| 20100295151 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first substrate having a first surface on which a passive element is formed and a second surface on which a shield layer is formed, and a second substrate having a first surface on which an active element is formed. The first substrate is mounted on the second substrate with the second surface of the first substrate facing the second substrate. | 11-25-2010 |
| 20100301450 | Semiconductor Device and Method of Forming IPD Structure Using Smooth Conductive Layer and Bottom-side Conductive Layer - A semiconductor device is made by forming a smooth conductive layer over a substrate. A first insulating layer is formed over a first surface of the smooth conductive layer. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The substrate is removed. A second conductive layer is formed over a second surface of the smooth conductive layer opposite the first surface of the smooth conductive layer. A third insulating layer is formed over the second conductive layer. The second conductive layer, smooth conductive layer, first insulating layer, and first conductive layer constitute a MIM capacitor. A portion of the second conductive layer includes an inductor. The smooth conductive layer has a smooth surface to reduce particles and hill-locks which decreases ESR, increases Q factor, and increases ESD of the MIM capacitor. | 12-02-2010 |
| 20100308434 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series. | 12-09-2010 |
| 20100314713 | Integrated Circuit Inductors with Reduced Magnetic Coupling - An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions. | 12-16-2010 |
| 20100314714 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a first substrate and a second substrate. The first substrate includes a semiconductor substrate. An active element portion is formed on one of the surfaces of the first substrate, and a first through electrode electrically connected to the active element is formed to extend through the first substrate. A passive element is formed on one of the surfaces of the second substrate, and a second through electrode electrically connected to the passive element is formed to extend through the second substrate. The other surface of the first substrate and the other surface of the second substrate are opposed to each other, and the first through electrode and the second through electrode are electrically connected to each other. | 12-16-2010 |
| 20100327404 | INDUCTOR STRUCTURES FOR INTEGRATED CIRCUIT DEVICES - An IC device ( | 12-30-2010 |
| 20100327405 | ELECTRICAL PROPERTY ALTERING, PLANAR MEMBER WITH SOLDER ELEMENT IN IC CHIP PACKAGE - A structure includes a solder element for electrically coupling a substrate of an integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate. | 12-30-2010 |
| 20100327406 | Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In Substrate - A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties. | 12-30-2010 |
| 20110001214 | SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF MAKING - An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor. | 01-06-2011 |
| 20110001215 | MULTI-COMPONENT ELECTRONIC PACKAGE - An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure. | 01-06-2011 |
| 20110012228 | SEMICONDUCTOR DEVICE - A plurality of semiconductor chips are juxtaposed, each having an electromagnetic induction coil disposed thereon. A signal is transmitted by way of electromagnetic induction between the electromagnetic induction coils disposed on a pair of adjacent semiconductor chips. | 01-20-2011 |
| 20110031583 | HIGH FREQUENCY DEVICE - A small high frequency device that is able to inhibit generation of an eddy current and a parasitic capacity and shows superior high frequency characteristics is provided. The high frequency device includes: a substrate having a depression; a dielectric layer over the substrate; and a plurality of electronic devices which are provided in the dielectric layer or on the dielectric layer, and at least one of which is opposed to the depression. | 02-10-2011 |
| 20110031584 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first insulating film includes five extension lines formed between connection pad portions of adjacent two predetermined wiring lines. The first insulating film also includes peripheral portions of the adjacent two connection pad portions on both sides of the five extension lines. A second insulating film made of a polyimide resin or the like is formed on the upper surface of the first insulating layer by a screen printing method or ink jet method. Since a short circuit may be easily caused by electromigration in a region where the five extension lines are parallel to another, the short circuit due to the electromigration can be prevented by covering only that region with the second insulating film. Accordingly, the region where the second insulating film is formed can be as small as possible, and the semiconductor wafer does not easily warp. | 02-10-2011 |
| 20110042782 | ON-CHIP INDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a an on-chip inductor structure and a method for manufacturing the same. The an on-chip inductor structure according to the present invention comprises a substrate, a porous layer, a plurality of conductors, and an inductor. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of conductors is disposed in the plurality of voids, respectively; and the inductor is disposed on the porous layer. Because the plurality of conductors is used as the core of the inductor, the inductance is increased effectively and the area of the an on-chip inductor is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered. | 02-24-2011 |
| 20110042783 | ELECTRONIC DEVICE AND FABRICATION METHOD THEREOF - An electronic device and fabrication method thereof are provided. The electronic device contains a glass substrate, a patterned semiconductor substrate, having at least one opening, disposed on the glass substrate and at least one passive component having a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed between the patterned semiconductor substrate and the glass substrate. | 02-24-2011 |
| 20110049671 | BONDING PAD STRUCTURE AND INTEGRATED CIRCUIT CHIP USING SUCH BONDING PAD STRUCTURE - An integrated circuit chip includes a substrate; a topmost metal layer over the substrate; a lower metal layer on or over the substrate and lower than the topmost metal layer; and at least one bonding pad in the lower metal layer. | 03-03-2011 |
| 20110049672 | SEMICONDUCTOR DEVICE - A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section. | 03-03-2011 |
| 20110057291 | ULTRA HIGH SPEED SIGNAL TRANSMISSION/RECEPTON - An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device. | 03-10-2011 |
| 20110062549 | Semiconductor Device and Method of Forming Integrated Passive Device - An IPD semiconductor device has a capacitor formed over and electrically connected to a semiconductor die. An encapsulant is deposited over the capacitor and around the semiconductor die. A first interconnect structure is formed over a first surface of the encapsulant by forming a first conductive layer, forming a first insulating layer over the first conductive layer, and forming a second conductive layer over the first insulating layer. The second conductive layer has a portion formed over the encapsulant at least 50 micrometer away from a footprint of the semiconductor die and wound to operate as an inductor. The portion of the second conductive layer is electrically connected to the capacitor by the first conductive layer. A second interconnect structure is formed over a second surface of the encapsulant. A conductive pillar is formed within the encapsulant between the first and second interconnect structures. | 03-17-2011 |
| 20110068433 | FORMING RADIO FREQUENCY INTEGRATED CIRCUITS - Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate. | 03-24-2011 |
| 20110073987 | Through Substrate Features in Semiconductor Substrates - Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate. | 03-31-2011 |
| 20110073988 | Semiconductor Component and Method of Manufacture - A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates. | 03-31-2011 |
| 20110079876 | Method of Manufacturing a Semiconductor Component and Structure - A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated passive device. In accordance with embodiments, the monolithically integrated passive device includes an inductor formed from damascene structures. | 04-07-2011 |
| 20110084358 | Apparatus and Method for Through Silicon via Impedance Matching - Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit. | 04-14-2011 |
| 20110084359 | SEMICONDUCTOR DEVICE - A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor. | 04-14-2011 |
| 20110089530 | Semiconductor Device - This application relates to a semiconductor device comprising a first chip comprising a first electrode on a first face of the first chip, and a second chip attached to the first electrode, wherein the second chip comprises a transformer comprising a first winding and a second winding. | 04-21-2011 |
| 20110095395 | Inductors and Methods for Integrated Circuits - Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed. | 04-28-2011 |
| 20110101497 | METHOD FOR FABRICATING A FLIP-BONDED DUAL-SUBSTRATE INDUCTOR, FLIP-BONDED DUAL-SUBSTRATE INDUCTOR, AND INTEGRATED PASSIVE DEVICE INCLUDING A FLIP-BONDED DUAL-SUBSTRATE INDUCTOR - A flip-bonded dual-substrate inductor includes a base substrate, a first inductor body portion provided on a surface of the base substrate, a cover substrate, a second inductor body portion provided on a surface of a cover substrate, and a nanoparticle bonding material provided between the base substrate surface and the cover substrate surface to electrically connect the first inductor body portion and the second inductor body portion. A method for fabricating a flip-bonded dual-substrate inductor including forming a first inductor body portion on a surface of a base substrate, forming a second inductor body portion on a surface of a cover substrate, and attaching the base substrate surface to the cover substrate surface using a nanoparticle bonding material that electrically connects the first inductor body portion and the second inductor body portion. | 05-05-2011 |
| 20110101498 | SEMICONDUCTOR DEVICE AND ARRANGEMENT METHOD THEREOF - An arrangement method of a semiconductor device including external connection terminals and inductors, the terminals being arranged at a predetermined pitch in a lattice pattern is provided. The method includes determining the arrangement of the terminals, determining a maximum width of air-core portions of the inductors, drawing first virtual lines passing a central position between two adjacent ones of the terminals in a first direction, drawing second virtual lines passing a central position between two adjacent ones of the terminals in a direction orthogonal to the first direction, determining a permissible range of distances between the first and second virtual lines nearest to each inductor and the inductor center, and arranging the inductors such that at least one of a distance between the nearest first virtual line and the inductor center and a distance between the nearest second virtual line and the inductor center falls within the permissible range. | 05-05-2011 |
| 20110108947 | Microelectronic device and method of manufacturing same - A microelectronic device comprises a first substrate ( | 05-12-2011 |
| 20110133308 | SEMICONDUCTOR DEVICE WITH OXIDE DEFINE PATTERN - A semiconductor device includes a substrate; an inductor wiring pattern overlying the substrate, wherein the inductor wiring pattern is formed in an inductor-forming region; a plurality of shielding patterns between the inductor wiring pattern and the substrate within the inductor-forming region; and at least one first oxide define (OD) pattern disposed in the substrate or between the inductor wiring pattern and the substrate. | 06-09-2011 |
| 20110133309 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The invention relates to a semiconductor device and a manufacturing method for the same, and makes the rejection rate of the product after chips are stacked and mounted sufficiently low, even when the chips are selected in a conventional, simple and inexpensive wafer test. | 06-09-2011 |
| 20110156204 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a base material, a first metal layer, a first dielectric layer, a first upper electrode and a first protective layer. The first metal layer is disposed on a first surface of the base material, and includes a first inductor and a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first inductor and the first capacitor. Whereby, the first inductor and the first lower electrode of the first capacitor are disposed on the same layer, so that the thickness of the product is reduced. | 06-30-2011 |
| 20110156205 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT - An integrated circuit device includes a receiving circuit, a transmission circuit, and common pads common to the receiving circuit and the transmission circuit, which are disposed in such a way that the distance between the receiving circuit and the common pad, and the distance between the transmission circuit and the common pad become shorter, respectively. | 06-30-2011 |
| 20110163413 | RF SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A radio frequency (RF) semiconductor device includes a semiconductor substrate, a resistor film formed at one area of the semiconductor substrate, a first metal layer formed on the semiconductor substrate, a dielectric layer formed at least on the lower electrode film, a second metal layer formed on the dielectric layer, a first insulating layer having a first pad via connected with the first metal layer, a capacitor via connected with the second metal layer, and an inductor via connected with the first or second metal layer. a third metal layer includes filling parts that fill the capacitor via and the inductor via, respectively, and a second circuit line. A second insulating layer is formed on the first insulating layer to have a second pad via connected with the first pad via. A bonding pad is formed at the first and second pad vias. | 07-07-2011 |
| 20110163414 | Semiconductor Device Having Embedded Integrated Passive Devices Electrically Interconnected Using Conductive Pillars - A semiconductor device includes a first conductive layer and conductive pillars disposed over the first conductive layer and directly contacting the first conductive layer. The semiconductor device includes an Integrated Passive Device (IPD) mounted to the first conductive layer such that the IPD is disposed between the conductive pillars. The IPD is self-aligned to the first conductive layer, and includes a metal-insulator-metal capacitor disposed over a first substrate and a wound conductive layer forming an inductor disposed over the first substrate. The semiconductor device includes a discrete capacitor mounted over the first conductive layer. The discrete capacitor is electrically connected to one of the conductive pillars. The semiconductor device includes an encapsulant disposed around the IPD, discrete capacitor, and conductive pillars, a first insulation layer disposed over the encapsulant and conductive pillars, and a second conductive layer disposed over the first insulating layer. The second conductive layer is electrically connected to the conductive pillars. | 07-07-2011 |
| 20110169130 | Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure - A semiconductor device, includes a semiconductor device, a wiring layer provided on the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring, wherein the wiring layer in plan view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, wherein the high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region, wherein the plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively, and wherein an average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region. | 07-14-2011 |
| 20110175193 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film. | 07-21-2011 |
| 20110175194 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method of manufacturing the same. A high-resistance silicon wafer is manufactured in such a manner that a large-sized silicon wafer manufactured by the Czochralski method is irradiated with neutrons, and high-resistance and low-resistance elements are simultaneously formed on the high-resistance silicon wafer. Thus, the manufacturing cost can be remarkably saved, and the reliability of products can be enhanced. | 07-21-2011 |
| 20110175195 | METHOD FOR MAKING HIGH-PERFORMANCE RF INTEGRATED CIRCUITS - A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line. The silicon that remains in place in the passive surface of the substrate underneath the scribe lines is removed by etching, the glass panel is separated along the scribe line. Under the second embodiment of the invention, the inductor is created on the surface of a thick layer of polymer that is deposited over the layer of passivation. | 07-21-2011 |
| 20110193192 | Stacked-Die Electronics Package with Planar and Three-Dimensional Inductor Elements - An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component. | 08-11-2011 |
| 20110204473 | VOLTAGE-CONTROLLED SEMICONDUCTOR INDUCTOR AND METHOD - A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein. | 08-25-2011 |
| 20110210419 | MULTI-CHIP PACKAGE WITH IMPROVED SIGNAL TRANSMISSION - Provided is an MCP including a plurality chips stacked therein. Each of the chips includes a plurality of inductor pads configured to transmit power or signals, and at both sides of a reference inductor pad, a first and a second inductor pads are formed to generate magnetic fluxes in different directions from each other. | 09-01-2011 |
| 20110210420 | Semiconductor Device Having IPD Structure with Smooth Conductive Layer and Bottom-Side Conductive Layer - A semiconductor device includes an interface layer, a smooth conductive layer disposed over the interface layer, and a first insulating layer disposed over a first surface of the smooth conductive layer. A first conductive layer is disposed over the first insulating layer and the interface layer, and the first conductive layer contacts the first insulating layer. A second insulating layer is disposed over the second insulating layer and the first conductive layer, and a second conductive layer is disposed below the first conductive layer and contacts a second surface of the smooth conductive layer. The second surface of the smooth conductive layer is opposite the first surface of the smooth conductive layer. A third insulating layer is disposed over the first insulating layer and the first surface of the smooth conductive layer, and a fourth insulating layer is disposed below the second conductive layer and the interface layer. | 09-01-2011 |
| 20110215438 | Stacked Semiconductor Package Having Discrete Components - A stacked semiconductor package includes a substrate and a plurality of semiconductor dice stacked on the substrate. Each semiconductor die includes a recess, and a discrete component contained in the recess encapsulated in a die attach polymer. The stacked semiconductor package also includes interconnects electrically connecting the semiconductor dice and discrete components, and an encapsulant encapsulating the dice and the interconnects. | 09-08-2011 |
| 20110221032 | BIAS CIRCUIT AND METHOD OF MANUFACTURING THE SAME - A bias circuit according to the present invention includes a resistor layer | 09-15-2011 |
| 20110221033 | HIGH POWER SEMICONDUCTOR DEVICE FOR WIRELESS APPLICATIONS AND METHOD OF FORMING A HIGH POWER SEMICONDUCTOR DEVICE - A high power semiconductor device for operation at powers greater than 5 watts for wireless applications comprises a semiconductor substrate including an active area of the high power semiconductor device, contact regions formed on the semiconductor substrate providing contacts to the active area of the high power semiconductor device, a dielectric layer formed over a part of the semiconductor substrate, a lead for providing an external connection to the high power semiconductor device and an impedance matching network formed on the semiconductor substrate between the active area of the high power semiconductor device and the lead. The impedance matching network includes conductor lines formed on the dielectric layer. The conductor lines are coupled to the contact regions for providing high power connections to the contact regions of the active area, and have a predetermined inductance for impedance matching. | 09-15-2011 |
| 20110241163 | Semiconductor Device and Method of Forming High-Attenuation Balanced Band-Pass Filter - A semiconductor device has a substrate and band-pass filter formed over the substrate. The band-pass filter includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device, and first capacitor coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The second conductive trace has a different size and shape as the first conductive trace. A second capacitor is coupled between the first and second ends of the second conductive trace. A third conductive trace is wound around the first and second conductive traces to exhibit inductive properties. | 10-06-2011 |
| 20110241164 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, an inter-layer insulating film, a wiring, and a via. The inter-layer insulating film is provided on the semiconductor substrate. The wiring is provided in the inter-layer insulating film. The via is provided in the inter-layer insulating film. Inside the inter-layer insulating film in a circumferential region around a device region, a vertical structure body is formed in which the wiring and the via are vertically connected. At least in an upper portion inside the inter-layer insulating film in an edge region located around the circumferential region and constituting an outer edge portion, no vertical structure body is formed in which the wiring and the via are vertically connected. | 10-06-2011 |
| 20110241165 | Semiconductor device and communication method - A semiconductor module includes a semiconductor device including a mounting board, a semiconductor chip disposed at a first surface of the mounting board, a first inductor which is provided at a surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside, a sealing resin layer which is formed at the first surface of the mounting board in order to seal the semiconductor chip, and a recess or an opening which is provided in the sealing resin layer and which includes the inductor inside when seen in a plan view; and a second inductor, which is located in the recess or the opening of the semiconductor device so that the second inductor performs communication with the first inductor. | 10-06-2011 |
| 20110248380 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - In a manufacturing method for a semiconductor device having a coil layer part on a substrate, two support substrates each having a flat surface are prepared, and a component member is formed on the flat surface of each of the support substrates. The component member includes a wiring portion having a predetermined pattern and an insulation film surrounding the wiring portion. The wiring portion is provided with a connecting portion exposing from the insulation film. A coil layer part is formed by opposing and bonding the component members formed on the support substrates to each other while applying pressure in a condition where the flat surfaces of the support substrates are parallel to each other. A coil is formed in the coil layer part by connecting the wiring portions through the connecting portions. | 10-13-2011 |
| 20110254123 | ULTRA HIGH SPEED SIGNAL TRANSMISSION/RECEPTION - There is provided, in combination, an integrated circuit chip, a device, and a multilayered structure mounted between the integrated circuit chip and the device. The multilayered structure has signal pathways that transfer signals between the integrated circuit chip and the device, and at least one signal pathway with a first wireless coupling element in the multilayered structure that is in communication with a second wireless coupling element in one of the integrated circuit chip, the device, and the multilayered structure. | 10-20-2011 |
| 20110254124 | FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material. | 10-20-2011 |
| 20110272780 | METHOD AND STRUCTURE FOR IMPROVING THE QUALILTY FACTOR OF RF INDUCTORS - An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil. | 11-10-2011 |
| 20110272781 | SEMICONDUCTOR DEVICE - A package-on-package includes a semiconductor package, and a coil provided at the semiconductor package. The semiconductor package includes a bottom face, and a solder ball protruded from the bottom face. An axis of the coil is inclined with respect to the normal line of the bottom face. | 11-10-2011 |
| 20110278696 | Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device - A semiconductor device includes an internal circuit provided on a substrate, a plurality of external terminals connected to the internal circuit, a plurality of wires connecting the internal circuit and the external terminals, and a plurality of inductors communicating with an external device. Each of the inductors is connected to each of the wires. The external terminals are formed in a region not to interrupt communication between the inductors and the external device. | 11-17-2011 |
| 20110284989 | SEMICONDUCTOR APPARATUS AND POWER SUPPLY CIRCUIT - A semiconductor apparatus comprising an integrated semiconductor circuit device having pluralities of electrode pads, pluralities of first external terminals connected to the electrode pads of the integrated semiconductor circuit device, an inductor disposed in a region surrounded by the first external terminals, and a resin portion sealing them, the integrated semiconductor circuit device being arranged on an upper surface of the inductor, and the inductor being exposed from a lower surface of the resin portion together with the first external terminals. | 11-24-2011 |
| 20110291231 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE - A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke. | 12-01-2011 |
| 20110291232 | 3D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 12-01-2011 |
| 20110291233 | SEMICONDUCTOR DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREFOR - There is disclosed a package comprising at least an integrated circuit embedded in an electrically non-conductive moulded material. The moulded material includes at least one moulded pattern on at least one surface thereof, and at least one electrically conductive track in the pattern. There is further provided at least one capacitive, inductive or galvanic component electrically connecting between at least two parts of the at least one electrically conductive track. The conductive track can be configured as an antenna, and the capacitive, inductive or galvanic component is used to adjust tuning and other characteristics of the antenna. | 12-01-2011 |
| 20110298088 | Semiconductor Package with Integrated Inductor - A semiconductor package includes a semiconductor chip. An inductor is applied to the semiconductor chip. The inductor has at least one winding. An encapsulation body is formed of an encapsulation material. The encapsulation material contains a magnetic component and fills a space within the winding to form a magnetic winding core. | 12-08-2011 |
| 20110304011 | Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure - A semiconductor wafer has an insulating layer over a first surface of the substrate. An IPD structure is formed over the insulating layer. The IPD structure includes a MIM capacitor and inductor. A conductive via is formed through a portion of the IPD structure and partially through the substrate. The conductive via can be formed in first and second portions. The first portion is formed partially through the substrate and second portion is formed through a portion of the IPD structure. A first via is formed through a second surface of the substrate to the conductive via. A shielding layer is formed over the second surface of the substrate wafer. The shielding layer extends into the first via to the conductive via. The shielding layer is electrically connected through the conductive via to an external ground point. The semiconductor wafer is singulated through the conductive via. | 12-15-2011 |
| 20110304012 | Semiconductor Device and Method of Forming RF FEM With LC Filter and IPD Filter Over Substrate - A semiconductor device has a substrate and RF FEM formed over the substrate. The RF FEM includes an LC low-pass filter having an input coupled for receiving a transmit signal. A Tx/Rx switch has a first terminal coupled to an output of the LC filter. A diplexer has a first terminal coupled to a second terminal of the Tx/Rx switch and a second terminal for providing an RF signal. An IPD band-pass filter has an input coupled to a third terminal of the Tx/Rx switch and an output providing a receive signal. The LC filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The IPD filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The RF FEM substrate can be stacked over a semiconductor package containing an RF transceiver. | 12-15-2011 |
| 20110304013 | INTEGRATED INDUCTOR - A method of fabricating an integrated inductor device includes providing a silicon substrate and forming a thickness of an insulating layer overlying the silicon substrate. The insulating layer includes a dummy structure within a portion of the thickness. The method includes forming an inductor having a first portion and a second portion. The first portion includes a spiral coil of conductor lines. The method also includes exposing the dummy structure by forming an opening in the insulating layer and removing the dummy structure to form a cavity underlying the inductor to reduce a dielectric constant and to increase a Q value of the inductor. The method includes using aluminum or copper for the dummy structures. The method includes dry etching the insulator and wet etching the dummy structure. The method also includes forming the inductors using aluminum or copper. | 12-15-2011 |
| 20110304014 | PASSIVE INTEGRATED CIRCUIT - A passive integrated circuit formed on a substrate, including contact areas of a conductive material specifically capable of receiving bonding pads, wherein the conductive material further creates connections between regions of a lower metallization level. | 12-15-2011 |
| 20110309473 | CHIP PACKAGE WITH DIE AND SUBSTRATE - A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure. | 12-22-2011 |
| 20110316117 | DIE PACKAGE AND A METHOD FOR MANUFACTURING THE DIE PACKAGE - A die package and a method for manufacturing the die package are provided. The die package includes a second die arranged above a first die, the first die comprising an interconnect region on a surface facing the second die, wherein the second die is arranged laterally next to the interconnect region of the first die; a first package-internal free-standing interconnect structure disposed above the interconnect region of the first die; a second package-internal free-standing interconnect structure disposed above an interconnect region of the second die, the interconnect region of the second die being on a surface of the second die facing away from the first die; and package material formed partially around the first package-internal free-standing interconnect structure and the second package-internal free-standing interconnect structure such that a connecting portion of the first package-internal free-standing interconnect structure and a connecting portion of the second package-internal free-standing interconnect structure remains uncovered to be electrically connected to a package-external interconnect structure. | 12-29-2011 |
| 20110316118 | Semiconductor device - A semiconductor device includes a substrate including a diffusion region, a device isolation region, an inductor region, and a guard ring region, a guard ring formed on the substrate to be connected to the diffusion region in the guard ring region, an insulating film formed on the substrate, in which the insulating film includes an interconnect, and an inductor formed in the inductor region, in which the guard ring region surrounds the inductor region and the device isolation region. | 12-29-2011 |
| 20120001297 | Techniques for Placement of Active and Passive Devices within a Chip - A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs). | 01-05-2012 |
| 20120012978 | SEMICONDUCTOR DEVICE - A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor. | 01-19-2012 |
| 20120018842 | SWITCHING ELEMENT, VARIABLE INDUCTOR, AND ELECTRONIC CIRCUIT DEVICE HAVING CIRCUIT CONFIGURATION INCORPORATING THE SWITCHING ELEMENT AND THE VARIABLE INDUCTOR - An inexpensive variable inductor has inductance value continuously changeable without reducing a Q value. When a control voltage is applied to a control terminal of a MOS transistor from a power supply, a continuity region is formed in a channel, and a region between main terminals becomes conductive. When the control voltage is changed, length of the continuity region in the channel is changed. This changes length of a path area of an induced current, flowing in an induced current film. Thus, the amount of induced current is increased or decreased. Therefore, when the control voltage of the MOS transistor is changed, the inductance value of the coil is continuously changed. | 01-26-2012 |
| 20120032297 | Electronic Device and Method for Fabricating the Same, Spiral Inductor Device and Method for Fabricating the Same - The invention provides an electronic device and method for fabricating the same, and a spiral inductor device and method for fabricating the same. The electronic device includes a substrate and a conductive trace pattern formed on the substrate, wherein the conductive trace pattern has an opening to expose the substrate. | 02-09-2012 |
| 20120032298 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin. | 02-09-2012 |
| 20120038025 | INTEGRATED INDUCTOR - The invention provides advances in the arts with useful and novel integrated packaging having inductor elements and adjacent magnetic material enhancing the inductance characteristics of the packaged inductor. Preferably the integrated packages also contain one or more ICs operable coupled to the inductor(s). | 02-16-2012 |
| 20120056297 | BALUNS FOR RF SIGNAL CONVERSION AND IMPEDANCE MATCHING - A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance. | 03-08-2012 |
| 20120068300 | Inductive getter activation for high vacuum packaging - An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used. | 03-22-2012 |
| 20120068301 | MONOLITHIC MAGNETIC INDUCTION DEVICE - Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable. | 03-22-2012 |
| 20120068302 | ELECTRONIC DEVICE AND METHOD FOR DIRECT MOUNTING OF PASSIVE COMPONENTS - An electronic device including a semiconductor die, which has a top surface that is configured to operate as a printed circuit board so as to provide connections for at least one passive component, in particular a passive surface mounted device (SMD). | 03-22-2012 |
| 20120068303 | Semiconductor Device Comprising a Metal System Including a Separate Inductor Metal Layer - In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system. | 03-22-2012 |
| 20120080770 | Transformer Arrangement - A transformer arrangement and a method for producing a transformer arrangement is disclosed. | 04-05-2012 |
| 20120086101 | INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME - The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect. | 04-12-2012 |
| 20120086102 | Integrated Circuits with Magnetic Core Inductors and Methods of Fabrications Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil. | 04-12-2012 |
| 20120091558 | SHIELD-MODULATED TUNABLE INDUCTOR DEVICE - A semiconductor device is presented here. The semiconductor device includes an integrated inductor formed on a semiconductor substrate, a transistor arrangement formed on the semiconductor substrate to modulate loop current induced by the integrated inductor, dielectric material to insulate the integrated inductor from the transistor arrangement, and a controller coupled to the transistor arrangement. The controller is used to select conductive and nonconductive operating states of the transistor arrangement. A conductive operating state of the transistor arrangement allows formation of induced loop current in the transistor arrangement, and a nonconductive operating state of the transistor arrangement inhibits formation of induced loop current in the transistor arrangement. | 04-19-2012 |
| 20120098089 | SEMICONDUCTOR DEVICE, MOUNTED SUBSTRATE TO BE USED IN SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF MOUNTED SUBSTRATE - [Problem to be Solved] A semiconductor element having fine pitch electrodes is mounted on a substrate at low cost without reducing the number of input-output terminals. | 04-26-2012 |
| 20120104546 | STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME - Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical. | 05-03-2012 |
| 20120126368 | Semiconductor Package - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer | 05-24-2012 |
| 20120139082 | STACKED MICROELECTRONIC ASSEMBY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP - A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad. | 06-07-2012 |
| 20120146180 | HYBRID-CORE THROUGH HOLES AND VIAS - A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil. | 06-14-2012 |
| 20120146181 | Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die - A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer. | 06-14-2012 |
| 20120153433 | Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps - A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump. | 06-21-2012 |
| 20120161279 | Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer - A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die. | 06-28-2012 |
| 20120168901 | SEMICONDUCTOR ELECTRONIC DEVICE WITH AN INTEGRATED DEVICE WITH AN INTEGRATED GALVANIC ISOLATOR ELEMENT AND RELATED ASSEMBLY PROCESS - An electronic device is provided with: a first electronic circuit, integrated in a first die; a second electronic circuit, integrated in a second die; and a galvanic isolator element, designed to insulate galvanically, and to enable transfer of signals between, the first electronic circuit and the second electronic circuit. The galvanic isolator element has: a transformer substrate, distinct from the first die and from the second die; and a galvanic-insulation transformer formed by a first inductive element, integrated in the first die, and by a second inductive element, integrated in the transformer substrate and so arranged as to be magnetically coupled to the first inductive element. | 07-05-2012 |
| 20120175731 | SEMICONDUCTOR STRUCTURE WITH PASSIVE ELEMENT NETWORK AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor. | 07-12-2012 |
| 20120175732 | Semiconductor Package with Semiconductor Core Structure and Method of Forming Same - A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure. | 07-12-2012 |
| 20120187530 | USING BACKSIDE PASSIVE ELEMENTS FOR MULTILEVEL 3D WAFERS ALIGNMENT APPLICATIONS - Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack. | 07-26-2012 |
| 20120187531 | Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure - A semiconductor wafer has an insulating layer over a first surface of the substrate. An IPD structure is formed over the insulating layer. The IPD structure includes a MIM capacitor and inductor. A conductive via is formed through a portion of the IPD structure and partially through the substrate. The conductive via can be formed in first and second portions. The first portion is formed partially through the substrate and second portion is formed through a portion of the IPD structure. A first via is formed through a second surface of the substrate to the conductive via. A shielding layer is formed over the second surface of the substrate wafer. The shielding layer extends into the first via to the conductive via. The shielding layer is electrically connected through the conductive via to an external ground point. The semiconductor wafer is singulated through the conductive via. | 07-26-2012 |
| 20120187532 | SEMICONDUCTOR DEVICE HAVING HIGH FREQUENCY WIRING AND DUMMY METAL LAYER AT MULTILAYER WIRING STRUCTURE - A semiconductor device, includes a semiconductor device, a wiring layer provided on the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring, wherein the wiring layer in plan view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, wherein the high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region, wherein the plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively, and wherein an average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region. | 07-26-2012 |
| 20120205778 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a package structure and method for manufacturing the same. The package structure can minimize the area of the circuit board used for packaging, by stacking a passive element directly on a chip. The disclosed package structure comprises: a circuit board having a first surface, where a plurality of first connecting pads being disposed thereon; a chip unit having an active surface, a non-active surface and a plurality of conductive vias, while a plurality of second connecting pads and a plurality of electric pads being disposed on the active surface, and a plurality of third connecting pads being disposed on the non-active surface; a plurality of solder balls electrically connected with the first connecting pads and the second connecting pads; and a passive element being electrically connected with the third connecting pads. The passive element and the chip unit both electrically connect to the chip unit. | 08-16-2012 |
| 20120211864 | INDUCTOR - Parasitic capacitance between upper and lower adjacent wirings of an inductor using a multilayer wiring layer in an insulating film formed on a base substrate is reduced. An inductor is characterized by having one go-around of go-around wiring (A-B or B-C) formed in each of at least two of adjacent wiring layers of a plurality of wiring layers | 08-23-2012 |
| 20120217614 | POWER CONVERTOR DEVICE AND CONSTRUCTION METHODS - In one aspect, the present invention relates generally to integrated circuit (IC) packages and more specific to some embodiments of IC power convertor technologies. In particular, IC packages that have a high degree of scalability to handle high voltage or current levels, good heat dissipation properties, flexible adaptability to generate packages operable at a wide range of current levels and having a wide range of power adaptability, lends itself to rapid inexpensive prototyping, the ability to adapt various substrates and IC devices to one another without extensive retooling or custom designing of components, as well as other advantages. | 08-30-2012 |
| 20120223411 | STRIPED ON-CHIP INDUCTOR - Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters. | 09-06-2012 |
| 20120235275 | ON-CHIP ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to an on-chip electronic device and a method for manufacturing the same. The on-chip electronic device according to the present invention comprises a substrate, a porous layer, a plurality of magnetic bodies, and an electronic member layer. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of magnetic bodies is disposed in the plurality of voids, respectively; and the electronic member layer is disposed on one side of the porous layer, such as upper side of or lower sider of the porous layer. Because the plurality of magnetic bodies is used as the core of the inductance, the inductance is increased effectively and the area of the on-chip electronic device is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered. | 09-20-2012 |
| 20120241904 | SYMMETRICAL CENTER TAP INDUCTOR STRUCTURE - An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line. | 09-27-2012 |
| 20120248569 | INTERPOSER HAVING AN INDUCTOR - An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures. | 10-04-2012 |
| 20120248570 | ON CHIP INTEGRATED INDUCTOR - A semiconductor chip has an integrated inductor, manufactured during back end of line processing. In particular, a loop ( | 10-04-2012 |
| 20120261796 | DIE ARRANGEMENTS AND METHODS OF MANUFACTURING A DIE ARRANGEMENT - In various embodiments, a die arrangement may be provided. The die arrangement may include a die, at least one bond pad, at least one redistribution trace electrically connecting the die with the at least one bond, and at least one inductor enclosing the at least one bond pad and the at least one redistribution trace. | 10-18-2012 |
| 20120267756 | Semiconductor Package with Embedded Spiral Inductor - In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector. | 10-25-2012 |
| 20120286391 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit is provided. The semiconductor circuit includes a metal layer, a conductive layer disposed under the metal layer and a semiconductor device disposed under the conductive layer. The metal layer forms an inductor device. The semiconductor device is coupled to the inductor device. | 11-15-2012 |
| 20120292738 | Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit - A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant. | 11-22-2012 |
| 20120299150 | Power Semiconductor Module with Embedded Chip Package - A power semiconductor module includes a power semiconductor die, a metal substrate, a patterned metallization layer, a plurality of padless electrical connections, a plurality of vias and an inductor. The power semiconductor die has a top surface, an opposing bottom surface and a plurality of sides extending between the top and bottom surfaces. The metal substrate is attached to the bottom surface of the die. The patterned metallization layer is disposed above the top surface of the die. The plurality of padless electrical connections are at the top surface of the die and connect the patterned metallization layer to the die. The plurality of vias are disposed adjacent one or more of the sides of the die and electrically connected to the patterned metallization layer at a first end of the plurality of vias and to the metal substrate at a second end of the plurality of vias. | 11-29-2012 |
| 20120299151 | Semiconductor Device and Method of Forming RF Balun having Reduced Capacitive Coupling and High CMRR - A semiconductor device has an RF balun formed over a substrate. The RF balun includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device. A first capacitor is coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The first conductive trace is formed completely within the second conductive trace. The first conductive trace and second conductive trace can have an oval, circular, or polygonal shape separated by 50 micrometers. A second capacitor is coupled between the first and second ends of the second conductive trace. | 11-29-2012 |
| 20120319236 | INTEGRATED CIRCUIT INDUCTORS WITH INTERTWINED CONDUCTORS - An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance. | 12-20-2012 |
| 20120319237 | CORNER-ROUNDED STRUCTURES AND METHODS OF MANUFACTURE - Corner-rounded structures and methods of manufacture are provided. The method includes forming at least two conductive wires with rounded corners on a substrate. The method further includes forming a insulator film on the substrate and between the at least two conductive wires with the rounded corners. | 12-20-2012 |
| 20130001742 | SEMICONDUCTOR DEVICE - In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls. | 01-03-2013 |
| 20130009279 | INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS - Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits. | 01-10-2013 |
| 20130015554 | Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures - A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate. | 01-17-2013 |
| 20130015555 | Method of Forming an Inductor on a Semiconductor Wafer - A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad. | 01-17-2013 |
| 20130020675 | INDUCTIVE STRUCTURE FORMED USING THROUGH SILICON VIAS - An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV. | 01-24-2013 |
| 20130020676 | SOLENOID INDUCTOR FOR FREQUENCY SYNTHESIZER IN DIGITAL CMOS PROCESS - The present invention relates to a solenoid inductor for a frequency synthesizer in a digital CMOS process. The solenoid inductor includes: a plurality of wiring metals configured in a solenoid structure with a given width wherein the wiring metals are stacked at two side regions in a vertical direction; and wiring metal connection means connecting the stacked side regions of the individual wiring metals in a vertical direction, wherein a given number of lower layer wiring metals among the wiring metals are connected through corresponding wiring metal connection means so as to completely overlap. Hence, by using a solenoid inductor to implement a frequency synthesizer operating at high frequency bands of 4 to 5 GHz or higher in a digital CMOS process, a frequency synthesizer operating at several GHz frequencies, which has been realized only in an RF CMOS process, can be implemented. | 01-24-2013 |
| 20130032923 | Integrated Inductor - A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization. | 02-07-2013 |
| 20130043557 | VERTICALLY ORIENTED SEMICONDUCTOR DEVICE AND SHIELDING STRUCTURE THEREOF - The present disclosure involves a semiconductor device. The semiconductor device includes a substrate having a horizontal surface. The semiconductor device includes an interconnect structure formed over the horizontal surface of the substrate. The interconnect structure includes an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The interconnect structure includes a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members. | 02-21-2013 |
| 20130043558 | SEMICONDUCTOR DEVICE AND COMMUNICATION METHOD - A semiconductor device, includes a substrate with a first surface, a semiconductor chip disposed over the first surface of the substrate, the semiconductor chip including a first region and a second region, and an encapsulant resin formed over the first surface of the substrate and encapsulating the semiconductor chip. The encapsulant resin has a thickness that is less at the first region of the semiconductor chip than that at the second region. | 02-21-2013 |
| 20130056847 | SMALL SIZE AND FULLY INTEGRATED POWER CONVERTER WITH MAGNETICS ON CHIP - An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary. | 03-07-2013 |
| 20130056848 | INDUCTIVE LOOP FORMED BY THROUGH SILICON VIA INTERCONNECTION - The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips. | 03-07-2013 |
| 20130056849 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor and a second spiral inductor formed in the multilayer interconnect, and an interconnect substrate formed over the semiconductor chip and having a third spiral inductor and a fourth spiral inductor. The third spiral inductor overlaps the first spiral inductor in a plan view. The fourth spiral inductor overlaps the second spiral inductor in the plan view. The third spiral inductor and the fourth spiral inductor collectively include a line, the line being spirally wound in a same direction in the third spiral inductor and the fourth spiral inductor. | 03-07-2013 |
| 20130062729 | FORMING A FERROMAGNETIC ALLOY CORE FOR HIGH FREQUENCY MICRO FABRICATED INDUCTORS AND TRANSFORMERS - A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency. | 03-14-2013 |
| 20130062730 | ELECTRONIC SEMICONDUCTOR DEVICE WITH INTEGRATED INDUCTOR, AND MANUFACTURING METHOD - An embodiment of an electronic device includes first and second semiconductor bodies. The first semiconductor body houses a first conductive strip having a first end portion and a second end portion, and houses a first conduction terminal electrically coupled to the first end portion and facing a surface of the first semiconductor body. The second semiconductor body houses a second conductive strip having a third end portion and a fourth end portion, and houses a second conduction terminal electrically coupled to the third end portion and facing a surface of the second semiconductor body. The first and second semiconductor bodies are arranged relative to one another so that the respective surfaces face one another, and the first conduction terminal and the second conduction terminal are coupled to one another by means of a conductive element so as to form a loop of an inductor. | 03-14-2013 |
| 20130062731 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad. | 03-14-2013 |
| 20130069197 | Semiconductor Device and Method of Forming RF FEM with LC Filter and IPD Filter Over Substrate - A semiconductor device has a substrate and RF FEM formed over the substrate. The RF FEM includes an LC low-pass filter having an input coupled for receiving a transmit signal. A Tx/Rx switch has a first terminal coupled to an output of the LC filter. A diplexer has a first terminal coupled to a second terminal of the Tx/Rx switch and a second terminal for providing an RF signal. An IPD band-pass filter has an input coupled to a third terminal of the Tx/Rx switch and an output providing a receive signal. The LC filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The IPD filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The RF FEM substrate can be stacked over a semiconductor package containing an RF transceiver. | 03-21-2013 |
| 20130075859 | Semiconductor structure including guard ring - One or more embodiments related to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature. | 03-28-2013 |
| 20130075860 | METHOD FOR FABRICATING A THREE-DIMENSIONAL INDUCTOR CARRIER WITH METAL CORE AND STRUCTURE THEREOF - A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures. | 03-28-2013 |
| 20130075861 | Semiconductor structure including guard ring - One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature. | 03-28-2013 |
| 20130087884 | SILICON INTERPOSER INCLUDING BACKSIDE INDUCTOR - Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate. | 04-11-2013 |
| 20130093045 | VERTICALLY ORIENTED SEMICONDUCTOR DEVICE AND SHIELDING STRUCTURE THEREOF - The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature. | 04-18-2013 |
| 20130099352 | STRUCTURE AND METHOD FOR A HIGH-K TRANSFORMER WITH CAPACITIVE COUPLING - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer. | 04-25-2013 |
| 20130099353 | ESD PROTECTION DEVICE - An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer provided on a surface of the semiconductor substrate. An ESD protection circuit is provided on or in an outer layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post electrodes. First ends of the interlayer wiring lines disposed in the thickness direction are connected to the input/output electrodes disposed on the surface of the semiconductor substrate, and second ends of the interlayer wiring lines are connected to first ends of the in-plane wiring lines routed in plan view. Prismatic post electrodes are provided between second ends of the in-plane wiring lines and terminal electrodes. | 04-25-2013 |
| 20130105941 | SEMICONDUCTOR DEVICE INCLUDING IN WAFER INDUCTORS, RELATED METHOD AND DESIGN STRUCTURE | 05-02-2013 |
| 20130119511 | INDUCTOR HAVING BOND-WIRE AND MANUFACTURING METHOD THEREOF - The present application discloses an inductor including a substrate, a first conductive line and a second conductive line formed over the substrate, a passivation layer formed over the first and the second conductive lines, and a bond wire coupling an end of the first conductive line and an end of the second conductive line. At least a portion of the at least one bond wire is positioned above an upper surface of the passivation layer. The first conductive line, the bond wire, and the second conductive line are connected to form a coil. | 05-16-2013 |
| 20130127009 | DEFECTED GROUND PLANE INDUCTOR - An spiral inductor ( | 05-23-2013 |
| 20130127010 | INTEGRATED CIRCUIT INCLUDING A DIFFERENTIAL POWER AMPLIFIER WITH A SINGLE ENDED OUTPUT AND AN INTEGRATED BALUN - An integrated circuit, including, a die with an electronic circuit embedded thereon; wherein the electronic circuit includes a differential power amplifier and pads to electronically interface with the electronic circuit; a packaging encasing the die with contact pins to connect between the integrated circuit and external elements; wires connecting between the pads and the contact pins; a converter that includes capacitors and inductors to combine the outputs from the differential power amplifier to form a single ended output at one of the contact pins; wherein inherent inductance of some of the wires serve as the inductors of the converter. | 05-23-2013 |
| 20130134551 | INDUCTORS IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - An inductor in a semiconductor device may include a first interconnection line on a substrate; a second interconnection line on the first interconnection line; first and second common interconnection lines on the second interconnection line; a first via connecting a first end of the first interconnection line to a first end of the first common interconnection line; a second via connecting a second end of the first interconnection line to a second end of the second common interconnection line; a third via connecting a first end of the second interconnection line to the first end of the first common interconnection line; and a fourth via connecting a second end of the second interconnection line to the second end of the second common interconnection line. The first and second interconnection lines and the first and second common interconnection lines may extend in a direction parallel to a surface of the substrate. | 05-30-2013 |
| 20130134552 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series. | 05-30-2013 |
| 20130140671 | COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THREE-DIMENSIONALLY FORMED COMPONENTS - The present invention relates to a compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology. | 06-06-2013 |
| 20130140672 | VARIABLE INDUCTOR AND SEMICONDUCTOR DEVICE USING SAME - A variable inductor includes a spiral inductor, a loop conductor, and a switch for opening or short-circuiting an end of the loop conductor. The loop conductor is formed in a direction perpendicular to the spiral inductor and is used for adjusting the inductance value of the spiral inductor by opening or short-circuiting the end of the loop conductor by the switch. | 06-06-2013 |
| 20130147010 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 06-13-2013 |
| 20130147011 | SEMICONDUCTOR DEVICE - A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section. | 06-13-2013 |
| 20130154053 | INDUCTORS WITH THROUGH VIAS - A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate. | 06-20-2013 |
| 20130161785 | ON CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE - A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies. | 06-27-2013 |
| 20130168808 | MEMS POWER INDUCTOR WITH MAGNETIC LAMINATIONS FORMED IN A CRACK RESISTANT HIGH ASPECT RATIO STRUCTURE - Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants. | 07-04-2013 |
| 20130168809 | STRUCTURE AND METHOD FOR A TRANSFORMER WITH MAGNETIC FEATURES - The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors. | 07-04-2013 |
| 20130168810 | INTEGRATED CIRCUITS INCLUDING INDUCTORS - An integrated circuit includes a substrate having a surface and an inductor disposed over the surface of the substrate. The inductor includes a first conductive line disposed over the surface and first conductive structures disposed over and electrically coupled with the first conductive line. The inductor includes second conductive structures disposed over and electrically coupled with the first conductive structures. The inductor includes a second conductive line disposed over and electrically coupled with the second conductive structures. The inductor includes third conductive structures disposed over and electrically coupled with the first conductive line and at least one fourth conductive structure disposed over and electrically coupled with the third conductive structures. The inductor includes a third conductive line disposed over and electrically coupled with the at least one fourth conductive structure, the third conductive line extending substantially parallel to the second conductive line. | 07-04-2013 |
| 20130175664 | Power Management Module and Method of Manufacture - A power management module, provides an inductor including one or more electrical conductors disposed around a ferromagnetic ceramic element including one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.50 mol % throughout the ceramic element. | 07-11-2013 |
| 20130181323 | Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate - A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. | 07-18-2013 |
| 20130181324 | SEMICONDUCTOR DEVICE - A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit. | 07-18-2013 |
| 20130187255 | POWER INDUCTORS IN SILICON - Various methods and systems are provided for power inductors in silicon (PIiS) In one embodiment, a PIiS includes a magnetic core of magnetic material embedded in a silicon substrate, and a conductive winding having a plurality of turns, where adjacent turns of the conductive winding have a space therebetween, and where at least a portion of the magnetic core is encircled by the conductive winding In another embodiment, a DC to DC converter includes a PIiS, which includes a magnetic core of magnetic material embedded in a silicon substrate, a conductive winding having a plurality of turns, where at least a portion of the magnetic core is encircled by the conductive winding, and a cap layer of magnetic material disposed on at least one side of the silicon substrate The DC to DC converter also includes an integrated circuit mounted on the cap layer of the power inductor in silicon | 07-25-2013 |
| 20130193553 | High performance system-on-chip inductor using post passivation process - A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer. | 08-01-2013 |
| 20130207230 | ON-CHIP FERRITE BEAD INDUCTOR - A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes. | 08-15-2013 |
| 20130234285 | INDUCTOR ELEMENT, INDUCTOR ELEMENT MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE WITH INDUCTOR ELEMENT MOUNTED THEREON - An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer. | 09-12-2013 |
| 20130234286 | SEMICONDUCTOR DEVICE HAVING HIGH-FREQUENCY INTERCONNECT - Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view. The semiconductor device further includes dummy conductor patterns (first dummy conductor patterns) in the interconnect layer in which the high-frequency interconnect is disposed. | 09-12-2013 |
| 20130241032 | SEMICONDUCTOR DEVICE HAVING HIGH FREQUENCY WIRING AND DUMMY METAL LAYER AT MULTILAYER WIRING STRUCTURE - A semiconductor device includes a semiconductor substrate, a wiring layer provided over the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring. In a plan view, the wiring layer includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region. The high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region. The plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively. An average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region. | 09-19-2013 |
| 20130256833 | TRIPLE WELL ISOLATED DIODE AND METHOD OF MAKING - A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well. | 10-03-2013 |
| 20130277797 | Coil and Method of Manufacturing a Coil - A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening. | 10-24-2013 |
| 20130285197 | Semiconductor Devices and Methods of Manufacturing and Using Thereof - A semiconductor device includes at least one first semiconductor element and two interconnectors for electrically coupling the at least one first semiconductor element to external. A spacing between the two interconnectors corresponds to a size of a second semiconductor element. The second semiconductor element can be affixed between the two interconnectors. | 10-31-2013 |
| 20130285198 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a spiral-shaped inductor formed to include a metal wire; and a horseshoe-shaped inductor formed to include the metal wire. The horseshoe-shaped inductor is arranged such that an opening of the horseshoe-shaped inductor is disposed opposite to the spiral-shaped inductor. Accordingly, unnecessary wave (spurious) output from a transmitting unit can be reduced as small as possible. | 10-31-2013 |
| 20130299941 | INDUCTOR - An inductor is provided. The inductor includes first and second bonding pads on a semiconductor substrate, a lead pin on a board trace, a first bonding wire being configured to connect the first bonding pad and the lead pin, and a second bonding wire configured to connect the second bonding pad and the lead pin, the second bonding wire being connected to the first bonding wire in parallel. | 11-14-2013 |
| 20130307117 | Structure and Method for Inductors Integrated into Semiconductor Device Packages - A thin-contour semiconductor device with a solenoid and iron core integrated into the device package. The solenoid windings are constructed by a stripe-shaped layer portion, deposited on the chip surface, and an arced wire portion welded to the layer portion by low-cost standard wire bonding technique. The stripes are arrayed parallel to each other, spaced apart respective insulating gaps. The arced wires span from one stripe to the adjacent next stripe by bridging the gap and keeping the clock direction constant. The arced solenoid windings are then integrated into the encapsulating device package. The ferromagnetic core may be shaped as a ring to allow the formation of a strong and nearly homogeneous magnetic field inside the solenoid, providing reliable energy storage for power supply circuits. | 11-21-2013 |
| 20130320490 | INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING - A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions. | 12-05-2013 |
| 20130320491 | Semiconductor Device Having Features to Prevent Reverse Engineering - It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices. | 12-05-2013 |
| 20130320492 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - Disclosed herein is a substrate including: a base substrate; an insulating layer formed on an upper portion of the base substrate; a circuit layer formed in a form in which it is buried in the insulating layer; at least one electrode formed on upper portions of the circuit layer and the insulating layer and having a prominence and depression formed at a side thereof; and a dielectric layer formed in a form in which it surrounds the side of the electrode. | 12-05-2013 |
| 20130328163 | INDUCTOR DEVICE AND FABRICATION METHOD - Various embodiments provide inductor devices and fabrication methods. In one embodiment, an inductor device can include a first dielectric layer disposed on a semiconductor substrate; a first planar spiral wiring disposed on the first dielectric layer, and optionally one or more second planar spiral wirings disposed over the first planar spiral wiring. Each of the first and the optional second planar spiral wirings can include a first spiral metal wiring and a second spiral metal wiring connected to the first spiral metal wiring. The second spiral metal wiring can include at least two sub-metal-lines isolated with one another. | 12-12-2013 |
| 20130328164 | INDUCTOR DEVICE AND FABRICATION METHOD - Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel. | 12-12-2013 |
| 20130328165 | MICROFABRICATED MAGNETIC DEVICES AND ASSOCIATED METHODS - A magnetic device includes a semiconductor wafer, a spiral winding, and a magnetic core. The spiral winding forms a plurality of turns and is disposed in a channel of the semiconductor wafer. The magnetic core is disposed at least partially in the channel of the semiconductor wafer and at least partially surrounds the plurality of turns. A width of the spiral winding optionally varies such that a respective width of an edge turn is smaller than a respective width of a middle turn. The channel is formed, for example, by a method including (1) patterning a resist layer on the semiconductor wafer using a mask including angularly extending compensation features, and (2) anistropically etching the semiconductor wafer to form the channel. | 12-12-2013 |
| 20130328166 | Semiconductor Device and Method of Manufacture Thereof - A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled to the first coil, and an isolating intermediate layer between the first semiconductor chip and the second semiconductor chip. | 12-12-2013 |
| 20130341758 | CHIP INDUCTOR - Disclosed herein is a chip inductor. The chip inductor according to the present invention includes a substrate on which a through-hole is formed, a conductive coil that is formed on the substrate, an upper resin composite magnetic layer that is filled to surround the conductive coil so that a core is formed on a center portion of the substrate, a lower resin composite magnetic layer that is formed on a bottom portion of the substrate, and an external electrode that is formed on both sides of the upper and lower resin composite magnetic layers. | 12-26-2013 |
| 20140001597 | Voids in Interconnect Structures and Methods for Forming the Same | 01-02-2014 |
| 20140021582 | CONFIGURABLE PASSIVE COMPONENTS - A wafer of passive components is diced to leave a flat passive chip. The flat passive chip has bond pads for passive components on a same side of the flat passive chip. The flat passive chip is stacked onto an active chip. The passive components are wirebonded together to connect the passive components in series or parallel, resulting in the flat passive chip having an overall passive characteristic equal to a target characteristic. | 01-23-2014 |
| 20140027879 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT - One aspect of the invention relates to a semiconductor component with a semiconductor body with a top side and with a bottom side. A first coil that is monolithically integrated with the semiconductor body is arranged distant from the bottom side and comprises N first windings, wherein N≧1. The first coil has a first coil axis that extends in a direction different from a surface normal of the bottom side. | 01-30-2014 |
| 20140027880 | INTEGRATED INDUCTOR FOR INTEGRATED CIRCUIT DEVICES - A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described. | 01-30-2014 |
| 20140035097 | SEMICONDUCTOR PACKAGE HAVING AN ANTENNA AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment. | 02-06-2014 |
| 20140048906 | Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters. | 02-20-2014 |
| 20140061853 | PLATED LAMINATION STRUCTURES FOR INTEGRATED MAGNETIC DEVICES - Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure. | 03-06-2014 |
| 20140061854 | SMALL SIZE AND FULLY INTEGRATED POWER CONVERTER WITH MAGNETICS ON CHIP - An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary. | 03-06-2014 |
| 20140070365 | SEMICONDUCTOR DEVICES WITH IMPEDANCE MATCHING-CIRCUITS, AND METHODS OF MANUFACTURE THEREOF - Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices. | 03-13-2014 |
| 20140084414 | VERTICAL MEANDER INDUCTOR FOR SMALL CORE VOLTAGE REGULATORS - Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography. | 03-27-2014 |
| 20140084415 | Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer - A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die. | 03-27-2014 |
| 20140097514 | Semiconductor Package and Method for Fabricating the Same - A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material. | 04-10-2014 |
| 20140097515 | COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THREE-DIMENSIONALLY FORMED COMPONENTS - A compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A SiN protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology. | 04-10-2014 |
| 20140103486 | ROLLED-UP INDUCTOR STRUCTURE FOR A RADIOFREQUENCY INTEGRATED CIRCUIT (RFIC) - A rolled-up inductor structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis. The multilayer sheet comprises a conductive pattern layer on a strain-relieved layer, and the conductive pattern layer comprises at least one conductive strip having a length extending in a rolling direction. The at least one conductive strip thereby wraps around the longitudinal axis in the rolled configuration. The conductive pattern layer may also comprise two conductive feed lines connected to the conductive strip for passage of electrical current therethrough. The conductive strip serves as an inductor cell of the rolled-up inductor structure. | 04-17-2014 |
| 20140103487 | SEMICONDUCTOR DEVICE - A semiconductor device, includes a first substrate having a main surface and a rear surface opposing to the main surface, a first circuit including a plurality of transistors formed over the main surface, a first insulating film formed over the main surface to cover the first circuit, a first inductor formed in the first insulating film over the main surface, the first inductor being electrically connected to the first circuit; and a bonding pad formed over the main surface, the bonding pad being located at a first area, the first inductor being located at a second area, the first area being different from the second area in a plan view, and a second substrate having a main surface, a rear surface opposing to the main surface and a second inductor formed over the main surface. | 04-17-2014 |
| 20140110820 | PASSIVE COMPONENT AS THERMAL CAPACITANCE AND HEAT SINK - Representative implementations of devices and techniques provide improved thermal performance of a chip die disposed within a layered printed circuit board (PCB). Passive components may be strategically located on one or more surfaces of the PCB. The passive components may be arranged to conduct heat generated by the chip die away from the chip die. | 04-24-2014 |
| 20140110821 | FOLDED CONICAL INDUCTOR - A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive track and a first inner-spiral electrically conductive track separated from the first outer-spiral electrically conductive track by a first dielectric material. A second spiral structure, located on a second metal layer, having a second outer-spiral electrically conductive track and a second inner-spiral electrically conductive track separated from the second outer-spiral electrically conductive track by a second dielectric material may also be provided. The first outer-spiral electrically conductive track may be electrically coupled to the second outer-spiral electrically conductive track and the first inner-spiral electrically conductive track may be electrically coupled to the second inner-spiral electrically conductive track. The first outer-spiral conductive track is laterally offset relative to the second outer-spiral conductive track and the first inner-spiral conductive track is laterally offset relative to the second inner-spiral conductive track. | 04-24-2014 |
| 20140110822 | Semiconductor Device Including Magnetically Coupled Monolithic Integrated Coils - A semiconductor device includes a first coil that is monolithically integrated in a first portion of a semiconductor body and that includes a first winding wrapping around a first core structure. A second coil is monolithically integrated in a second portion of the semiconductor body and includes a second winding wrapping around the second core structure. The first and second coils are magnetically coupled with each other. An insulator frame in the semiconductor body surrounds the first portion and excludes the second portion. High dielectric strength between the first and the second coils is achieved without patterning a backside metallization for connecting the turns of the windings and without being restricted to thin substrates. | 04-24-2014 |
| 20140117494 | INDUCTOR STRUCTURE WITH PRE-DEFINED CURRENT RETURN - An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit. | 05-01-2014 |
| 20140117495 | SWITCH CIRCUIT PACKAGE MODULE - A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes sub micro-switch elements. The capacitor unit is arranged at a periphery of the semiconductor switch unit or stacked on a surface of the semiconductor switch unit, such that impedances of commutation loops between the capacitor unit and the sub micro-switch elements are close to or the same with each other. | 05-01-2014 |
| 20140117496 | SEMICONDUCTOR DEVICE HAVING GROUND SHIELD STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor devices having a ground shield structure and methods for their formation are provided herein. An exemplary semiconductor device can include a substrate, a ground ring, a ground shield, an electronic device, and/or an insulation layer. The ground ring can be disposed over the substrate. The ground shield can be disposed over the substrate and surrounded by the ground ring. The ground shield can include a plurality of coaxial conductive wirings and a metal wire passing through the plurality of coaxial conductive wirings along a radial direction. The metal wire can be connected to the ground ring. The electronic device can be disposed over the ground shield. The insulation layer can be disposed between the ground shield and the electronic device. | 05-01-2014 |
| 20140138792 | HYBRID TRANSFORMER STRUCTURE ON SEMICONDUCTOR DEVICES - Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer. | 05-22-2014 |
| 20140151846 | SHIELDING SILICON FROM EXTERNAL RF INTERFERENCE - Consistent with an example embodiment, there is an integrated circuit device (IC) built on a substrate of a thickness. The IC comprises an active device region of a shape, the active device region having a topside and an underside. Through silicon vias (TSVs) surround the active device region, the TSVs having a depth defined by the substrate thickness. On the underside of and having the shape of the active device region, is an insulating layer. A thin-film conductive shield is on the insulating layer, the conductive shield is in electrical contact with the TSVs. | 06-05-2014 |
| 20140159196 | Through Substrate Features in Semiconductor Substrates - Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate. | 06-12-2014 |
| 20140167216 | LOW-PROFILE CHIP PACKAGE WITH MODIFIED HEAT SPREADER - An integrated circuit system includes a heat spreader that is thermally coupled to a semiconductor chip and has a cavity or opening formed in the heat spreader. The cavity or opening is positioned so that capacitors and/or other passive components mounted to the same packaging substrate as the semiconductor chip are at least partially disposed in the cavity or opening. Because the passive components are disposed in the cavity or opening, the integrated circuit system has a reduced package thickness. | 06-19-2014 |
| 20140167217 | PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER - Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed. | 06-19-2014 |
| 20140167218 | CIRCUIT CONFIGURATION AND MANUFACTURING PROCESSES FOR VERTICAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) AND EMI FILTER - A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter. | 06-19-2014 |
| 20140167219 | Thick On-Chip High-Performance Wiring Structures - Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire. | 06-19-2014 |
| 20140175602 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device are improved. A semiconductor device has a laminated insulating film formed above a lower-layer inductor. This laminated insulating film includes a first polyimide film, and a second polyimide film formed on the first polyimide film and having a second step between the first polyimide film and the second polyimide film. An upper-layer inductor is formed on the laminated insulating film. Since such a laminated structure of the first and second polyimide films is adopted, the film thickness of the insulating film between the lower-layer and upper-layer inductors can be increased, so that withstand voltage can be improved. Further, the occurrence of a depression or peeling-off due to defective exposure can be reduced, and step disconnection of a Cu (copper) seed layer or a plating defect due to the step disconnection can also be reduced. | 06-26-2014 |
| 20140183690 | Guard Ring Design for Maintaining Signal Integrity - A structure includes a metal feature, and a passivation layer having a portion overlapping the metal feature. The passivation layer includes a non-low-k dielectric material. A polymer layer is over the passivation layer. A Post-Passivation Interconnect (PPI) extends into the polymer layer to electrically couple to the metal feature. A guard ring includes a second PPI, wherein the guard ring is electrically grounded. The second PPI substantially encircles the first PPI. | 07-03-2014 |
| 20140183691 | RESONANT CLOCKING FOR THREE-DIMENSIONAL STACKED DEVICES - Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit. | 07-03-2014 |
| 20140183692 | TECHNIQUES FOR FAST RESONANCE CONVERGENCE - Some methods provide an electronic design file, which includes an integrated circuit (IC) component that is operably coupled to a package component. The IC component and package component collectively form a resistor inductor capacitor (RLC) resonant circuit. The method also provides a damping component in the electronic design file. This damping component is configured to reduce a pre-resonant time during which energy exchanged in the RLC resonant circuit approaches a steady-state, and thereby speeds simulation time. | 07-03-2014 |
| 20140191361 | ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS - A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip. | 07-10-2014 |
| 20140191362 | ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS - A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip. | 07-10-2014 |
| 20140191363 | EXTERNAL STORAGE DEVICE AND METHOD OF MANUFACTURING EXTERNAL STORAGE DEVICE - An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer. | 07-10-2014 |
| 20140203397 | Methods and Apparatus for Inductors and Transformers in Packages - Methods and apparatus for forming a semiconductor device package with inductors and transformers using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top die and a bottom die, or between a die and an interposer. An inductor can be formed by a redistribution layer within a bottom device and a micro-bump line above the bottom device connected to the RDL. The inductor may be a symmetric inductor, a spiral inductor, a helical inductor which is a vertical structure, or a meander inductor. A pair of inductors with micro-bump lines can form a transformer. | 07-24-2014 |
| 20140203398 | Integrated Magnetic Core Inductors with Interleaved Windings - A coupled inductor topology for a thin-film magnetic core power inductor that enables efficient integrated power conversion. Coupled magnetic core inductors with interleaved windings inductors comprise magnetic films and partially or fully interleaved conductors. Methods described herein are suitable for integration into monolithic, chip stacking fabrication or other traditional semiconductor device fabrication techniques and equipment. Soft ferromagnetic materials exhibiting high permeability and low coercivity are deposited using thin-film techniques. A plurality of electrical conductors surround at least one ferromagnetic core giving rise to two or more windings. Windings are coupled to one another through magnetic core(s). Windings are used to control permeability, inductance and magnetic saturation, finding particular utility in high magnetic flux applications. | 07-24-2014 |
| 20140203399 | Integrated Circuits with Magnetic Core Inductors and Methods of Fabrications Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil. | 07-24-2014 |
| 20140210044 | SEMICONDUCTOR DEVICE HAVING INDUCTOR - A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines. | 07-31-2014 |
| 20140210045 | INDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An inductor device includes an insulation layer, an inductor, fixed electrodes, and a movable electrode. The inductor is formed on the insulation layer. The fixed electrodes are provided in positions which do not overlap with the inductor in a planar view. The movable electrode overlaps with the inductor and the fixed electrodes in the planar view, and is separated from the inductor and the fixed electrodes. Further, the movable electrode includes first openings. | 07-31-2014 |
| 20140210046 | SEMICONDUCTOR DEVICE HAVING HIGH FREQUENCY WIRING AND DUMMY METAL LAYER AT MULTILAYER WIRING STRUCTURE - A semiconductor device includes a semiconductor substrate, and a multilayer wiring layer provided over the semiconductor substrate. The multilayer wiring layer includes an inductor wiring formed in one wiring layer, a plurality of first dummy metals formed in the same layer as the inductor and provided inside the inductor, a plurality of second dummy metals formed in a same layer as the inductor and provided outside the inductor, a plurality of third dummy metals formed in a layer lower than the one wiring layer including the inductor, and provided inside the inductor in a plan view, a plurality of fourth dummy metals formed in a same layer as the plurality of third dummy metals and provided outside the inductor in the plan view, and a plurality of fifth dummy metals formed in the same layer as the plurality of third dummy metals and provided to overlap with the inductor. | 07-31-2014 |
| 20140210047 | SEMICONDUCTOR DEVICE - A semiconductor device including: first and second semiconductor chips mounted on a base substrate; a third semiconductor chip, which is mounted on the base substrate, and outputs control signals controlling operations of the first and second semiconductor chips; a first transmission transformer, which is mounted on the base substrate, and has a reception-side terminal connected to the third semiconductor chip and a transmission-side terminal connected to the first semiconductor chip; and a second transmission transformer, which is mounted on the base substrate, and has a reception-side terminal connected to the third semiconductor chip and a transmission-side terminal connected to the second semiconductor chip, wherein the control signals are transmitted from the third semiconductor chip to the first semiconductor chip and the second semiconductor chip individually through the first transmission transformer and the second transmission transformer. | 07-31-2014 |
| 20140217546 | HELICAL SPIRAL INDUCTOR BETWEEN STACKING DIE - The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies. | 08-07-2014 |
| 20140217547 | SEMICONDUCTOR PACKAGE WITH AIR CORE INDUCTOR (ACI) AND MAGNETIC CORE INDUCTOR (MCI) - Semiconductor die packaged with air core inductors (ACIs) and magnetic core inductors (MCIs), or with multiple MCIs, are described. In a first example, a semiconductor package includes a semiconductor die, one or more air core inductors (ACIs) coupled to the semiconductor die, and one or more magnetic core inductors (MCIs) coupled to the semiconductor die. In a second example, a semiconductor package includes a semiconductor die, a first magnetic core inductor (MCI) coupled to the semiconductor die and having a first saturation current, and a second MCI coupled to the semiconductor die and having a second, different, saturation current. | 08-07-2014 |
| 20140231955 | Process of Ultra Thick Trench Etch with Multi-Slope Profile - The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer. | 08-21-2014 |
| 20140231956 | INTEGRATED CIRCUIT INDUCTOR - An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer. | 08-21-2014 |
| 20140239442 | ELECTROLESS PLATED MATERIAL FORMED DIRECTLY ON METAL - A method for forming magnetic conductors includes forming a metal structure on a substrate. Plating surfaces are prepared on the metal structure for electroless plating by at least one of: masking surfaces of the metal structure to prevent electroless plating on masked surfaces and/or activating a surface of the metal structure. Magnetic material is electrolessly plated directly on the plating surfaces to form a metal and magnetic material structure. | 08-28-2014 |
| 20140239443 | ELECTROLESS PLATED MATERIAL FORMED DIRECTLY ON METAL - A method for forming magnetic conductors includes forming a metal structure on a substrate. Plating surfaces are prepared on the metal structure for electroless plating by at least one of: masking surfaces of the metal structure to prevent electroless plating on masked surfaces and/or activating a surface of the metal structure. Magnetic material is electrolessly plated directly on the plating surfaces to form a metal and magnetic material structure. | 08-28-2014 |
| 20140246753 | HIGH QUALITY FACTOR INDUCTOR IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) - Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls. | 09-04-2014 |
| 20140252540 | Semiconductor Device and Method of Manufacturing Thereof - A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes. | 09-11-2014 |
| 20140252541 | SYSTEMS AND METHODS FOR POWER TRAIN ASSEMBLIES - A power train assembly is provided. The power train assembly includes a component package including a first transistor having a first gate, a first drain, and a first source, a second transistor having a second gate, a second drain, and a second source, and a thermal pad configured to dissipate heat generated in the component package, wherein the thermal pad is electrically coupled to the first source and the second drain. The power train assembly further includes a printed circuit board (PCB) electrically coupled to the component package, and an electrical component electrically coupled directly to the thermal pad, wherein the electrical component is external to the component package. | 09-11-2014 |
| 20140252542 | Structure and Method for an Inductor With Metal Dummy Features - The present disclosure provides a semiconductor device. The semiconductor device includes an inductor formed on a substrate and configured to be operable with a current of a frequency; and dummy metal features configured between the inductor and the substrate, the dummy metal features having a first width less than 2 times of a skin depth associated with the frequency. | 09-11-2014 |
| 20140264732 | MAGNETIC CORE INDUCTOR (MCI) STRUCTURES FOR INTEGRATED VOLTAGE REGULATORS - Semiconductor packages including magnetic core inductor (MCI) structures for integrated voltage regulators are described. In an example, a semiconductor package includes a package substrate and a semiconductor die coupled to a first surface of the package substrate. The semiconductor die has a first plurality of metal-insulator-metal (MIM) capacitor layers thereon. The semiconductor package also includes a magnetic core inductor (MCI) die coupled to a second surface of the package substrate. The MCI die includes one or more slotted inductors and has a second plurality of MIM capacitor layers thereon. | 09-18-2014 |
| 20140264733 | DEVICE WITH INTEGRATED PASSIVE COMPONENT - Semiconductor devices and methods for forming a semiconductor device are presented. The semiconductor device includes a die which includes a die substrate having first and second major surfaces. The semiconductor device includes a passive component disposed below the second major surface of the die substrate. The passive component is electrically coupled to the die through through silicon via (TSV) contacts. | 09-18-2014 |
| 20140264734 | Inductor With Magnetic Material - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 09-18-2014 |
| 20140264735 | Inductor System and Method - A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed. | 09-18-2014 |
| 20140264736 | Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate - A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. | 09-18-2014 |
| 20140264737 | COMPONENT-EMBEDDED SUBSTRATE - A component-embedded substrate having a multilayer substrate formed by laminating a plurality of thermoplastic sheets in a predetermined direction, an internal component provided in the multilayer substrate, and a surface-mount component mounted on a surface of the multilayer substrate using bumps. The surface-mount component, when viewed in a plan view in the predetermined direction, is positioned so as to cross an outline of the internal component, with the bumps on the surface-mount component located 50 μm or more from the outline of the internal component. | 09-18-2014 |
| 20140264738 | FOLDED CONICAL INDUCTOR - A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive track and a first inner-spiral electrically conductive track separated from the first outer-spiral electrically conductive track by a first dielectric material. A second spiral structure, located on a second metal layer, having a second outer-spiral electrically conductive track and a second inner-spiral electrically conductive track separated from the second outer-spiral electrically conductive track by a second dielectric material may also be provided. The first outer-spiral electrically conductive track may be electrically coupled to the second outer-spiral electrically conductive track and the first inner-spiral electrically conductive track may be electrically coupled to the second inner-spiral electrically conductive track. The first outer-spiral conductive track is laterally offset relative to the second outer-spiral conductive track and the first inner-spiral conductive track is laterally offset relative to the second inner-spiral conductive track. | 09-18-2014 |
| 20140284761 | INTEGRATED INDUCTOR AND INTEGRATED INDUCTOR FABRICATING METHOD - The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of through silicon vias (TSVs), and an inductor. The TSVs are formed in the semiconductor substrate and arranged in a specific pattern, and the TSVs are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of TSVs in the semiconductor substrate and arranging the TSVs in a specific pattern; filling the TSVs with a metal material to form a PGS. forming an inductor above the semiconductor substrate. | 09-25-2014 |
| 20140284762 | INTEGRATED INDUCTOR AND INTEGRATED INDUCTOR FABRICATING METHOD - The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of deep trenches, and an inductor. The deep trenches are formed in the semiconductor substrate and arranged in a specific pattern, and the deep trenches are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of deep trenches in the semiconductor substrate and arranging the deep trenches in a specific pattern; filling the deep trenches with a metal material to form a patterned ground shield (PGS); and forming an inductor above the semiconductor substrate. | 09-25-2014 |
| 20140284763 | INTEGRATED INDUCTOR AND INTEGRATED INDUCTOR FABRICATING METHOD - The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, an inductor, and a redistribution layer (RDL). The inductor is formed above the semiconductor substrate. The RDL is formed above the inductor and has a specific pattern to form a patterned ground shield (PGS). The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming an inductor above the semiconductor substrate; and forming redistribution layer (RDL) having a specific pattern above the inductor to form a patterned ground shield (PGS). | 09-25-2014 |
| 20140299964 | ON-CHIP INDUCTOR USING REDISTRIBUTION LAYER AND DUAL-LAYER PASSIVIATION - A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it. | 10-09-2014 |
| 20140312457 | INTEGRATED CIRCUIT CHIP WITH DISCONTINUOUS GUARD RING - An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap. | 10-23-2014 |
| 20140312458 | METHODS AND APPARATUS RELATED TO AN IMPROVED PACKAGE INCLUDING A SEMICONDUCTOR DIE - In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar. | 10-23-2014 |
| 20140312459 | VERTICAL MEANDER INDUCTOR FOR SMALL CORE VOLTAGE REGULATORS - Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography. | 10-23-2014 |
| 20140319652 | HIGH QUALITY FACTOR FILTER IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) INTEGRATED DEVICE - Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die. | 10-30-2014 |
| 20140327107 | Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench in Substrate - A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties. | 11-06-2014 |
| 20140327108 | NOISE CANCELLATION FOR A MAGNETICALLY COUPLED COMMUNICATION LINK UTILIZING A LEAD FRAME - An integrated circuit package includes an encapsulation and a lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame includes a first conductor having a first conductive loop and a third conductive loop disposed within the encapsulation. The third conductive loop is wound in a direction relative to the first conductive loop such that the first conductive loop is coupled out of phase with the third conductive loop. The lead frame also includes a second conductor galvanically isolated from the first conductor. The second conductor includes a second conductive loop disposed within the encapsulation proximate to the first conductive loop to provide a communication link between the first and second conductors. | 11-06-2014 |
| 20140332925 | COMPOSITE RECONSTITUTED WAFER STRUCTURES - A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component. | 11-13-2014 |
| 20140346634 | ON-CHIP INDUCTORS WITH REDUCED AREA AND RESISTANCE - An integrated circuit that includes an on-chip inductor wrapped around an interface pad. On-chip inductors are arranged around an interface pad to reduce the area occupied by the inductor. Furthermore, arranging the on-chip inductors in an upper level metal layer, such us the redistribution layer (RDL), the top metal interconnect layer (MTop), or the second-to-top metal interconnect layer (MTop-1) reduces the on-chip inductor parasitic resistance, reducing the loss of signal. | 11-27-2014 |
| 20140346635 | SEMICONDUCTOR MODULE AND DRIVING DEVICE FOR SWITCHING ELEMENT - A semiconductor module includes: a semiconductor element; first and second main current passages for energizing the semiconductor element, the first and second main current passages being opposed to each other in such a manner that a first energization direction of the first main current passage is opposite to a second energization direction of the second main current passage, or an angle between the first energization direction and the second energization direction is an obtuse angle; and a coil unit sandwiched between the first and second main current passages. The coil unit includes a coil, which generates an induced electromotive force when a magnetic flux interlinks with the coil, the magnetic flux being generated when current flows through the first and second main current passages. | 11-27-2014 |
| 20140346636 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin. | 11-27-2014 |
| 20140353798 | Vertically Oriented Semiconductor Device and Shielding Structure Thereof - The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature. | 12-04-2014 |
| 20140361401 | PATTERNED GROUND SHIELD STRUCTURES AND SEMICONDUCTOR DEVICES - A patterned ground shield structure is provided. The patterned ground shield structure includes a substrate having a dielectric layer. The patterned ground shield structure also includes a plurality of conductive rings having a plurality of sub conductive rings in the dielectric layer. Further, the patterned ground shield structure includes an interconnection line connecting with all of the sub conductive rings in the dielectric layer. Further, the patterned ground shield structure also includes a ground ring connecting with the interconnection line. | 12-11-2014 |
| 20140361402 | INTEGRATED CIRCUIT PACKAGE WITH PRINTED CIRCUIT LAYER - An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die. | 12-11-2014 |
| 20140374875 | 3D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 12-25-2014 |
| 20140374876 | SEMICONDUCTOR DEVICE HAVING AN INDUCTOR - A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor. | 12-25-2014 |
| 20150028448 | Chip Package with Embedded Passive Component - A chip package includes an electrically conducting chip carrier and at least one first semiconductor chip attached to the electrically conducting chip carrier. The chip package further includes a passive component. The electrically conducting chip carrier, the at least one first semiconductor chip, and the passive component are embedded in an insulating laminate structure. | 01-29-2015 |
| 20150035116 | SEMICONDUCTOR DEVICE WITH CIRCUITS CONNECTED TO EACH OTHER IN CONTACTLESS MANNER - In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls. | 02-05-2015 |
| 20150041952 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer. | 02-12-2015 |
| 20150041953 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a common mode filter monolithically integrated with a protection device. The common mode filter may be composed of first, second, third, and fourth coils, wherein each coil has first and second terminals and the first coil is magnetically coupled to the second coil and the third coil is magnetically coupled to the fourth coil. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the third coil. An energy storage element has a terminal coupled to the second and first terminals of the first and second coils, respectively. Another embodiment includes monolithically integrating a common mode filter with a protection device and monolithically integrating a metal-insulator-metal capacitor with the common mode filter. | 02-12-2015 |
| 20150041954 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component, includes a common mode filter monolithically integrated with a protection device. The common mode filter includes a plurality of coils and the protection device has a terminal coupled to a first coil and another terminal coupled to a second coil. | 02-12-2015 |
| 20150048480 | INTEGRATED PASSIVE DEVICE (IPD) ON SUBTRATE - Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer. | 02-19-2015 |
| 20150048481 | SEMICONDUCTOR DEVICE - To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. | 02-19-2015 |
| 20150054124 | INDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed. | 02-26-2015 |
| 20150054125 | CHIP, CHIP ARRANGEMENT AND METHOD FOR PRODUCING A CHIP - Various embodiments provide a chip. The chip has a carrier, an integrated circuit formed above the carrier, and an energy storage element. The energy storage element has a first electrode and a second electrode and is used to supply the integrated circuit with electrical energy. The carrier, the integrated circuit and the energy storage element are monolithically formed, the first electrode being formed from the carrier. | 02-26-2015 |
| 20150069572 | Multilayer High Voltage Isolation Barrier in an Integrated Circuit - A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil formed in one or more dielectric laminate layers of the substrate, a second inductor coil formed in one or more dielectric laminate layers of the substrate, and an isolation barrier comprising two or more dielectric laminate layers of the multilayer substrate positioned between the first inductor coil and the second inductor coil. The transformer may be mounted on a lead frame along with one or more integrated circuits and molded into a packaged isolation device. | 03-12-2015 |
| 20150084158 | THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME - The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. | 03-26-2015 |
| 20150097267 | INDUCTOR STRUCTURE WITH MAGNETIC MATERIAL AND METHOD FOR FORMING THE SAME - Embodiments of mechanisms of forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer over the first metal layer. The inductor structure further includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a top surface, a bottom surface and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points. | 04-09-2015 |
| 20150097268 | INDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - An inductor structure includes a substrate, a protection layer, a patterned first conductive layer, copper bumps, a passivation layer, a diffusion barrier layer, and an oxidation barrier layer. The protection layer is located on the substrate. The bond pads of the substrate are respectively exposed through protection layer openings. The first conductive layer is located on the surfaces of the bond pads and the protection layer adjacent to the protection layer openings. The copper bumps are located on the first conductive layer. The passivation layer is located on the protection layer and the copper bumps. At least one of the copper bumps is exposed through a passivation layer opening. The diffusion barrier layer is located on the copper bump that is exposed through the passivation layer opening. The oxidation barrier layer is located on the diffusion barrier layer. | 04-09-2015 |
| 20150108603 | SEMICONDUCTOR DEVICE WITH PATTERNED GROUND SHIELDING - Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit. | 04-23-2015 |
| 20150115402 | INDUCTIVE CAPACITIVE STRUCTURE AND METHOD OF MAKING THE SAME - An inductive capacitive structure including a first substrate, a first conductive line over the first substrate, a first shielding layer over the first substrate and a second substrate over the first substrate. | 04-30-2015 |
| 20150115403 | TOROID INDUCTOR IN AN INTEGRATED DEVICE - Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor. | 04-30-2015 |
| 20150115404 | INTERCONNECTION BETWEEN INDUCTOR AND METAL-INSULATOR-METAL (MIM) CAPACITOR - Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal-insulator-metal (MIM) capacitor formed on a substrate. The semiconductor device structure also includes an inductor formed on the MIM capacitor. The semiconductor device structure further includes a via formed between the MIM capacitor and the inductor, and the via is formed in a plurality of dielectric layers, and the dielectric layers comprise an etch stop layer. | 04-30-2015 |
| 20150115405 | WIRELESS INTERCONNECTS IN AN INTERPOSER - Some implementations provide an interposer that includes a substrate, a first passive device in the substrate, and a second passive device. The first passive device includes a first set of through substrate vias (TSVs) in the substrate. The second passive device is configured to wirelessly couple to the first passive device. In some implementations, the second passive device includes a second set of through substrate vias (TSVs) in the substrate. In some implementations, the second passive device is configured to inductively couple to the first passive device. In some implementations, the first passive device is a first inductor and the second passive device is a second inductor. In some implementations, the interposer further includes a first set of interconnects coupled to the first set of TSVs, and a second set of interconnects coupled to the second set of TSVs. | 04-30-2015 |
| 20150115406 | SEMICONDUCTOR STRUCTURE - The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device. | 04-30-2015 |
| 20150130020 | SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. | 05-14-2015 |
| 20150130021 | SOLONOID INDUCTOR IN A SUBSTRATE - Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings. | 05-14-2015 |
| 20150130022 | Semiconductor Device - In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction. | 05-14-2015 |
| 20150137313 | Coil Arrangement with Metal Filling - Devices, methods and production devices that relate to the forming of a coil on a semiconductor substrate are provided. Arranged within the coil is a metal filling, for example with a density of less than 20%. | 05-21-2015 |
| 20150137314 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member. | 05-21-2015 |
| 20150318245 | SEMICONDUCTOR DEVICE - On a semiconductor substrate, coils CL | 11-05-2015 |
| 20150318248 | Integrated Circuits Including Magnetic Devices, And Associated Methods - An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is, for example, included in an integrated electronic assembly. | 11-05-2015 |
| 20150340338 | CONDUCTOR DESIGN FOR INTEGRATED MAGNETIC DEVICES - An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein. | 11-26-2015 |
| 20150340422 | METHOD OF MANUFACTURING A MICRO-FABRICATED WAFER LEVEL INTEGRATED INDUCTOR OR TRANSFORMER FOR HIGH FREQUENCY SWITCH MODE POWER SUPPLIES - A method of manufacturing an inductor on a wafer level process that can operate at 20 MHz with good efficiency and a high inductance density is disclosed, wherein the inductor design allows high frequency operation, low RDSON values and high efficiency. | 11-26-2015 |
| 20150340423 | SEMICONDUCTOR DEVICE HAVING INDUCTOR - A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines. | 11-26-2015 |
| 20150340424 | VERTICAL MEANDER INDUCTOR FOR SMALL CORE VOLTAGE REGULATORS - Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography. | 11-26-2015 |
| 20150349048 | SEMICONDUCTOR DEVICE AND PROCESS OF MAKING THE SAME - A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor. | 12-03-2015 |
| 20150357295 | DIELECTRIC REGION IN A BULK SILICON SUBSTRATE PROVIDING A HIGH-Q PASSIVE RESONATOR - Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in < | 12-10-2015 |
| 20150364417 | INTEGRATED CIRCUIT WITH GUARD RING - An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor. | 12-17-2015 |
| 20150364418 | CIRCUITS INCORPORATING INTEGRATED PASSIVE DEVICES HAVING INDUCTANCES IN 3D CONFIGURATIONS AND STACKED WITH CORRESPONDING DIES - A circuit including: a die a first substrate and at least one active device; an integrated passive device including a first layer, a second substrate, a second layer and an inductance; and a third layer. The inductance includes vias and is an electrostatic discharge inductance. The vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars. The pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack. | 12-17-2015 |
| 20150364532 | INDUCTOR FORMED ON A SEMICONDUCTOR SUBSTRATE - An inductor formed on a semiconductor substrate includes a semiconductor substrate, an inductor structure formed on the semiconductor substrate, and a plurality of slice structures formed in the semiconductor substrate. An extending direction of the slice structures is perpendicular to a surface of the semiconductor substrate. The slice structures are overlapped by the inductor. | 12-17-2015 |
| 20150371915 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained. | 12-24-2015 |
| 20150372073 | Coil and Method of Manufacturing a Coil - A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening. | 12-24-2015 |
| 20160027665 | DEVICE AND METHOD FOR IMPROVING RF PERFORMANCE - A semiconductor device and method of fabricating the semiconductor device are provided. The semiconductor device includes a first substrate including a front-end device containing a transistor, a radio frequency (RF) device and a first interconnect structure, and a second substrate containing a cavity disposed at a location corresponding to a location of the RF device. The first substrate and the second substrate are bonded together such that the first surface of the first substrate is facing the cavity in the second substrate, and the cavity is over the RF device. Because of the cavity, the distance between the second substrate and the RF device is relatively large so that the second substrate has less impact on the performance of the RF device, thereby improving the performance of the semiconductor device. | 01-28-2016 |
| 20160027732 | SEMICONDUCTOR DEVICE - Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL | 01-28-2016 |
| 20160031705 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a bottom substrate, wherein a front-end device including a microelectromechanical systems (MEMS) device and an inductor is disposed on the bottom substrate, and a top substrate bonded to the bottom substrate so as form a cavity enclosing the front-end device. The semiconductor device further includes an adsorption layer disposed on a portion of the top substrate facing the front-end device, wherein the adsorption layer and the inductor do not overlap in a vertical direction. | 02-04-2016 |
| 20160035670 | Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices - Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a back side interconnect structure, and a winding of an inductor disposed in a material layer of the back side interconnect structure. A molding material is coupled to the back side interconnect structure. The package includes an integrated circuit die mounting region disposed within the molding material. | 02-04-2016 |
| 20160035672 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 02-04-2016 |
| 20160035816 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure. | 02-04-2016 |
| 20160049458 | FISHBONE LC COMPONENT AND METHOD OF MAKING THE SAME - A semiconductor structure according to some examples may include an LC component for use in PMIC applications. The semiconductor structure may have a first conductive coil mounted on an upper surface of a substrate, the first conductive coil surrounding a magnetic core; an output located on a surface of the first conductive coil and coupled to the coil; a dielectric layer located on a surface of the output; and an upper conductive element located on a surface of the dielectric layer, wherein the upper conductive element, the dielectric layer, and the output form a capacitor; and the first conductive coil and the magnetic core form an inductor. The semiconductor structure may also include a second conductive coil located in a same horizontal plane as the first conductive coil, the second conductive coil surrounding a magnetic core where the first conductive coil and the second conductive coil form a fishbone pattern. | 02-18-2016 |
| 20160049459 | INTEGRATED CIRCUIT COMPRISING AT LEAST AN INTEGRATED ANTENNA - An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit. | 02-18-2016 |
| 20160064470 | MICRO-FABRICATED INTEGRATED COIL AND MAGNETIC CIRCUIT AND METHOD OF MANUFACTURING THEREOF - A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material. | 03-03-2016 |
| 20160071796 | DIELECTRIC REGION IN A BULK SILICON SUBSTRATE PROVIDING A HIGH-Q PASSIVE RESONATOR - Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC. | 03-10-2016 |
| 20160079171 | SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED SURFACE MOUNT DEVICE AND METHOD OF FORMING THE SAME - Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a package substrate bonded to a first side of the first package with by a first set of connectors. The semiconductor package further includes a surface mount device mounted to the first side of the first package, the surface mount device consisting essentially of one or more passive devices. | 03-17-2016 |
| 20160087025 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view. | 03-24-2016 |
| 20160093570 | SEMICONDUCTOR DEVICE - Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer. | 03-31-2016 |
| 20160093592 | WAFER LEVEL INTEGRATION OF PASSIVE DEVICES - A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization. | 03-31-2016 |
| 20160099301 | Structure of integrated inductor - This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure. | 04-07-2016 |
| 20160104064 | IC MODULE, DUAL IC CARD, AND METHOD FOR MANUFACTURING IC MODULE - An IC module of the present invention includes: a sheet-like base having a first surface and a second surface and having a first through hole and a second through hole spaced apart from the first through hole; an IC chip provided to the first surface, having a contact communication function and a contactless communication function, and having two terminals formed thereon; a connecting coil formed on the first surface and having two ends; a contact terminal portion provided to the second surface and configured to contact an external contact machine; bridge wiring provided to the second surface, provided at a position overlapping with the first and second through holes, and electrically insulated from the contact terminal portion; a first conductive wire inserted through the first through hole and connecting the first terminal of the IC chip to the bridge wiring; a second conductive wire inserted through the second through hole and connecting the bridge wiring to the first end of the connecting coil; and a third conductive wire connecting the second end of the connecting coil to the second terminal of the IC chip. | 04-14-2016 |
| 20160111364 | CHIP PACKAGE STRUCTURE - A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip. | 04-21-2016 |
| 20160111404 | METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES - Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing. | 04-21-2016 |
| 20160118368 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view. | 04-28-2016 |
| 20160122180 | METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A FUNCTIONAL CAPPING - A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices. | 05-05-2016 |
| 20160126219 | PACKAGE INCLUDING A SEMICONDUCTOR DIE AND A CAPACITIVE COMPONENT - In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar. | 05-05-2016 |
| 20160133565 | INTEGRATED CIRCUITS INCLUDING MAGNETIC CORE INDUCTORS AND METHODS FOR FABRICATING THE SAME - Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion. | 05-12-2016 |
| 20160133566 | MULTI-LAYER TRANSMISSION LINE STRUCTURE FOR MISALIGNMENT RELIEF - A circuit includes a dielectric layer and a stacked inductor. A first metal line is disposed on a first side of the dielectric layer. A second metal line is disposed on a second side of the dielectric layer and inductively coupled with the first metal line through a portion of the dielectric layer. The first metal line has a first width between respective edges of the first metal line. The second metal line has a second width between respective edges of the second metal line. The second width of the second metal line is greater than the first width of the first metal line. The first metal line is vertically aligned with the second metal line. The respective edges of the second metal line are located outwardly of the respective edges of the first metal line. | 05-12-2016 |
| 20160141239 | METAL PATTERN STRUCTURE HAVING POSITIONING LAYER - A metal pattern structure having a positioning layer thereon is provided. The positioning layer is located within a predetermined region of the metal pattern structure and located directly on the surface of a metal layer of the metal pattern structure. | 05-19-2016 |
| 20160141244 | INTEGRATED DEVICE PACKAGE COMPRISING AN ELECTROMAGNETIC (EM) PASSIVE DEVICE IN AN ENCAPSULATION LAYER, AND AN EM SHIELD - Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the die and the EM passive device, and a redistribution portion coupling the die and the EM passive device. In some implementations, the EM passive device includes an electromagnetic (EM) passive device. The EM passive device includes a base layer, a via traversing the base layer, a pad coupled to the via, and at least redistribution layer configured to operate as electromagnetic (EM) passive component, where the redistribution layer is coupled to the pad. The redistribution portion of the EM passive device includes at least one redistribution layer that is configured to electrically couple the die to the EM passive device. The redistribution portion includes at least one redistribution layer that is configured as an electromagnetic (EM) shield. | 05-19-2016 |
| 20160148926 | INTEGRATED CIRCUIT DEVICE - The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern and the second metal pattern. The third metal pattern is electrically grounding. An inductor is disposed over the third metal pattern. | 05-26-2016 |
| 20160148929 | INTEGRATED CIRCUIT DEVICE - The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern, and the second metal pattern. The third metal pattern is electrically grounded. An inductor is disposed over the third metal pattern. | 05-26-2016 |
| 20160163641 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for forming a semiconductor device includes, sequentially, providing a substrate having a first region and a second region; forming a first dielectric layer on the substrate; forming a second dielectric layer having a plurality of first openings exposing portions of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer and the first dielectric layer in the second region until the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer. | 06-09-2016 |
| 20160163660 | SEMICONDUCTOR DEVICE HAVING HIGH FREQUENCY WIRING AND DUMMY METAL LAYER AT MULTILAYER WIRING STRUCTURE - A semiconductor device includes a semiconductor substrate, a plurality of wiring layers provided on the semiconductor substrate, a high frequency wiring provided at a first layer in the plurality of wiring layers, and a plurality of dummy metals provided in a second layer provided between the semiconductor substrate and the first layer having the high frequency wiring. The plurality of wiring layers at a top view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, the high frequency wiring vicinity region including a first region enclosed by an outer edge of the high frequency wiring and a second region surrounding the first region. The plurality of dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively. | 06-09-2016 |
| 20160163693 | STRUCTURE WITH INDUCTOR AND MIM CAPACITOR - A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core. | 06-09-2016 |
| 20160181242 | PASSIVE DEVICE AND MANUFACTURING METHOD THEREOF | 06-23-2016 |
| 20160190076 | CHIP PART - A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench. | 06-30-2016 |
| 20160190113 | PASSIVE COMPONENTS IN VIAS IN A STACKED INTEGRATED CIRCUIT PACKAGE - Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit. | 06-30-2016 |
| 20160204062 | TANK CIRCUIT STRUCTURE AND METHOD OF MAKING THE SAME | 07-14-2016 |
| 20160204188 | HIGH BREAKDOWN VOLTAGE PASSIVE ELEMENT AND HIGH BREAKDOWN VOLTAGE PASSIVE ELEMENT MANUFACTURING METHOD | 07-14-2016 |
| 20160254224 | INDUCTOR FOR SEMICONDUCTOR INTEGRATED CIRCUIT | 09-01-2016 |
| 20160254342 | MAGNETIC CORE, INDUCTOR, AND METHOD FOR FABRICATING THE MAGNETIC CORE | 09-01-2016 |
| 20160379958 | MULTILAYER SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region. | 12-29-2016 |
| 20160380041 | Embedded Passive Chip Device and Method of Making the Same - An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed. | 12-29-2016 |
| 20160380042 | Passive Chip Device and Method of Making the Same - A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed. | 12-29-2016 |
| 20180025986 | INTEGRATED FAN-OUT PACKAGE | 01-25-2018 |
| 20180026090 | Embedded Passive Chip Device and Method of Making the Same | 01-25-2018 |
| 20180026095 | DEVICE ISOLATOR WITH REDUCED PARASITIC CAPACITANCE | 01-25-2018 |
| 20190148486 | DEVICE ISOLATOR WITH REDUCED PARASITIC CAPACITANCE | 05-16-2019 |
