| Entries |
| Document | Title | Date |
|---|
| 20080237781 | Chip-stacked semiconductor device and manufacturing method thereof - The semiconductor device according to the present invention includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a silicon film in contact with an inner surface of the isolation trench, a silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the silicon films. According to the present invention, the silicon film within the isolation trench can be substantially regarded as a part of the silicon substrate. Therefore, even when the width of the isolation trench is increased to increase the etching rate, the width of the insulation film becoming a dead space can be made sufficiently small. Consequently, the chip area can be decreased. | 10-02-2008 |
| 20080246110 | STRUCTURE FOR SPANNING GAP IN BODY-BIAS VOLTAGE ROUTING STRUCTURE - Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire. | 10-09-2008 |
| 20080283959 | Tapered through-silicon via structure - An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV. | 11-20-2008 |
| 20080283960 | Production of a Carrier Wafer Contact in Trench Insulated Integrated Soi Circuits Having High-Voltage Components - The invention relates to a method for producing structures which make it possible to form a trench insulation and to bring into contact SOI wafers provided with active thick layers and which are easily processable. For this purpose, a carrier wafer electric contact and the insulation trench are provided with components exhibiting high-blocking capability of insertion into an integrated circuit SOI wafer. A narrow trench for an insulating trench ( | 11-20-2008 |
| 20080296725 | SEMICONDUCTOR COMPONENT AND METHOD FOR FABRICATING THE SAME - A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate. | 12-04-2008 |
| 20090026572 | Method of Manufacturing a Semiconductor Device, Method of Manufacturing a SOI Device, Semiconductor Device, and SOI Device - According to one embodiment of the present invention, a SOI device includes a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer; a trench structure being formed within the first composite structure; and a second composite structure provided on the side walls of the trench structure, wherein the second composite structure includes a first isolation layer covering the part of the side walls formed by the semiconductor layer and formed by an upper part of the buried layer; and a contact layer covering the isolation layer and the part of the side walls formed by a lower part of the buried layer. | 01-29-2009 |
| 20090026573 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile semiconductor memory device and a method for manufacturing the same that may include forming an isolation pattern in a substrate, and then etching a portion of the isolation pattern to expose a portion of an active region of the substrate, and then forming high-density second-type ion implantation regions spaced apart at both edges of the active region by performing a tilted ion implantation process, and then forming a high-density first-type ion implantation region as a bit line in the active region, and then forming an insulating layer on the substrate including the high-density first-type ion implantation region, the high-density second-type ion implantation regions and the isolation pattern, and then forming a metal interconnection as a word line on the insulating layer pattern and extending in a direction perpendicular to bit line. | 01-29-2009 |
| 20090039457 | LOW CROSSTALK SUBSTRATE FOR MIXED-SIGNAL INTEGRATED CIRCUITS - An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip. | 02-12-2009 |
| 20090127652 | STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING - A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region. | 05-21-2009 |
| 20090140378 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a flash memory device, trenches are formed in an isolation area of a semiconductor substrate. A first insulating layer is formed on sidewalls and bottoms of the trenches. Conductive layer patterns are formed on the first insulating layers at the bottoms of the trenches. A second insulating layer is formed on the conductive layer patterns. Gate lines are formed over a semiconductor substrate including the second insulating layer. The gate lines intersect the conductive layer patterns. Junctions are formed on the semiconductor substrate between the gate lines. An interlayer insulating layer is formed over the semiconductor substrate including the gate lines. Contact holes are formed through which the conductive layer patterns and the junctions located on one side of the conductive layer patterns are exposed. The contact holes are gap-filled with a conductive material, thereby forming contact plugs. | 06-04-2009 |
| 20090146246 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure. | 06-11-2009 |
| 20090146247 | SEMICONDUCTOR GROUND SHIELD - A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield. | 06-11-2009 |
| 20090160012 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device, a silicon epitaxial layer formed on and/or over the first device, a second device formed on and/or over the silicon epitaxial layer, and a connection via formed through the silicon epitaxial layer, which may electrically interconnect the first device and the second device. According to embodiments, a method for fabricating a semiconductor device may include forming a first device, forming a silicon epitaxial layer on and/or over the first device, forming a connection via through the silicon epitaxial layer, and forming a second device on and/or over the silicon epitaxial layer such that the second device may be electrically connected to the connection via. | 06-25-2009 |
| 20090189244 | INTEGRATED CIRCUIT DEVICES AND METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUIT DEVICES - Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed. | 07-30-2009 |
| 20090189245 | SEMICONDUCTOR DEVICE WITH SEAL RING - A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner. | 07-30-2009 |
| 20090194843 | INTEGRATED CIRCUIT ARRANGEMENT INCLUDING A PROTECTIVE STRUCTURE - An integrated circuit arrangement. In one embodiment, the arrangement includes at least one first semiconductor zone of a first conduction type which is doped more highly than the basic doping of a first semiconductor layer and which is arranged at a distance from a first component zone adjoining the first semiconductor layer. At least one connecting zone extends as far as the at least one first semiconductor zone proceeding from the first side. A second semiconductor zone of the second conduction type, is arranged in the first semiconductor layer and is electrically conductively connected to the at least one connecting zone. | 08-06-2009 |
| 20090243031 | STRUCTURE AND METHOD TO CONTROL OXIDATION IN HIGH-K GATE STRUCTURES - In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric. | 10-01-2009 |
| 20090250783 | SEMICONDUCTOR DEVICE HAVING AN ANNULAR GUARD RING - A semiconductor chip | 10-08-2009 |
| 20090278226 | STRUCTURE FOR CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY AND STRUCTURE THEREOF - The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SIO. A dielectric liner is formed at an interface of the SIO within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material. | 11-12-2009 |
| 20090302415 | Micro-Electromechanical System Devices - Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer. | 12-10-2009 |
| 20100084735 | SEMICONDUCTOR ASSEMBLY AND METHOD FOR FORMING SEAL RING - A method for forming a seal ring is disclosed. First, a substrate including a MEMS region, a logic region and a seal ring region is provided. Second, a trench is formed in the MEMS region and multiple recesses are formed in the seal ring region. An oxide fills the trench and the recesses. Later, a MOS is form in the logic region and a dielectric layer is formed on the substrate. Then, an etching procedure is carried out to partially remove the dielectric layer and simultaneously remove the oxide in the multiple recesses completely to form a seal ring space. Afterwards, a metal fills the seal ring space to from the seal ring. | 04-08-2010 |
| 20100084736 | SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA - A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact. | 04-08-2010 |
| 20100090307 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS·FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved. | 04-15-2010 |
| 20100127344 | CONTACT OVER ISOLATOR - An apparatus and method for providing a reliable connection to an internal node from the backside of an integrated circuit using focused ion beam (“FIB”) milling are disclosed herein. In accordance with at least some embodiments, an integrated circuit includes an isolation region, an active region, a first contact, and a metal layer. The isolation region separates adjacent integrated circuit devices. The first contact is disposed between the isolation region and the metal layer. The first contact is electrically connected to the active region. A dummy structure is disposed between the isolation region and the first contact. A FIB via is milled through the isolation region and the dummy structure to the first contact to establish an electrical connection with active region through the via. | 05-27-2010 |
| 20100164055 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER - A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion. | 07-01-2010 |
| 20100207237 | Crack stop structure enhancement of the integrated circuit seal ring - An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate. | 08-19-2010 |
| 20100283119 | Semiconductor Device Including a Deep Contact and a Method of Manufacturing Such a Device - A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped. | 11-11-2010 |
| 20100327398 | DESIGN STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween. | 12-30-2010 |
| 20110006389 | SUPPRESSING FRACTURES IN DICED INTEGRATED CIRCUITS - A semiconductor device has a singulated die having a substrate and a die edge. An interconnect dielectric layer is located on the substrate, and integrated circuit has interconnections located within the interconnect dielectric layer. A trench is located in the interconnect dielectric layer and between a seal ring and a remnant of the interconnect dielectric layer. The seal ring is located within the interconnect dielectric layer and between the trench and the integrated circuit, with the remnant of the interconnect dielectric layer being located between the trench and the edge of the die. | 01-13-2011 |
| 20110031581 | INTEGRATED CIRCUIT (IC) HAVING TSVS WITH DIELECTRIC CRACK SUPPRESSION STRUCTURES - An IC includes a substrate having a semiconductor top surface, a plurality of metal interconnect levels having inter-level dielectric (ILD) layers therebetween on the top surface, and a bottom surface. A plurality of through substrate vias (TSVs) extend from a TSV terminating metal interconnect level downward to the bottom surface. The plurality of TSVs include an electrically conductive filler material surrounded by a dielectric liner that define a projected volume. The projected volume includes a projected area over the electrically conductive filler material and a projected height extending upwards from the TSV terminating metal interconnect level to a metal interconnect level above, and a projected sidewall surface along sidewalls of the projected volume. A crack suppression structure (CSS) protects TSVs and includes a lateral CSS portion that is positioned lateral to the projected volume and encloses at least 80% of the projected sidewall surface. | 02-10-2011 |
| 20110101491 | INTEGRATED CIRCUIT PACKAGES INCLUDING HIGH DENSITY BUMP-LESS BUILD UP LAYERS AND A LESSER DENSITY CORE OR CORELESS SUBSTRATE - In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented. In this regard, an apparatus is introduced having a first element including a microelectronic die having an active surface and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes at least one surface substantially planar to said microelectronic die active surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface; and a second element coupled to the first element, the second element including a substrate having a plurality of dielectric material layers and conductive traces to conductively couple conductive contacts on a top surface with conductive contacts on a bottom surface, said conductive contacts on said top surface conductively coupled with said conductive traces of said first element. Other embodiments are also disclosed and claimed. | 05-05-2011 |
| 20110108945 | Seal Ring Structures with Reduced Moisture-Induced Reliability Degradation - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 05-12-2011 |
| 20110115047 | SEMICONDUCTOR PROCESS USING MASK OPENINGS OF VARYING WIDTHS TO FORM TWO OR MORE DEVICE STRUCTURES - Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described. | 05-19-2011 |
| 20110140231 | INTEGRATED MICROELECTRONIC DEVICE WITH THROUGH-VIAS - An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone ( | 06-16-2011 |
| 20110140232 | METHODS OF FORMING A THERMAL CONDUCTION REGION IN A SEMICONDUCTOR STRUCTURE AND STRUCTURES RESULTING THEREFROM - An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a semiconductor layer over a thermal conduction layer, forming an isolation region over the thermal conduction layer, and forming a thermal conduction region in the isolation region. | 06-16-2011 |
| 20110147884 | Contacting and Filling Deep-Trench-Isolation with Tungsten - Electrically isolated, deep trench isolation (DTI) structures, are formed in a wafer, and a portion of the DTI structures are converted to electrically connected structures to provide a shielding function, or to provide connection to deep buried layers. In one aspect, DTI structures include a polysilicon filling over a liner layer disposed on the inner surface of a deep trench, the polysilicon is removed by isotropic etching, and the deep trench is re-filled with a conductive material. Alternatively, the polysilicon filling remains and a contact is formed to provide an electrical connection to the polysilicon. In another aspect, a deep trench is disposed in the wafer such that a lower portion thereof is located within a deep buried layer, and after the polysilicon is removed, an anisotropic etch removes a portion of the deep trench liner from the bottom of the deep trench, thereby allowing a tungsten deposition to make electrical contact with the deep buried layer. | 06-23-2011 |
| 20110163412 | ISOLATOR AND METHOD OF MANUFACTURING THE SAME - The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having at least two coil patterns spaced apart from each other. According to the present invention, an isolator can be protected from impulses generated by ESD and surge, so that its reliability can be improved, and its size can be considerably decreased. Further, the number of wire bonding times is decreased, so that performance of a chip can be enhanced, and packaging efficiency can be improved, thereby increasing productivity. | 07-07-2011 |
| 20110186960 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 08-04-2011 |
| 20110260286 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure. | 10-27-2011 |
| 20110266649 | Semiconductor device - A semiconductor device includes a SOI (silicon on insulator) substrate having a first region and a second region, a multilayer wiring layer formed on the SOI substrate and having an insulating layer and a wiring layer alternately stacked in this order, a first inductor formed over the SOI substrate, and a second inductor formed over the SOI substrate and positioned above the first inductor. | 11-03-2011 |
| 20110309468 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip package includes a substrate, a first layer disposed on the substrate and a second layer substantially similar to and disposed on the first layer. The first layer has a first input/output (I/O) circuit, a first through-via connected to the first input/output (I/O) circuit and a second through-via that is not connected to the first I/O circuit. The second layer has a second I/O circuit, a third through-via connected to the second I/O circuit and a fourth through-via that is not connected to the second I/O circuit. The first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. The package maybe fabricated by stacking the layers, and changing the orientation of the second layer relative to the first to ensure that the first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. | 12-22-2011 |
| 20120007211 | IN-STREET DIE-TO-DIE INTERCONNECTS - The present disclosure relates to the field of microelectronic die packaging, particularly multi-chip packaging, wherein on-substrate modularity is enabled by using in-street die-to-die interconnects to facilitate signal routing between microelectronic dice. These in-street die-to-die interconnects may allow for manufacturing of several products on a single microelectronic substrate, which may lead to improved microelectronic die and/or microelectronic module harvesting and increased product yields. | 01-12-2012 |
| 20120018840 | ELEMENT ISOLATION STRUCTURE OF SEMICONDUCTOR AND METHOD FOR FORMING THE SAME - Disclosed are an element isolation structure of a semiconductor device and a method for forming the same, the method including preparing a semiconductor substrate having an inactive region and an active region defined thereon, forming a first hard mask on the semiconductor substrate, exposing the inactive region of the semiconductor substrate by patterning the first hard mask, forming a second hard mask on the entire surface of the semiconductor substrate including the first hard mask, forming a deep trench in the semiconductor substrate by patterning the second hard mask and the semiconductor substrate, removing the patterned second hard mask, forming a shallow trench overlapped with the deep trench by patterning the semiconductor substrate using the first hard mask as a mask, forming an insulation film on the entire surface of the substrate including the shallow trench and the deep trench, filling the shallow trench and the deep trench by forming an element isolation film on the insulation film, and forming an element isolation film pattern in the deep trench and the shallow trench by selectively removing the element isolation film. | 01-26-2012 |
| 20120074519 | CRACK STOP STRUCTURE ENHANCEMENT OF THE INTEGRATED CIRCUIT SEAL RING - An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate. | 03-29-2012 |
| 20120104541 | SEAL RING STRUCTURE WITH POLYIMIDE LAYER ADHESION - The present disclosure provides a semiconductor device, including a substrate having a seal ring region and a circuit region, a seal ring structure disposed over the seal ring region, a first passivation layer disposed over the seal ring structure, the first passivation layer having a first passivation layer aperture over the seal ring structure, and a metal pad disposed over the first passivation layer, the metal pad coupled to the seal ring structure through the first passivation layer aperture and having a metal pad aperture above the first passivation layer aperture. The device further includes a second passivation layer disposed over the metal pad, the second passivation layer having a second passivation layer aperture above the metal pad aperture, and a polyimide layer disposed over the second passivation layer, the polyimide layer filling the second passivation layer aperture to form a polyimide root at an exterior tapered edge of the polyimide layer. | 05-03-2012 |
| 20120104542 | Semiconductor Structure With Contact Structure and Manufacturing Method of the Same - The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface. | 05-03-2012 |
| 20120119324 | MEMS ISOLATION STRUCTURES - A device may comprise a substrate formed of a first semiconductor material and a trench formed in the substrate. A second semiconductor material may be formed in the trench. The second semiconductor material may have first and second portions that are isolated with respect to one another and that are isolated with respect to the first semiconductor material. | 05-17-2012 |
| 20120119325 | GUARD TRENCH - A device may comprise a substrate formed of a first semiconductor material, a first trench formed in the substrate, a second trench formed in the substrate proximate the first trench, an oxide layer formed in the first trench and the second trench, and a second semiconductor material formed upon the oxide layer. The oxide layer in the second trench may be adapted to mitigate undercut of the oxide layer in the first trench during an etching process. | 05-17-2012 |
| 20120153430 | INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS - A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously. | 06-21-2012 |
| 20120153431 | INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT - Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s). | 06-21-2012 |
| 20120175727 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer. | 07-12-2012 |
| 20120175728 | SEAL RING STRUCTURE FOR INTEGRATED CIRCUIT CHIPS - A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W | 07-12-2012 |
| 20120205776 | DUAL CONTACT TRENCH RESISTOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - The invention relates to a semiconductor structures and methods of manufacture and, more particularly, to a dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture. In a first aspect of the invention, a method comprises forming a trench in a substrate; forming a first insulator layer within the trench; forming a first electrode within the trench, on the first insulator layer, and isolated from the substrate by the first insulator layer; forming a second insulator layer within the trench and on the first electrode; and forming a second electrode within the trench, on the second insulator layer, and isolated from the substrate by the first insulator layer and the second insulator layer. | 08-16-2012 |
| 20120205777 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a trench formed in a substrate and defining a plurality of active regions, a punch-through prevention layer filling a part of the trench and coupled to a ground, and an isolation layer formed over the punch-through prevention layer and filling the other part of the trench. | 08-16-2012 |
| 20120217611 | INTEGRATED CIRCUITS INCLUDING CONDUCTIVE STRUCTURES THROUGH A SUBSTRATE AND METHODS OF MAKING THE SAME - An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap. | 08-30-2012 |
| 20120217612 | VERTICAL FLOATING BODY STORAGE TRANSISTORS FORMED IN BULK DEVICES AND HAVING BURIED SENSE AND WORD LINES - A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime. | 08-30-2012 |
| 20120273918 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics. | 11-01-2012 |
| 20130001738 | HIGH BREAKDOWN VOLTAGE INTEGRATED CIRCUIT ISOLATION STRUCTURE - A high breakdown voltage integrated circuit isolator device communicates a digital signal from a signal input on one semiconductor die to a signal output on another semiconductor die while providing high voltage isolation between the signal input and the signal output. Each die may include a respective capacitive isolation barrier structure that couple together via a bonding wire between combined top metal/bonding pads of the capacitive isolation barrier structures. | 01-03-2013 |
| 20130015553 | High Voltage Isolation Trench, Its Fabrication Method and MOS DeviceAANM Jiang; YanfengAACI BeijingAACO CNAAGP Jiang; Yanfeng Beijing CN - A type of high voltage isolation trench, its fabrication method and an MOS device are disclosed. The isolation trench includes a trench extending to a buried oxide layer of a wafer, with high concentration N | 01-17-2013 |
| 20130026599 | SEMICONDUCTOR DEVICE - A semiconductor device includes an isolation portion penetrating a semiconductor substrate from a first surface to a second surface positioned opposite the first surface. The isolation portion includes a first insulating film and a second insulating film. The first insulating film has a slit portion at a side of the first surface and the slit portion is buried with the second insulating film. The semiconductor device further includes an electrode penetrating the semiconductor substrate that is surrounded by the isolation portion. | 01-31-2013 |
| 20130093043 | ARRAY AND MOAT ISOLATION STRUCTURES AND METHOD OF MANUFACTURE - An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region. | 04-18-2013 |
| 20130134548 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, the thickness of an insulating film formed in a through hole is reduced, while an annular groove having an insulating material embedded therein is provided so as to ensure a sufficient total thickness of the insulator, whereby a through silicon via is provided with an insulating ring which is improved in both processability and functionality. | 05-30-2013 |
| 20130147007 | DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions. | 06-13-2013 |
| 20130175663 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes linear patterns disposed between isolation trenches extending in a first direction in a semiconductor device and having a first crystal direction the same as the semiconductor substrate. A bridge pattern connects at least two adjacent linear patterns and includes a semiconductor material having a second crystal direction different from the first crystal direction. A first isolation layer pattern is disposed in at least one of the isolation trenches in a field region of the semiconductor substrate. Memory cells are disposed on at least one of the linear patterns. | 07-11-2013 |
| 20130193549 | SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PLUGS AND METHODS OF MANUFACTURING THE SAME - Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided. | 08-01-2013 |
| 20130193550 | 3D INTEGRATED CIRCUIT - A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer. | 08-01-2013 |
| 20130200487 | PATTERN STRUCTURE AND METHOD OF FORMING THE SAME - A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern. | 08-08-2013 |
| 20130207227 | MOSFET TERMINATION TRENCH - A method, in one embodiment, can include forming a core trench and a termination trench in a substrate. The termination trench is wider than the core trench. In addition, a first oxide can be deposited that fills the core trench and lines the sidewalls and bottom of the termination trench. A first polysilicon can be deposited into the termination trench. A second oxide can be deposited above the first polysilicon. A mask can be deposited above the second oxide and the termination trench. The first oxide can be removed from the core trench. A third oxide can be deposited that lines the sidewalls and bottom of the core trench. The first oxide within the termination trench is thicker than the third oxide within the core trench. | 08-15-2013 |
| 20130234282 | SEMICONDUCTOR DEVICE WITH VERTICAL CELLS AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor substrate includes defining an active region by forming a device isolation layer over the substrate, forming a first trench dividing the active region into a first active region and a second active region, forming a buried bit line filling a portion of the first trench, forming a gap-filling layer gap-filling an upper portion of the first trench over the buried bit line, forming second trenches by etching the gap-filling layer and the device isolation layer in a direction crossing the buried bit line, and forming a first buried word line and a second buried word line filling the second trenches, wherein the first buried word line and the second buried word line are shaped around sidewalls of the first active region and the second active region, respectively. | 09-12-2013 |
| 20130256830 | SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING - Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer. | 10-03-2013 |
| 20130256831 | N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE - A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells. | 10-03-2013 |
| 20130264676 | SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIA INTERCONNECT AND METHOD FOR FABRICATING THE SAME - The invention provides a semiconductor package with a through silicon via (TSV) interconnect and a method for fabricating the same. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate. A through hole is formed through the semiconductor substrate. A TSV interconnect is disposed in a through hole. A conductive layer lines a sidewall of the through hole, surrounding the TSV interconnect. | 10-10-2013 |
| 20130320486 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided. | 12-05-2013 |
| 20130328161 | SPACER ISOLATION IN DEEP TRENCH - A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening. | 12-12-2013 |
| 20140054743 | Isolated Through Silicon Vias in RF Technologies - Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate. | 02-27-2014 |
| 20140117492 | SEMICONDUCTOR DEVICES INCLUDING A RECESSED ACTIVE REGION, AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A RECESSED ACTIVE REGION - Semiconductor devices are provided. Each of the semiconductor devices may include a substrate including an active region that includes first and second regions. Each of the semiconductor devices may include a device isolation layer between the first and second regions of the active region. Each of the semiconductor devices may include a contact hole defined by recessed portions of the device isolation layer and the first region of the active region, respectively. Moreover, a topmost surface of the first region of the active region may define a bottommost portion of the contact hole. Related methods of forming semiconductor devices are also provided. | 05-01-2014 |
| 20140131833 | BODY-BIAS VOLTAGE ROUTING STRUCTURES - Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit. | 05-15-2014 |
| 20140167212 | Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method - A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW. | 06-19-2014 |
| 20140191359 | SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING - Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer. | 07-10-2014 |
| 20140252536 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes line patterns disposed on a substrate, the line patterns extending in a first direction and being parallel to one another. The semiconductor device includes conductive patterns spaced apart from each other in the first direction between an adjacent pair of the line patterns. The semiconductor device includes insulating fences electrically isolating the conductive patterns from each other and having chamfered corners. The semiconductor device includes insulating patterns filling gaps between side surfaces of the line patterns and the chamfered corners of the insulating fences. | 09-11-2014 |
| 20140264724 | DEEP TRENCH ISOLATION - An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type. | 09-18-2014 |
| 20150069570 | Integrated Circuit Structure with Active and Passive Devices in Different Tiers - An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure. | 03-12-2015 |
| 20150333019 | SEMICONDUCTOR DEVICE AND METHOD FABRICATING THE SAME - According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground. | 11-19-2015 |
| 20160005697 | SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF - Provided are a semiconductor chip, a semiconductor package and a fabricating method thereof, which can reduce or prevent cracks from being generated or propagated due to an external pressure. The semiconductor chip includes a semiconductor substrate including a first region and a second region, a plurality of interlayer insulation layers formed on the semiconductor substrate, a first crack stopper formed in the plurality of interlayer insulation layers of the first region, an interconnector formed in the plurality of interlayer insulation layers of the second region, a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, a bonding pad on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire, and a protection layer covering the pad wire and exposing the bonding pad. The first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad while not overlapping with the bonding pad and not being connected to the pad wire. | 01-07-2016 |
| 20160027772 | INTEGRATED CAPACITOR IN AN INTEGRATED CIRCUIT - An integrated capacitor includes a semiconductor substrate comprising a trench isolation area; a first interlayer dielectric (ILD) layer covering the trench isolation area; a first electrode plate comprising at least a first contact layer in the first ILD layer, wherein the contact layer is disposed directly on the trench isolation area; a second electrode plate in the first ILD layer; and a capacitor dielectric structure between the first electrode plate and the second electrode plate. | 01-28-2016 |
| 20160079240 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, an isolation region, a first electrode, a second electrode, and a third electrode. The plurality of second semiconductor regions is selectively provided on the first semiconductor region. The second semiconductor region has a first conductivity type. The plurality of third semiconductor regions is selectively provided on the first semiconductor region. Each of the third semiconductor regions is adjacent to each of the second semiconductor regions. The third semiconductor region has a second conductivity type. The isolation region is provided in the first semiconductor region. The isolation region is positioned between the adjacent second semiconductor regions and the adjacent third semiconductor regions. The first electrode is connected to the second semiconductor region and the third semiconductor region which are adjacent to the isolation region. | 03-17-2016 |
| 20160099193 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material. | 04-07-2016 |
| 20160133583 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF HAVING GUARD RING STRUCTURE - In some embodiments, an integrated circuit (IC) device includes a substrate having a first functional region, a second functional region and a third functional region. The IC device also includes a plurality of dielectric layers over the substrate, a first guard ring in the plurality of dielectric layers and around the first functional region, and a second guard ring in the plurality of dielectric layers and around the second functional region. The second guard ring is separate from the first guard ring, and the third functional region is free of a guard ring. The IC device further includes a seal ring in the plurality of dielectric layers. The seal ring encircles the first and the second guard rings, and is separate from the first and the second guard rings. | 05-12-2016 |
| 20160148941 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device may include semiconductor patterns. The semiconductor device may include insulating layers including first regions surrounding the semiconductor patterns and second regions isolated from each other by island-type first openings and connecting the first regions adjacent to each other. The semiconductor device may include metal layers interposed between the first regions of the stacked insulating layers surrounding the semiconductor patterns, and isolated from each other by line-type second openings overlapping the first openings and the second regions. The semiconductor device may include dielectric patterns partially interposed between the insulating layers and the metal layers and exposed through the second openings. | 05-26-2016 |
| 20160163635 | SEMICONDUCTOR DEVICE - A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure. | 06-09-2016 |
| 20160190067 | SEMICONDUCTOR STRUCTURES WITH ISOLATED OHMIC TRENCHES AND STAND-ALONE ISOLATION TRENCHES AND RELATED METHOD - A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench. | 06-30-2016 |
| 20190148389 | SEMICONDUCTOR STRUCUTRE AND METHOD OF FABRICATING THE SAME | 05-16-2019 |
| 20190148414 | DISPLAY DEVICE | 05-16-2019 |
