Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257499000 - INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application number	Description	Number of patent applications / Date published
257504000	Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation)	7
20080265362	BUILDING FULLY-DEPLETED AND BULK TRANSISTORS ON SAME CHIP - An integrated circuit having fully-depleted silicon-on-insulator (FD-SOI) transistors and bulk transistors on a semiconductor substrate is disclosed.	10-30-2008
20100264509	Enhanced Transmission Lines for Radio Frequency Applications - An integrated circuit structure includes a semiconductor substrate of a first conductivity type; a depletion region in the semiconductor substrate; and a deep well region substantially enclosed by the depletion region. The deep well region is of a second conductivity type opposite the first conductivity type, and includes a first portion directly over the deep well region and a second portion directly under the deep well region. A transmission line is directly over the depletion region.	10-21-2010
20110079870	SEMICONDUCTOR DEVICE - This specification discloses a semiconductor device having higher electric strength.	04-07-2011
20110147880	POWER SEMICONDUCTOR DEVICE WITH NEW GUARD RING TERMINATION DESIGN AND METHOD FOR PRODUCING SAME - A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer. This spacer sub-region has a width for enabling a reliable alignment of a shadow mask during an ion implantation such that an implanted lifetime control region having carrier lifetime reducing defects may be restricted to a central area while no such defects are implanted into the junction termination region to improve electrical characteristics.	06-23-2011
20110215435	SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p	09-08-2011
20140015091	SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SOI SUBSTRATE - Provided is a semiconductor device showing stable high-frequency characteristics.	01-16-2014
20160035722	SEMICONDUCTOR DEVICES AND STRUCTURES - An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.	02-04-2016