| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257503000 | With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit) | 55 |
| 20080246108 | Semiconductor device including power switch and power reinforcement cell - A semiconductor device according to one embodiment includes a cell disposition region in which plural basic cells are disposed and a basic power supply wiring. In the cell disposition region are disposed a primitive cell connected to the basic power supply wiring and a high current consumption cell connected to the basic power supply wiring. Furthermore, in the cell disposition region are disposed regularly plural ordinary power switch cells that supply a first current to the primitive cell respectively. The power reinforcement cell including a power switch cell configured so as to flow a predetermined current to the high current consumption cell is disposed near the high current consumption cell. | 10-09-2008 |
| 20080265361 | METHOD FOR GENERATING A LAYOUT, USE OF A TRANSISTOR LAYOUT, AND SEMICONDUCTOR CIRCUIT - A method for generating a layout, use of a transistor layout, and semiconductor circuit is provided that includes a matching structure, which has a number of transistors, whose structure is similar to one another, metallization levels with geometrically formed traces, which are formed directly above the transistors, and vias (in via levels), which are formed between two of the metallization levels. Whereby, within one and the same metallization level, the geometry of the traces above each transistor is formed the same. | 10-30-2008 |
| 20080290444 | CAPACITOR STRUCTURE IN A SEMICONDUCTOR DEVICE - A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator. | 11-27-2008 |
| 20090108392 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor device includes a plurality of rectilinear structures, wherein the plurality of rectilinear structures comprise silicon dioxide and extend from a surface of a semiconductor material to a distance of at least about three microns or greater below the surface of the semiconductor material and wherein a first rectilinear structure of the plurality of rectilinear structures is perpendicular to, or substantially perpendicular to, a second rectilinear structure of the plurality of rectilinear structures. Other embodiments are described and claimed. | 04-30-2009 |
| 20090108393 | Semiconductor Device With a Plurality of Ground Planes - A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting other chips and without being affected by other chips. This MCM structure also may facilitate testing of interconnects/connections between two or more chips. | 04-30-2009 |
| 20090166798 | DESIGN METHODOLOGY FOR GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR LATCHUP PREVENTION - A design structure is disclosed for a circuit optimizing guard ring design by optimizing the path resistance value between the components of the parasitic lateral bipolar transistors in a CMOS circuit and the power supply or ground. By comparing the calculated path resistance value to a maximum resistance number derived from specifications, elements that need further redesign are identified. Repeated redesign with several redesign options eventually lead to an optimized guard ring structure that provides area-efficient and sufficient latchup protection for the CMOS circuit. A design structure employing such an optimized guard ring is also provided. | 07-02-2009 |
| 20090189241 | Using floating fill metal to reduce power use for proximity communication - One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of transmission pads, wherein the layer of fill metal is “floating” (e.g., not connected to any signal). Leaving this layer of fill metal floating reduces the parasitic capacitance for the array of transmission pads, which can reduce the amount of power needed to transmit the signal. | 07-30-2009 |
| 20090321871 | Chip Pad Resistant to Antenna Effect and Method - A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC. | 12-31-2009 |
| 20100001366 | Semiconductor device having shared bit line structure and method of manufacturing the same - A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions. | 01-07-2010 |
| 20100140734 | Electronic Device and Method for Manufacturing Thereof - An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure. | 06-10-2010 |
| 20100155879 | SEMICONDUCTOR DEVICE - A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area. | 06-24-2010 |
| 20100164053 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling. | 07-01-2010 |
| 20100207234 | SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD - A semiconductor device ( | 08-19-2010 |
| 20100264508 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high Ohmic region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high Ohmic region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided. | 10-21-2010 |
| 20100283117 | FUSE BOX GUARD RINGS INCLUDING PROTRUSIONS AND METHODS OF FORMING SAME - A structure included in a semiconductor device can include a fuse box guard ring that defines an interior region of the fuse box inside the fuse box guard ring and that defines an exterior region of the fuse box outside the fuse box guard ring. The fuse box guard ring can include protruding support members that protruding from an interior sidewall or from an exterior sidewall of the fuse box guard ring. | 11-11-2010 |
| 20100295146 | SEAL RING STRUCTURE FOR INTEGRATED CIRCUITS - A seal ring structure for an integrated circuit includes a seal ring being disposed along a periphery of the integrated circuit and being divided into at least a first portion and a second portion, wherein the second portion is positioned facing an analog and/or RF circuit block and is different from the first portion in structure. A P | 11-25-2010 |
| 20110049667 | Semiconductor Component With Dielectric Layer Stack - A semiconductor component has a semiconductor body zone, a first electrically conductive layer adjacent to the semiconductor body zone, a first dielectric layer with first dielectric properties and a second dielectric layer with second dielectric properties. The first dielectric properties differ from the second dielectric properties. The first dielectric layer and the second dielectric layer are arranged between the semiconductor body zone and the first electrically conductive layer. A second electrically conductive layer is applied between the first dielectric layer and the second dielectric layer. A first voltage divider is switched between the first electrically conductive layer and the semiconductor body zone. The second electrically conductive layer is electrically conductively connected only to the voltage divider. | 03-03-2011 |
| 20110057288 | MEMS DEVICE AND METHOD FOR FABRICATING THE SAME - A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The MEMS device includes a first electrode and a second electrode. The first electrode is disposed on a substrate, and includes at least two metal layers, a first protection ring and a dielectric layer. The first protection ring connects two adjacent metal layers, so as to define an enclosed space between two adjacent metal layers. The dielectric layer is disposed in the enclosed space and connects two adjacent metal layers. The second electrode is disposed on the first electrode, wherein a cavity is formed between the first electrode and the second electrode. | 03-10-2011 |
| 20110095392 | HIGH VOLTAGE RESISTANCE COUPLING STRUCTURE - The disclosed invention provides a structure and method for providing a high lateral voltage resistance between the electrical networks, sharing a lateral plane, of conductive elements (e.g., having different high voltage potentials) comprising a coupler. In one embodiment, an integrated coupler providing a high lateral voltage resistance comprises a primary conductive element and a secondary conductive element. An isolating material is laterally configured between the electrical network of the primary conductive element and an electrical network of the secondary conductive element. The isolating material may comprise a low-k dielectric layer and prevents any lateral barrier layers (e.g., etch stop layers, diffusion barrier layers, etc.) from extending between the first conductive element and the electrical network of the second conductive element. The structure therefore provides a galvanically isolated integrated coupler which avoids electrical shorting between circuits (e.g., at barrier layers) resulting in an improved high voltage resistance. | 04-28-2011 |
| 20110101487 | CRACK RESISTANT CIRCUIT UNDER PAD STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A circuit under pad structure includes a substrate, a pad electrode, wiring layers interlayer insulation layers alternately disposed between the pad electrode and the substrate, and at least one circuit pattern integral with the substrate, disposed beneath the lowermost wiring layer and spanned by the pad electrode. The width of each wiring layer is smaller than the width of the wiring layer beneath it, i.e., closer to the substrate. The structure is fabricated such that it resists cracking, which maximizes its production yield, and possesses a minimal footprint. | 05-05-2011 |
| 20110108942 | METHOD FOR PRODUCING FIELD EFFECT TRANSISTORS WITH A BACK GATE AND SEMICONDUCTOR DEVICE - The method for producing a field effect transistor on a substrate comprising a support layer, a sacrificial layer and a semi-conducting layer comprises forming an active area in the semi-conducting layer. The active area is delineated by a closed peripheral insulation pattern and comprises an additional pattern made from insulating material. The method also comprises etching the insulating material of the additional pattern to access the sacrificial layer, etching the sacrificial layer resulting in formation of a first cavity, forming a dielectric layer on a top wall of the first cavity, and depositing an electrically conducting layer in the first cavity. The closed peripheral insulation pattern is formed through the semi-conducting layer and the sacrificial layer. | 05-12-2011 |
| 20110133305 | SEMICONDUCTOR CHIP FOR SUPPRESSING ELECTROMAGNETIC WAVE - A semiconductor chip includes: a semiconductor substrate having a plurality of electronic elements therein; a metal circuit pattern formed on the semiconductor substrate and allowing the plurality of electronic elements to be electrically connected to one another; and dummy metal patterns formed on the semiconductor substrate and the metal circuit pattern to suppress a predetermined specific frequency ranges. | 06-09-2011 |
| 20110233717 | INTEGRATED CIRCUIT GUARD RINGS - Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage. | 09-29-2011 |
| 20110260281 | SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES - Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band. | 10-27-2011 |
| 20110266646 | SEMICONDUCTOR DEVICE - A digital circuit portion ( | 11-03-2011 |
| 20110272776 | STANDARD CELL, SEMICONDUCTOR DEVICE HAVING STANDARD CELLS, AND METHOD FOR LAYING OUT AND WIRING THE STANDARD CELL - The chip area of a semiconductor device having a plurality of standard cells is to be made smaller. A semiconductor device includes first and second standard cells. The first standard cell includes a diffusion region, a functional device region opposed to the diffusion region, and a metal layer. The second standard cell includes another diffusion region continuous with the diffusion region, another functional device region opposed to the other diffusion region, and further another diffusion region formed between the other diffusion region and the other functional device region. The metal layer and the other functional device region are coupled together electrically through the diffusion regions. | 11-10-2011 |
| 20110309465 | SEAL RING STRUCTURE IN SEMICONDUCTOR DEVICES - The present disclosure provides a semiconductor device that includes a substrate having a seal ring region and a circuit region, a plurality of dummy gates disposed over the seal ring region of the substrate, and a seal ring structure disposed over the plurality of dummy gates in the seal ring region. A method of fabricating a semiconductor device is also provided, the method including providing a substrate having a seal ring region and a circuit region, forming a plurality of dummy gates over the seal ring region of the substrate, and forming a seal ring structure over the plurality of dummy gates over the seal ring region. | 12-22-2011 |
| 20110309466 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a first-conductivity-type region (an N-type well region, for example) and a first second-conductivity-type region (a P-type semiconductor substrate, for example) positioned to cover a lower surface of the first-conductivity-type region, a second second-conductivity-type region (a P-type well region, for example) that is positioned to surround the side faces of the first-conductivity-type region and is in contact with the first second-conductivity-type region, a guard ring that is electrically connected to the second second-conductivity-type region and is also electrically connected to a fixed potential terminal, an insulating film positioned to cover an upper surface of the first-conductivity-type region, and an analog element (a resistor element, for example) placed on the insulating film. | 12-22-2011 |
| 20120012969 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug. | 01-19-2012 |
| 20120025345 | METHOD, APPARATUS, AND DESIGN STRUCTURE FOR SILICON-ON-INSULATOR HIGH-BANDWIDTH CIRCUITRY WITH REDUCED CHARGE LAYER - A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view. | 02-02-2012 |
| 20120038020 | SEAL RING STRUCTURE WITH METAL PAD - A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided. | 02-16-2012 |
| 20120061794 | METHODS OF FORMING THROUGH WAFER INTERCONNECTS IN SEMICONDUCTOR STRUCTURES USING SACRIFICIAL MATERIAL, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of fabricating semiconductor structures include providing a sacrificial material within a via recess, forming a first portion of a through wafer interconnect in the semiconductor structure, and replacing the sacrificial material with conductive material to form a second portion of the through wafer interconnect. Semiconductor structures are formed by such methods. For example, a semiconductor structure may include a sacrificial material within a via recess, and a first portion of a through wafer interconnect that is aligned with the via recess. Semiconductor structures include through wafer interconnects comprising two or more portions having a boundary therebetween. | 03-15-2012 |
| 20120112308 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR GROUP MEMBER AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device includes a device portion, a first electrode portion, a second electrode portion and a protruding portion. The device portion is provided on a substrate. The first electrode portion is provided on the device portion and is electrically contacted with the device portion. The second electrode portion is provided on the device portion separated from the first electrode portion, and electrically contacted with the device portion. The protruding portion is provided on the device portion and protrudes outward from a peripheral portion of the first electrode portion and the second electrode portion. | 05-10-2012 |
| 20120241900 | SELF DETECTION DEVICE FOR HIGH VOLTAGE ESD PROTECTION - An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection. | 09-27-2012 |
| 20120273917 | High Voltage Resistance Coupling Structure - The disclosed invention provides a structure and method for providing a high lateral voltage resistance between the electrical networks, sharing a lateral plane, of conductive elements (e.g., having different high voltage potentials) comprising a coupler. In one embodiment, an integrated coupler providing a high lateral voltage resistance comprises a primary conductive element and a secondary conductive element. An isolating material is laterally configured between the electrical network of the primary conductive element and an electrical network of the secondary conductive element. The isolating material may comprise a low-k dielectric layer and prevents any lateral barrier layers (e.g., etch stop layers, diffusion barrier layers, etc.) from extending between the first conductive element and the electrical network of the second conductive element. The structure therefore provides a galvanically isolated integrated coupler which avoids electrical shorting between circuits (e.g., at barrier layers) resulting in an improved high voltage resistance. | 11-01-2012 |
| 20120319228 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed, which includes first and second power supply pads supplied with first and second power voltages, respectively, a first protection circuit coupled between the first and second power supply pads, and an internal circuit including a first power line and a plurality of transistors electrically coupled to the first power line. The first power line includes first and second portions, and the first portion is electrically connected to the first power supply pad. The device further includes a second protection circuit coupled between the second portion of the first power line and the second power supply pad. | 12-20-2012 |
| 20120319229 | SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES - Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band. | 12-20-2012 |
| 20130075856 | Integrated Circuit Structure and Method of Forming the Same - An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path. | 03-28-2013 |
| 20130082346 | SEAL RING STRUCTURE WITH A METAL PAD - A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided. | 04-04-2013 |
| 20130277794 | Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps - A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump. | 10-24-2013 |
| 20140035092 | RADIO FREQUENCY ISOLATION FOR SOI TRANSISTORS - According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided. | 02-06-2014 |
| 20140054742 | Semiconductor Structure - Various embodiments provide a semiconductor structure. The semiconductor structure may include a semiconductor substrate; a via extending through the semiconductor substrate; and a capacitive structure surrounding at least a portion of the via. The capacitive structure may include a metal layer formed on the semiconductor substrate. | 02-27-2014 |
| 20140151842 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a semiconductor chip formed with cut fuses over one surface thereof; and migration preventing modules preventing occurrence of a phenomenon in which metal ions of the fuses migrate to cut zones of the fuses; each migration preventing module including: a ground electrode formed in the semiconductor chip to face the fuse with a first insulation member interposed therebetween; a floating electrode formed over the fuse with a second insulation member interposed therebetween to face the ground electrode with the fuse interposed therebetween; and a power supply electrode formed over the floating electrode with a third insulation member interposed therebetween. | 06-05-2014 |
| 20140252532 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening. | 09-11-2014 |
| 20140306316 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first insulator, a second insulator, and a sacrificial layer on a semiconductor substrate, and forming plural core materials from the sacrificial layer and the second insulator. The method further includes forming first and second interconnects on side surfaces of each core material to form plural first interconnects and plural second interconnects alternately, each first interconnect having a first side surface in contact with a core material and a second side surface positioned on an opposite side of the first side surface, and each second interconnect having a third side surface in contact with a core material and a fourth side surface positioned on an opposite side of the third side surface. The method further includes removing the sacrificial layer so that the second insulator remains, after the first and second interconnects are formed. | 10-16-2014 |
| 20140339674 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a lower wiring on the substrate; an inter-layer insulating film covering the lower wiring; first and second upper wirings on the inter-layer insulating film and separated from each other; and a semi-insulating protective film covering the first and second upper wirings, wherein the protective film is not provided in a region right above the lower wiring and between the first upper wiring and the second upper wiring. | 11-20-2014 |
| 20150115394 | Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die - A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers. | 04-30-2015 |
| 20150123238 | SEMICONDUCTOR DEVICES - There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon. | 05-07-2015 |
| 20150137307 | Integrated Circuit Assembly with Faraday Cage - An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer. The third electrically conductive interconnect layer forms a second electrically conductive plate below the electrically conductive ring and the region of the semiconductor layer. The plurality of electrically conductive vias electrically couple the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate. The electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device. | 05-21-2015 |
| 20150294970 | CAPACITOR, RESISTOR AND RESISTOR-CAPACITOR COMPONENTS - Capacitor, resistor and resistor-capacitor components are described herein. In one embodiment, a die comprises first and second metal interconnect layers in a back end of line (BEOL) of the die, and an insulator between the first and second metal interconnect layers. The die also comprises a metal-insulator-metal (MIM) capacitor embedded in the insulator, the MIM capacitor comprising a first metal plate, a second metal plate, and a dielectric layer between the first and second metal plates. The die further comprises a metal resistor embedded in the insulator, wherein the metal resistor and the first metal plate of the MIM capacitor are formed from a same metal layer. In one example, the dielectric layer may have a higher dielectric constant than the insulator. In another example, the second metal plate of the MIM capacitor may overlap the metal resistor. | 10-15-2015 |
| 20150340277 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device in accordance with various embodiments may include: forming an opening in a first region of a semiconductor substrate, the opening having at least one sidewall and a bottom; implanting dopant atoms into the at least one sidewall and the bottom of the opening; configuring at least a portion of a second region of the semiconductor substrate laterally adjacent to the first region as at least one of an amorphous or polycrystalline region; and forming an interconnect over at least one of the first and second regions of the semiconductor substrate. | 11-26-2015 |
| 20160126324 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region. | 05-05-2016 |
| 20160163692 | SINGLE-CHIP INTEGRATED CIRCUIT WITH CAPACITIVE ISOLATION AND METHOD FOR MAKING THE SAME - An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions. | 06-09-2016 |
| 20160379999 | HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE - Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation. | 12-29-2016 |
| 20180025997 | SEMICONDCUTOR STRUCTURE AND SEMICONDUCTOR MANUFACTURING PROCESS THEREOF | 01-25-2018 |
