| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257500000 | Including high voltage or high power devices isolated from low voltage or low power devices in the same integrated circuit | 50 |
| 20080211053 | Superjunction Semiconductor Device - In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the boundary between the active region and the termination region. The active and termination regions include columns of first and second conductivity type material alternately arranged along a horizontal direction in a semiconductor region having top and bottom surfaces. At least one of the columns of the first conductivity type material in the termination region has a different width than a width of the columns of the first conductivity type material in the active region. | 09-04-2008 |
| 20080237777 | Completely decoupled high voltage and low voltage transistor manufacurting processes - A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer. | 10-02-2008 |
| 20080258253 | Integrated Microprocessor System for Safety-Critical Regulations - Disclosed is an integrated circuit arrangement for safety-critical applications, such as for regulating and controlling tasks in an electronic brake system for motor vehicles. The arrangement includes several electronic, cooperating functional groups ( | 10-23-2008 |
| 20080308895 | Semiconductor device - A semiconductor device and fabricating method thereof are provided. A dual gate oxide layer is formed by thermal oxidation after carrying out a prescribed pre-processing on an STI edge, which results in a high quality oxide layer by thermal oxidation and a uniformly maintained gate oxide layer thickness of a high voltage device area. The present invention includes a semiconductor substrate divided into an active area and an inactive area, the active area including a high voltage device area and a low voltage device area; a device isolation layer on the inactive area of the semiconductor substrate; and a gate oxide layer on the high voltage device area of the semiconductor substrate, the gate oxide layer having a uniform thickness. | 12-18-2008 |
| 20090008740 | Semiconductor Integrated Circuit Devices Having Conductive Patterns that are Electrically Connected to Junction Regions and Methods of Fabricating Such Devices - A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern. | 01-08-2009 |
| 20090090990 | FORMATION OF NITROGEN CONTAINING DIELECTRIC LAYERS HAVING AN IMPROVED NITROGEN DISTRIBUTION - Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region. | 04-09-2009 |
| 20090140372 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least one second region includes at least one second device oriented in a second direction. The second direction is different than the first direction. | 06-04-2009 |
| 20090140373 | Method of Manufacturing LCD Driver IC - Disclosed is a method of manufacturing an LCD driver IC. The method includes forming a plurality of gate patterns on a semiconductor substrate by sequentially forming a plurality of gate insulating films and gate electrodes; sequentially depositing a plurality of spacer material layers covering the gate electrodes; forming spacers on the side walls of the gate electrodes by performing an etchback process on the plurality of spacer material layers such that the lowermost spacer material layer remains on the semiconductor substrate; and controlling the thickness of the lowermost spacer material layer (or removing the lowermost spacer material layer) by etching the lowermost spacer material layer. | 06-04-2009 |
| 20090166797 | HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE INCLUDING HIGH-VOLTAGE RESISTANT DIODE - Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented. | 07-02-2009 |
| 20090236681 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 09-24-2009 |
| 20090261446 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed. | 10-22-2009 |
| 20090261447 | SEMICONDUCTOR INTEGRATED CIRCUIT - Signal lines ( | 10-22-2009 |
| 20100001364 | Semiconductor Device Having Improved Oxide Thickness at a Shallow Trench Isolation Edge and Method of Manufacture Thereof - One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer. | 01-07-2010 |
| 20100019343 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a first transistor in a substrate; a second transistor in said substrate; and a further device in said substrate, wherein the second transistor and the further device are arranged to operate at a second voltage which is higher than a first voltage, wherein the first voltage is the (normal) voltage of operation of the first transistor, and wherein the first transistor is isolated from the second voltage. | 01-28-2010 |
| 20100059851 | CMOS CIRCUITS COMBINING HIGH VOLTAGE AND RF TECHNOLOGIES - A CMOS circuit comprises at least one high voltage transistor (having gate and drain operating voltages of greater than 8V) and at least one high frequency capable transistor (having a maximum switching frequency of between 100 MHz and 1000 GHz) wherein said transistors are integrated on the same semiconductor substrate so as to allow the simple integration of high voltage circuits and RF (radio frequency) CMOS circuits on the same integrated circuit. | 03-11-2010 |
| 20100148298 | SEMICONDUCTOR DEVICE - A semiconductor device is composed of a pair of semiconductor chips ( | 06-17-2010 |
| 20100164052 | HIGH POWER INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers. | 07-01-2010 |
| 20100283116 | SEMICONDUCTOR DEVICE DRIVING BRIDGE-CONNECTED POWER TRANSISTOR - A semiconductor device includes a low-side circuit, high-side circuit, a virtual ground potential pad, a common ground potential pad and a diode, formed on a semiconductor substrate. The low-side circuit drives a low-side power transistor. The high-side circuit is provided at a high potential region, and drives a high-side power transistor. The virtual ground potential pad is arranged at the high potential region, and coupled to a connection node of both power transistors to supply a virtual ground potential to the high-side circuit. The common ground potential pad supplies a common ground potential to the low-side circuit and high-side circuit. The diode has its cathode connected to the virtual ground potential pad and its anode connected to the common ground potential pad. | 11-11-2010 |
| 20100314709 | LATCH-UP PREVENTION STRUCTURE AND METHOD FOR ULTRA-SMALL HIGH VOLTAGE TOLERANT CELL - A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level. | 12-16-2010 |
| 20110057287 | SEMICONDUCTOR DEVICE HAVING DUAL-STI AND MANUFACTURING METHOD THEREOF - A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved. | 03-10-2011 |
| 20110140227 | Depletion mode circuit protection device - A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines. | 06-16-2011 |
| 20110316115 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device comprises: a high-voltage side switching element and a low-voltage side switching element which are totem-pole-connected in that order from a high-voltage side between a high-voltage side potential and a low-voltage side potential; a high-voltage side drive circuit that drives the high-voltage side switching element; a low-voltage side drive circuit that drives the low-voltage side switching element; a capacitor which has a first end connected to a connection point between the high-voltage side switching element and the low-voltage side switching element and a second end connected to a power supply terminal of the high-voltage side drive circuit and supplies a drive voltage to the high-voltage side drive circuit; and a diode which has an anode connected to a power supply and a cathode connected to the second end of the capacitor and supplies a current from the power supply to the second end of the capacitor, wherein the diode includes a P-type semiconductor substrate, an N-type cathode region on a surface of the P-type semiconductor substrate, a P-type anode region in the N-type cathode region, a P-type contact region and an N-type contact region in the P-type anode region, a cathode electrode connected to the N-type cathode region, and an anode electrode connected to the P-type contact region and the N-type contact region. | 12-29-2011 |
| 20120018839 | SEMICONDUCTOR DEVICE - CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration. | 01-26-2012 |
| 20120098083 | INTEGRATED CIRCUIT TECHNOLOGY WITH DIFFERENT DEVICE EPITAXIAL LAYERS - A semiconductor die includes a substrate, a first device region and a second device region. The first device region includes an epitaxial layer on the substrate and one or more semiconductor devices of a first type formed in the epitaxial layer of the first device region. The second device region is spaced apart from the first device region and includes an epitaxial layer on the substrate and one or more semiconductor devices of a second type formed in the epitaxial layer of the second device region. The epitaxial layer of the first device region is different than the epitaxial layer of the second device region so that the one or more semiconductor devices of the first type are formed in a different epitaxial layer than the one or more semiconductor devices of the second type. | 04-26-2012 |
| 20120193750 | POWER MANAGEMENT INTEGRATED CIRCUIT - A Power Management Integrated Circuit (PMIC) that includes a substrate, a high-side (HS) region on the substrate, a low-side (LS) region spaced from the first region, a device isolation layer interposed between the HS region and the LS region, a metal interconnection connected to the HS region across the device isolation layer and configured to permit a high-voltage current to flow in the HS region, and at least one electric field shield between the metal interconnection and the device isolation layer. Since the electric field shield is disposed under the metal interconnection, a sufficient breakdown voltage can be ensured for the HS region and the LS region. | 08-02-2012 |
| 20130249046 | CONFIGURABLE ELECTROSTATIC DISCHARGING POWER CLAMP AND RELATED INTEGRATED CIRCUIT - There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit. | 09-26-2013 |
| 20140167207 | SEMICONDUCTOR DEVICE - A potential isolation element is provided separately from a diode. An n-type low-concentration region is formed on a P-type layer. A first high-concentration N-type region is positioned in the n-type low-concentration region and is connected to a cathode electrode of the diode. A second high-concentration N-type region is positioned in the n-type low-concentration region, is disposed to be spaced from a first second-conduction-type high-concentration region, and is connected to a power supply interconnection of a first circuit. A first P-type region is formed in the n-type low-concentration region, and a bottom portion thereof is connected to the P-type layer. A ground potential is applied to the first P-type region, and the first P-type region is positioned in the vicinity of the first high-concentration N-type region. | 06-19-2014 |
| 257501000 | Including dielectric isolation means | 22 |
| 20080203519 | MICROELECTRONIC ASSEMBLY WITH IMPROVED ISOLATION VOLTAGE PERFORMANCE AND A METHOD FOR FORMING THE SAME - A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices ( | 08-28-2008 |
| 20080296723 | Semiconductor device - Provided is a semiconductor device that is capable of suppressing occurrence of a crystal defect in an elongated circuit region formed in an SOI substrate. Low-voltage transistor regions are separated, by multiple inner isolation layers, into multiple sub-regions. For this reason, the length of the longitudinal direction of the sub-regions is reduced, even though the low-voltage transistor regions are extremely elongated, for example. This configuration can suppress occurrence of a crystal defect in the low-voltage transistor regions in the longitudinal direction thereof, although such defect may occur due to the difference in thermal expansion or thermal contraction between a semiconductor layer in the low-voltage transistor regions, and the element isolation layers. | 12-04-2008 |
| 20080315346 | Passivation of Deep Isolating Separating Trenches with Sunk Covering Layers - Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches. | 12-25-2008 |
| 20090065890 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments relate to the lowered reliability of a device due to deterioration caused by the concentration of an electric field in the top corner of an STI. To solve the reliability problem, the STI top corners have a local oxidation of silicon, the top corners of the STI are rounded, and the STI steps are increased in a semiconductor device fabricated according to embodiments. Embodiments relate to an STI in high and low voltage regions of a semiconductor device which can be fabricated by providing a semiconductor substrate having a shallow trench isolation structure, a high voltage region and a low voltage region. A capping layer is formed over the entire surface of the top of the high voltage region and the low voltage region, including the shallow trench isolation structure. A photoresist pattern is formed over the top of the capping layer to expose the high voltage region, including a portion of the shallow trench isolation structure formed within the high voltage region. The capping layer of the high voltage region is removed by performing an etching process using the photoresist pattern as a mask. An oxidation process is performed on the shallow trench isolation structure top corners of the high voltage region from which the capping layer is removed. An ion implantation is then carried out. The ion implantation may be carried out by implanting boron using a tilt method. | 03-12-2009 |
| 20090090991 | Method for Manufacturing Semiconductor Device - A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively. | 04-09-2009 |
| 20090152668 | Semiconductor apparatus - A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference circuit part located in the active layer and operable at a second reference potential; a level-shifting element forming part located in the active layer and for providing a level-shift between the first and second reference potentials; and an insulation member insulating first and second portions of the support substrate from each other, wherein locations of the first and second portions respectively correspond to the low and high potential reference circuit parts. | 06-18-2009 |
| 20090194841 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film. | 08-06-2009 |
| 20100001365 | ISOLATION TECHNIQUE ALLOWING BOTH VERY HIGH AND LOW VOLTAGE CIRCUITS TO BE FABRICATED ON THE SAME CHIP - An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000 s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk. | 01-07-2010 |
| 20100052091 | Semiconductor device and fabrication method of the same - A semiconductor device including a first conduction type semiconductor layer; a second conduction type element forming region formed above the first conduction type semiconductor layer and formed with at least one semiconductor element formed on a surface region of the second conduction type element forming region; a first conduction type element-isolation region insulating and segregating the second conduction type element forming region from the exterior; and a second conduction type buried region formed at the interface of the first conduction type semiconductor layer and the second conduction type element forming region, formed separated from the first conduction type element-isolation region. In the semiconductor device a second conduction type high concentration region is buried in the surface of the second conduction type element forming region and formed to surround the semiconductor element and separated from the first conduction type element-isolation region. | 03-04-2010 |
| 20100102414 | SEMICONDUCTOR DEVICE - The present invention aims at providing a semiconductor device that can prevent quality degradation of a signal caused by noise, reduce a malfunction of a circuit caused by latch-up, and secure favorable isolation, and the semiconductor device includes: a first layer with a resistivity higher than 10·cm and lower than 1 k·cm which is formed in a semiconductor substrate; a second layer formed on a surface of the semiconductor substrate so as to be located above the first layer; two semiconductor devices formed in the second layer or on the second layer; and a trench-type insulating region which is located between the two semiconductor devices, is formed in the semiconductor substrate so as to reach the first layer from the surface of the semiconductor substrate, and electrically isolates the two semiconductor devices. | 04-29-2010 |
| 20100109118 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor layer, a low withstand voltage transistor, and a high withstand voltage transistor. In the low withstand voltage transistor, a first high concentration collector region and a first base region contact with a first low concentration collector region provided in the semiconductor layer. In the high withstand voltage transistor, a second high concentration collector region and a second base region contact a second low concentration collector region provided in the semiconductor layer. Further, the second high concentration collector region and the second base region are configured such that the distance between the second high concentration collector region and the second base region in a parallel direction to a main surface of the semiconductor layer is longer than the distance between the first high concentration collector region and the first base region. | 05-06-2010 |
| 20100171193 | SEMICONDUCTOR DEVICE - This invention provides a semiconductor device, which is used to manufacture two lateral high-voltage devices on the same substrate, where the voltages between maximum voltage terminals and minimum voltage terminals of the two devices have not too much difference. Both devices are formed on two different surface regions with a small isolation region in-between the two regions. When the semiconductor region(s) of the isolation region is fully depleted, its effective electric flux density emitted to the substrate is of a value between the values of its adjacent regions of said two semiconductor devices. The figure presented here schematically shows the structure used to form a low-side high-voltage n-MOST and high-voltage n-MOST and M | 07-08-2010 |
| 20100176480 | Semiconductor device, method for manufacturing the same, and multilayer substrate having the same - A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit. | 07-15-2010 |
| 20100181638 | METHOD OF FORMING AN ISOLATION STRUCTURE - Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit. | 07-22-2010 |
| 20100207233 | HIGH POWER DEVICE ISOLATION AND INTEGRATION - A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device. | 08-19-2010 |
| 20100314710 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE - Aspects of the present invention provide a high-voltage semiconductor device and a high voltage integrated circuit device while minimizing or eliminating the need for the addition of back surface steps. Aspects of the invention provide a high-voltage semiconductor device that achieves, low voltage driving and quick response by way of stable high voltage wiring and a low ON voltage. In some aspects of the invention, a high-voltage semiconductor device can include a semiconductor layer is formed on a support substrate interposing an embedded oxide film therebetween. A high potential side second stage transistor and a low potential side first stage transistor surrounding the second stage transistor are formed on the surface region of the semiconductor layer. The source electrode of the second stage transistor is connected to the drain electrode of the first stage transistor. A drain electrode of the second stage transistor is connected to a drain pad. | 12-16-2010 |
| 20100327395 | SEMICONDUCTOR DEVICE ON DIRECT SILICON BONDED SUBSTRATE WITH DIFFERENT LAYER THICKNESS - A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices. | 12-30-2010 |
| 20110233716 | CIRCUIT STRUCTURE OF AN ULTRA HIGH VOLTAGE LEVEL SHIFTER - A circuit structure of an ultra high voltage level shifter includes a low voltage substrate having the electronic elements of the ultra high voltage level shifter thereon, an ultra high voltage redistribution layer, and a passivation layer between the substrate and the redistribution layer to prevent dielectric breakdown between the redistribution layer and the substrate. | 09-29-2011 |
| 20120056295 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 03-08-2012 |
| 20160005812 | Integrated Circuit of Driving Device and Manufacture Method thereof - An integrated circuit for a driving device is disclosed. The integrate circuit includes a substrate comprising a high-voltage area and a low-voltage area; a plurality of first trenches, formed in the high-voltage area; a plurality of first isolations, formed in the plurality of first trenches of the high-voltage area; a plurality of second trenches, formed in the low-voltage area; and a plurality of second isolations, formed in the plurality of second trenches of the low-voltage area; wherein a depth difference exists between each of the plurality of first trenches and each of the plurality of second trenches. | 01-07-2016 |
| 20160099310 | SEMICONDUCTOR DEVICE INTEGRATING HIGH AND LOW VOLTAGE DEVICES - The present invention is directed to a method for forming multiple active components, such as bipolar transistors. MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance. | 04-07-2016 |
| 20160172236 | DEVICE SUBSTRATES, INTEGRATED CIRCUITS AND METHODS FOR FABRICATING DEVICE SUBSTRATES AND INTEGRATED CIRCUITS | 06-16-2016 |
| 257502000 | High power or high voltage device extends completely through semiconductor substrate (e.g., backside collector contact) | 1 |
| 20090250781 | POWER SEMICONDUCTOR DEVICE - The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a reverse electrode of the switching power semiconductor element and a reverse electrode of the free wheeling diode are bonded and mounted on a circuit pattern formed on the main surface of the first substrate, and that a circuit pattern, which is so formed on the main surface of the second substrate as to oppose a surface electrode of the switching power semiconductor element and a surface electrode of the free wheeling diode, is connected to the surface electrodes of the switching power semiconductor element and the free wheeling diode through connective conductors to be soldered, respectively. | 10-08-2009 |
