| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257495000 | Floating pn junction guard region | 10 |
| 20080265359 | SEMICONDUCTOR DIVICE - A semiconductor device in the present invention is provided with a cathode layer of an N-type impurity region and an anode layer of a P-type impurity region formed on the cathode layer. A plurality of floating ring layers of the P-type impurity regions which is electrically floating is provided spaced apart from the anode layer on the main surface of the cathode layer. Then, well layers of the N-type impurity regions containing floating ring layers are provided. For example, each well layer can individually be provided to the floating ring layer. In this case, each floating ring layer may be spaced apart or overlapped one another. Accordingly, a semiconductor device serves to downsize a chip without changing a property of on-resistance or a breakdown voltage. | 10-30-2008 |
| 20080303114 | Semiconductor device having P-N column layer and method for manufacturing the same - A semiconductor device is provided, which includes a substrate; a P-N column layer disposed on the substrate; a second conductivity type epitaxial layer disposed on the P-N column layer. The P-N column layer includes first conductivity type columns and second conductivity type columns, which are alternately arranged. Each column has a tapered shape. A portion of the first conductivity type column located around the substrate has a smaller impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer. A portion of the second conductivity type column located around the substrate has a larger impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer. | 12-11-2008 |
| 20090045481 | SEMICONDUCTOR DEVICE HAVING BREAKDOWN VOLTAGE MAINTAINING STRUCTURE AND ITS MANUFACTURING METHOD - A semiconductor device has an active portion having at least one well region in a semiconductor layer, and a breakdown voltage maintaining structure surrounding the active portion. The maintaining structure includes a conductor layer over each of a plurality of guard rings with an insulating film interposed in between and connected to the respective guard ring. An inner side end portion of each conductor layer projects over the immediate adjacent inner side guard ring. The impurity concentration of the guard rings is set between the impurity concentrations of the semiconductor layer and the well regions. A field plate can extend over the innermost conductor layer with the insulating film interposed in between. The field plate is in contact with the outermost well region and is in contact with the first conductor layer. The outer side end of the field plate extends outwardly beyond an outer side end of the innermost conductor layer. With these arrangements, the guard rings can be shortened and the chip size can be reduced. Furthermore, the device can be made less susceptible to external charge. | 02-19-2009 |
| 20090206440 | Power Semiconductor Device - A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region. | 08-20-2009 |
| 20110233715 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a cell active region including a p-base layer being an active layer of a second conductivity type that is diffused above a high concentration n-type substrate being a semiconductor substrate of a first conductivity type; and a p-well layer being a first well region of the second conductivity type having a ring shape, which is adjacent to the p-base layer, is diffused above the high concentration n-type substrate so as to surround the cell active region, and serves as a main junction part of a guard ring structure, wherein in a region on a surface of the p-well layer other than both ends, a trench region that is a ring-shaped recess having a tapered side surface is formed along the ring shape of the p-well layer | 09-29-2011 |
| 20120267750 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having a bootstrap-type driver circuit includes a cavity for a SON structure formed below a bootstrap diode Db, and a p-type floating region formed in a n | 10-25-2012 |
| 20140015090 | BIPOLAR TRANSISTOR WITH HIGH BREAKDOWN VOLTAGE - A higher breakdown voltage transistor has separated emitter, base contact, and collector contact. Underlying the emitter and the base contact are, respectively, first and second base portions of a first conductivity type. Underlying and coupled to the collector contact is a collector region of a second, opposite, conductivity type, having a central portion extending laterally toward, underneath, or beyond the base contact and separated therefrom by the second base portion. A floating collector region of the same conductivity type as the collector region underlies and is separated from the emitter by the first base portion. The collector and floating collector regions are separated by a part of the semiconductor (SC) region in which the base is formed. A further part of the SC region in which the base is formed, laterally bounds or encloses the collector region. | 01-16-2014 |
| 20140239436 | HIGH VOLTAGE FAST RECOVERY TRENCH DIODE - Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 08-28-2014 |
| 20150130014 | FAST RECOVERY RECTIFIER - The present disclosure provides a rectifier. The rectifier includes a N-type epitaxial layer, a plurality of P-type diffusion regions and a plurality of N-type diffusion regions. The P-type diffusion regions are disposed in the N-type epitaxial layer, and the N-type diffusion regions are respectively disposed in the P-type diffusion regions. Wherein, the P-type diffusion regions are electronically coupled to the N-type diffusion regions. | 05-14-2015 |
| 20160013267 | TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS | 01-14-2016 |
