| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257494000 | Reverse-biased pn junction guard region | 19 |
| 20090079022 | METHOD OF FORMING LOW CAPACITANCE ESD DEVICE AND STRUCTURE THEREFOR - In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage. | 03-26-2009 |
| 20090294892 | Edge Termination for Semiconductor Devices - A high-voltage termination structure includes a peripheral voltage-spreading network. One or more trench structures are connected at least partly in series between first and second power supply voltages. The trench structures include first and second current-limiting structures connected in series with a semiconductor material, and also includes permanent charge in a trench-wall dielectric. The current-limiting structures in the trench structures are jointly connected in a series-parallel ladder configuration. The current-limiting structures, in combination with the semiconductor material, provide a voltage distribution between the core portion and the edge portion. | 12-03-2009 |
| 20100019342 | SEMICONDUCTOR DEVICE - In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region. | 01-28-2010 |
| 20100224953 | RECTIFIER APPLICABLE IN HIGH TEMPERATURE CONDITION - A rectifier for high temperature application includes a conductive semiconductor layer, a conductive epitaxial layer, and a plurality of conductive doped regions within the conductive epitaxial layer. A fringe conductive doped region is formed surrounding the conductive doped region, and an outer fringe conductive doped region is formed further surrounding the fringe conductive doped region. A first metal layer is formed on the upper surface of the conductive semiconductor substrate covering the entire conductive doped regions, and contacting at least a portion of the fringe conductive doped region. A second metal layer is formed on the lower surface of the conductive semiconductor substrate. | 09-09-2010 |
| 20130105934 | SEMICONDUCTOR DEVICE | 05-02-2013 |
| 20130175657 | Surface (Lateral) Voltage-sustaining Region with an Insulator Film Containing Conductive Particles - A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types. | 07-11-2013 |
| 20130228891 | MULTI-TRENCH TERMINATION STRUCTURE FOR SEMICONDUCTOR DEVICE AND MANUFACTURING MEHTOD THEREOF - A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device. | 09-05-2013 |
| 20140159192 | SEMICONDUCTOR DEVICE - In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance. | 06-12-2014 |
| 20140167205 | SUPER JUNCTION FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode. | 06-19-2014 |
| 20140175593 | Super Junction Semiconductor Device - A super junction semiconductor device includes a substrate layer of a first conductivity type and an epitaxial layer adjoining the substrate layer and including first columns of the first conductivity type and second columns of a second conductivity type. The first and second columns extend along a main crystal direction into the epitaxial layer and have vertical dopant profiles perpendicular to the first surface. The vertical dopant profile of at least one of the first and second columns includes first portions separated by second portions. In each of the first portions a dopant concentration varies by at most 30% of a maximum value within the respective first portion. In the second portions the dopant concentration is lower than in the adjoining first portions. A ratio of a total length of the first portions to a total length of the first and second portions is at least 50%. | 06-26-2014 |
| 20140284757 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, and a second electrode. The semiconductor substrate is of a first conductivity type. The first semiconductor layer is of a second conductivity type, provided on the semiconductor substrate. The second semiconductor layer is of a first conductivity type, reaches the semiconductor substrate from a surface of the first semiconductor layer, and surrounds the first semiconductor layer. The third semiconductor layer is of a second conductivity type, separated from the second semiconductor layer, surrounded by the second semiconductor layer, and has a higher concentration of second-conductivity-type impurities than the first semiconductor layer. In addition, a withstand voltage between the semiconductor substrate and the third semiconductor layer is lower than the withstand voltage between the second semiconductor layer and the third semiconductor layer. | 09-25-2014 |
| 20150123237 | SEMICONDUCTOR DEVICE - A semiconductor device including field insulating films and having first corner portions, provided on a P-type epitaxial growth layer; an N | 05-07-2015 |
| 20150340432 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. A substrate of a first conductivity type is provided. The substrate has a first area and a second area. An epitaxial layer of a second conductivity type is disposed on the front side of the substrate. A first doped region of the first conductivity type is disposed in the epitaxial layer in the first area, wherein a doping depth of the first doped region is gradually decreased away from the second area. At least one second doped region of the second conductivity type is disposed in the first doped region, wherein a doping depth of the at least one second doped region is gradually increased away from the second area. A dielectric layer is disposed on the epitaxial layer. A first conductive layer is disposed on the dielectric layer. | 11-26-2015 |
| 20150349144 | SEMICONDUCTOR DEVICE - The semiconductor device includes a p-anode region disposed on an n-drift region, and a p-diffusion region disposed so as to be in contact with the p-anode region on the n-drift region. A resistance region disposed so as to be in contact with the p-diffusion region on an n | 12-03-2015 |
| 20150380483 | COMPACT GUARD RING STRUCTURE FOR CMOS INTEGRATED CIRCUITS - An integrated circuit includes a guard ring structure including a guard ring with integrated well taps to reduce the silicon area required for the guard ring structure. In some embodiments, the guard ring structure includes an N-type guard ring surrounded by inner and outer P-type guard rings. The N-type guard ring is formed with interleaving deep N-wells and P-wells that are formed on an N-type buried layer and are electrically shorted together. The inner and outer P-type guard rings are formed in P-wells. The interleaving deep N-wells and P-wells of the N-type guard ring may be connected to ground or be left floating. By integrating P-well contacts in the N-type guard ring, P-well contacts, or P-taps, for the P-type guard ring can be eliminated. | 12-31-2015 |
| 20160013266 | VERTICAL SEMICONDUCTOR DEVICE | 01-14-2016 |
| 20160087110 | SEMICONDUCTOR DEVICE | 03-24-2016 |
| 20160133694 | Structures and Methods with Reduced Sensitivity to Surface Charge - The present application provides (in addition to more broadly applicable inventions) improvements which are particularly applicable to two-sided power semiconductor devices which use bipolar conduction. In this class of devices, the inventor has realized that two or three of the four (or more) semiconductor doping components which form the carrier-emission structures and control structures in the active device (array) portion of a two-sided power device can also be used, with surprising advantages, to form field-limiting rings around the active arrays on both surfaces. Most preferably, in some but not necessarily all embodiments, a shallow implant of one conductivity type is used to counterdope the surface of a well having the other conductivity type. This shallow implant, singly or in combination with another shallow implant of the same conductivity type, works to shield the well from the effects of excess charge at or above the surface of the semiconductor material. | 05-12-2016 |
| 20160172437 | Wide Band Gap Semiconductor Device | 06-16-2016 |
