| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257067000 | In combination with device formed in single crystal semiconductor material (e.g., stacked FETs) | 14 |
| 20080237602 | THREE DIMENSIONAL NAND MEMORY - A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell. | 10-02-2008 |
| 20090140259 | THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device in a high yield are provided. In the thin film transistor, a gate electrode, a gate insulating film, crystal grains that mainly contain silicon and are provided for a surface of the gate insulating film, a semiconductor film that mainly contains germanium and covers the crystal grains and the gate insulating film, and a buffer layer in contact with the semiconductor film that mainly contains germanium overlap with one another. Further, the display device has the thin film transistor. | 06-04-2009 |
| 20090166636 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE TFT - A thin film transistor (TFT), a method of fabricating the same, and display device having the TFT of which the TFT includes a metal catalyst layer disposed on a substrate, a semiconductor layer disposed on the metal catalyst layer, a gate insulating layer disposed on the entire surface of the substrate, a gate electrode disposed on the gate insulating layer at a position corresponding to the semiconductor layer, an interlayer insulating layer disposed on the entire surface of the substrate, and source and drain electrodes disposed on the interlayer insulating layer and connected to the semiconductor layer, wherein the metal catalyst layer includes one of carbon, nitrogen, and halogen. The thin film transistor includes a poly-Si layer that may be formed to a smaller thickness than in conventional deposition methods thereby producing a TFT in which the remaining amount of metal catalyst in a semiconductor layer is reduced. | 07-02-2009 |
| 20120175626 | IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS - A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node. | 07-12-2012 |
| 20140084295 | Transistor Device with Field Electrode - A transistor device includes a semiconductor body having a source region, a drift region, and a body region between the source region and the drift region. A source electrode is electrically coupled to the source region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A field electrode adjacent the drift region is dielectrically insulated from the drift region by a field electrode dielectric and electrically coupled to one of the gate electrode and the source electrode. A rectifier element electrically couples the field electrode to the one of the gate electrode and the source electrode. | 03-27-2014 |
| 20150021609 | SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS - Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments. | 01-22-2015 |
| 20160086980 | GAN TRANSISTORS WITH POLYSILICON LAYERS USED FOR CREATING ADDITIONAL COMPONENTS - A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer. | 03-24-2016 |
| 257068000 | Capacitor element in single crystal semiconductor (e.g., DRAM) | 1 |
| 20090050892 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A CMOS image sensor and method for fabricating same are provided. The CMOS image sensor can include a gate electrode formed on an active area of a first conductive type semiconductor substrate, on which a photodiode area and a transistor area are defined; a low-density second conductive type diffusion region formed on the photodiode area at a first side of the gate electrode; a high-density second conductive the diffusion region formed on the transistor area at a second side of the gate electrode; an insulating layer formed on the semiconductor substrate at both sides of the gate electrode with a thickness less than a thickness of the gate electrode, but greater than a thickness of a gate insulating layer; and insulating layer sidewalls formed on the insulating layer at both sides of the gate electrode. | 02-26-2009 |
| 257069000 | Field effect transistor in single crystal material, complementary to that in non-single crystal, or recrystallized, material (e.g., CMOS) | 4 |
| 20080237603 | METHOD OF FORMING CMOS TRANSISTORS WITH DUAL-METAL SILICIDE FORMED THROUGH THE CONTACT OPENINGS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, and annealing the at least one contact area to form at least one silicide. | 10-02-2008 |
| 20080237604 | PLASMA NITRIDED GATE OXIDE, HIGH-K METAL GATE BASED CMOS DEVICE - In accordance with the invention, there are CMOS devices and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate including a first active region and a second active region and a first transistor device over the first active region, wherein the first transistor device includes a high-K layer over the first active region, a first dielectric capping layer on the high-K layer, and a first metal gate layer over the first dielectric capping layer. The CMOS device can also include a second transistor device over the second active region, wherein the second transistor device includes a high-K layer over the second active region, a second dielectric capping layer on the second high-K layer, and a second metal gate layer over the second dielectric capping layer. | 10-02-2008 |
| 20110073866 | VERTICAL-TYPE SEMICONDUCTOR DEVICE - In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern. | 03-31-2011 |
| 20150102348 | INTEGRATED FINFET-BJT REPLACEMENT METAL GATE - A method of forming a semiconductor structure that includes forming a first recess and a second recess between a first pair of sidewall spacers and a second pair of sidewall spacers respectively, the first and second pair of sidewall spacers surrounding a fin on top of a buried dielectric layer, the fin is formed from a top most semiconductor layer of a semiconductor-on-insulator substrate. A high-k dielectric layer is deposited within the first and second recesses and a dummy titanium nitride layer is deposited on the high-k dielectric layer. The high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess and a silicon cap layer is deposited within the first and second recesses. Next, dopants are implanted into the silicon cap layer in the second recess without implanting dopants into the silicon cap layer in the first recess to form a BJT device. | 04-16-2015 |
| 257070000 | Recrystallized semiconductor material | 2 |
| 20080265256 | MOS devices with improved source/drain regions with SiGe - A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage. | 10-30-2008 |
| 20140175445 | THIN FILM TRANSISTOR ARRAY SUBSTRATE - A thin film transistor array substrate includes a substrate, a plurality of pixel elements arranged on the substrate, each of the pixel elements including a thin film transistor and a pixel electrode electrically connected with the thin film transistor, a light shielding electrode disposed between the substrate and the thin film transistor to shield a channel of the thin film transistor, and a storage capacitor including a first electrode and a second electrode disposed opposite to each other. The light shielding electrode includes a transparent electrically-conductive layer and a non-transparent electrically-conductive layer stacked on top of each other. The first electrode of the storage capacitor is disposed in a same layer and of a same material as the transparent electrically-conductive layer of the light shielding electrode. | 06-26-2014 |
