Class / Patent application number | Description | Number of patent applications / Date published |
257051000 | Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction) | 86 |
20080210936 | Hetero-Crystalline Semiconductor Device and Method of Making Same - A hetero-crystalline semiconductor device and a method of making the same include a non-single crystalline semiconductor layer and a nanostructure layer that comprises a single crystalline semiconductor nanostructure integral to a crystallite of the non-single crystalline semiconductor layer. | 09-04-2008 |
20080210937 | Hetero-Crystalline Structure and Method of Making Same - A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth. | 09-04-2008 |
20080210938 | SEMICONDUCTOR DEVICE - A semiconductor device with superior long-term reliability is disclosed that alleviates current concentration into a switch structure arranged at an outermost portion. The semiconductor device comprises hetero semiconductor regions formed of polycrystalline silicon having a band gap width different from that of a drift region and hetero-adjoined with the drift region, a gate insulation film, a gate electrode adjoined to the gate insulation film, a source electrode connected to a source contact portion of the hetero semiconductor regions and an outermost switch structure and a repeating portion switch structure with a drain electrode connected to a substrate region. In a conduction state, the outermost switch structure comprises a mechanism in which the current flowing at the outermost switch structure becomes smaller than the current flowing at the repeating portion switch structure. | 09-04-2008 |
20080230780 | Group III Nitride Semiconductor Multilayer Structure - An object of the present invention is to provide a Group III nitride semiconductor multilayer structure having a smooth surface and exhibiting excellent crystallinity, which multilayer structure employs a low-cost substrate that can be easily processed. Another object is to provide a Group III nitride semiconductor light-emitting device comprising the multilayer structure. | 09-25-2008 |
20080258145 | Semiconductor Devices Including an Amorphous Region in an Interface Between a Device Isolation Layer and a Source/Drain Diffusion Layer - Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of the silicide layer formed in the interface between the device isolation layer and the source/drain region is reduced. | 10-23-2008 |
20080277662 | SEMICONDUCTOR STRUCTURES - A semiconductor structure is disclosed. The semiconductor structure includes a polycrystal substrate, a first single crystal layer formed thereon and a second single crystal layer formed on the first single crystal layer. A variation of coefficients of thermal expansion (CTE) between the first single crystal layer and the polycrystal substrate is less than 25%. There is no lattice mismatch between the first single crystal layer and the polycrystal substrate. | 11-13-2008 |
20080283832 | Integrated Circuit Comprising an Amorphous Region and Method of Manufacturing an Integrated Circuit - An integrated circuit comprises a doped semiconductor portion including an amorphous portion and a contact structure comprising a conductive material. The contact structure is in contact with the amorphous portion. According to another embodiment, an integrated circuit comprises a doped semiconductor portion including a region having a non-stoichiometric composition and a contact structure comprising a conductive material. The contact structure is in contact with the region having a non-stoichiometric composition. | 11-20-2008 |
20090001371 | BLOCKING PRE-AMORPHIZATION OF A GATE ELECTRODE OF A TRANSISTOR - A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors. | 01-01-2009 |
20090032814 | SiGe DIAC ESD protection structure - A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors. | 02-05-2009 |
20090078936 | SEMICONDUCTOR DEVICE - A PIN diode includes an anode electrode, a P layer, an I layer, an N layer and a cathode electrode. A polysilicon film is formed in a region near the pn junction or n | 03-26-2009 |
20090127555 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF - In order to form a metal thin film, a silicide film, or the like between an upper-layer unit cell and a lower-layer unit cell in stacked-layer photoelectric conversion devices, a step of forming the thin film is additionally needed. Therefore, a problem such as decline in productivity of the photoelectric conversion devices occurs. A first unit cell including a single crystal semiconductor layer with a thickness of 10 μm or less as a photoelectric conversion layer and a second unit cell including a non-single-crystal semiconductor layer as a photoelectric conversion layer, which is provided over the first unit cell, are at least included, and conductive clusters are dispersed between the unit cells. The conductive clusters are located between the lower-layer unit cell and the upper-layer unit cell to form an ohmic contact; thus, current flows between the both unit cells. | 05-21-2009 |
20090146146 | Semiconductor Device formed in a Recrystallized Layer - A semiconductor device includes a substrate that includes a first layer and a recrystallized layer on the first layer. The first layer has a first intrinsic stress and the recrystallized layer has a second intrinsic stress. A transistor is formed in the recrystallized layer. The transistor includes a source region, a drain region, and a charge carrier channel between the source and drain regions. The second intrinsic stress is aligned substantially parallel to the charge carrier channel. | 06-11-2009 |
20090166625 | MOS DEVICE STRUCTURE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 07-02-2009 |
20090206335 | Bipolar complementary semiconductor device - The invention relates to a BiCMOS device comprising a substrate having a first type of conductivity and a number of active regions that are provided therein and are delimited in a lateral direction by flat field-insulating regions. Vertical npn bipolar epitaxial base transistors are disposed in a first partial number of the active regions while vertical pnp bipolar epitaxial base transistors are arranged in a second partial number of the active regions of the BiCMOS device. One transistor type or both transistor types are provided with both a collector region and a collector contact region in one and the same respective active region. In order to improve the high frequency characteristics, an insulation doping region that is configured so as to electrically insulate the collector and the substrate is provided between the collector region and the substrate exclusively in a first transistor type in which the type of conductivity of the substrate corresponds to that of the collector region. In addition, the collector region of the first transistor type or both transistor types is laterally delimited by the flat field-insulating regions. | 08-20-2009 |
20090206336 | Method to fabricate gate electrodes - A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of the layer of nitride to the first layer of oxide. The method further comprises depositing a second layer of oxide and planarizing the oxide to expose at least a portion of the layer of nitride. The method further comprises stripping at least a portion of the layer of nitride to create one or more notches and removing at least a portion of the first layer of oxide. The method further comprises depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into at least one of the one or more notches. | 08-20-2009 |
20090267066 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor and includes an impurity imparting one conductivity type. An amorphous semiconductor layer is deposited on a microcrystalline semiconductor layer by setting the flow rate of a dilution gas (typically silane) to 1 time to 6 times the flow rate of a semiconductor source gas (typically hydrogen) at the time of deposition. Thus, a crystal with a three-dimensional shape tapered in a direction of the deposition of a film, i.e., in a direction from the microcrystalline semiconductor layer to the amorphous semiconductor layer is made to grow. | 10-29-2009 |
20090272975 | Poly-Crystalline Layer Structure for Light-Emitting Diodes - A structure and method for a light-emitting diode are presented. A preferred embodiment comprises a substrate with a conductive, poly-crystalline, silicon-containing layer over the substrate. A first contact layer is epitaxially grown, using the conductive, poly-crystalline, silicon-containing layer as a nucleation layer. An active layer is formed over the first contact layer, and a second contact layer is formed over the active layer. | 11-05-2009 |
20100019242 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, SOI SUBSTRATE AND DISPLAY DEVICE USING THE SAME, AND MANUFACTURING METHOD OF THE SOI SUBSTRATE - A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO | 01-28-2010 |
20100044705 | DOPED SUBSTRATE TO BE HEATED - A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure so that the front face reaches a given temperature when a given infrared power is supplied to the structure. At least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, a method of producing this structure and a method of forming a useful layer of semiconductor material on the structure. | 02-25-2010 |
20100102319 | SPIN INJECTION DEVICE HAVING SEMICONDUCTOR-FERROMAGNETIC-SEMICONDUCTOR STRUCTURE AND SPIN TRANSISTOR - A spin injection device and spin transistor including a spin injection device. A spin injection device includes different semiconductor materials and a spin-polarizing ferromagnetic material there between. The semiconductor materials may have different crystalline structures, e.g., a first material can be polycrystalline or amorphous silicon, and a second material can be single crystalline silicon. Charge carriers are spin-polarized when the traverse the spin-polarizing ferromagnetic material and injected into the second semiconductor material. A Schottky barrier height between the first semiconductor and ferromagnetic materials is larger than a second Schottky barrier height between the ferromagnetic and second semiconductor materials. A spin injection device may be a source of a spin field effect transistor. | 04-29-2010 |
20100140619 | PHOTOVOLTAIC DEVICE - The present invention is related to a photovoltaic device, the device comprising a first layer of a first semiconductor material of a first conductivity type, a second layer of a second semiconductor material of the opposite conductivity type of the first layer, and a third layer of a third porous semiconductor material situated between the first layer and the second layer. The present invention also provides a method for producing the photovoltaic device. | 06-10-2010 |
20100148174 | GaN Epitaxial Wafer and Semiconductor Devices, and Method of Manufacturing GaN Epitaxial Wafer and Semiconductor Devices - Affords GaN epitaxial wafers designed to improve production yields, as well as semiconductor devices utilizing such GaN epitaxial wafers, and methods of manufacturing such GaN epitaxial wafers and semiconductor devices. | 06-17-2010 |
20100171118 | Junction Field-Effect Transistor Having Insulator-Isolated Source/Drain Regions and Fabrication Method Therefor - Junction field-effect transistors (JFETs) having insulator-isolated source/drain regions and fabrication methods therefor are disclosed here. In SOI JFETs and bulk silicon JFETs having junction isolated source and drain regions from the body region, the junction leakage current is one of the leakage components of the off-state leakage current and consequently limits the on-off switching performance. In particular, for short-channel devices (for example, sub-100 nm and/or sub-65 nm devices), the leakage currents are especially pronounced. The techniques herein introduced include JFET with an insulating spacer such that the source and drain regions are insulator isolated from the body region. In one embodiment, the source and drain regions of the transistor are insulator isolated by silicon dioxide thus reducing the source-drain to body junction leakage current and improved on-off performance. | 07-08-2010 |
20100187529 | LASER-IRRADIATED THIN FILMS HAVING VARIABLE THICKNESS - A crystalline film includes a first crystalline region having a first film thickness and a first crystalline grain structure; and a second crystalline region having a second film thickness and a second crystalline grain structure. The first film thickness is greater than the second film thickness and the first and second film thicknesses are selected to provide a crystalline region having the degree and orientation of crystallization that is desired for a device component. | 07-29-2010 |
20100289022 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD - The invention relates to a method of manufacturing a semiconductor device ( | 11-18-2010 |
20100327280 | SCALING OF BIPOLAR TRANSISTORS - Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor. | 12-30-2010 |
20110012110 | SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A gallium nitride based field effect transistor having good current hysteresis characteristics in which forward gate leakage can be reduced. In a gallium nitride-based field effect transistor ( | 01-20-2011 |
20110017992 | THIN FILM TRANSISTOR - A thin film transistor includes a first insulating layer covering the gate electrode layer; source and drain regions which at least partly overlaps with the gate electrode layer; a pair of second insulating layers which is provided apart from each other in a channel length direction over the first insulating layer and which at least partly overlaps with the gate electrode layer and the pair of impurity semiconductor layers; a pair of microcrystalline semiconductor layers provided apart from each other on and in contact with the second insulating layers; and an amorphous semiconductor layer covering the first insulating layer, the pair of second insulating layers, and the pair of microcrystalline semiconductor layers and which extends to exist between the pair of microcrystalline semiconductor layers. The first insulating layer is a silicon nitride layer and each of the pair of the second insulating layers is a silicon oxynitride layer. | 01-27-2011 |
20110042672 | Coplanar waveguide having amorphous silicon layer between substrate and insulated layer and a manufacturing method thereof - A coplanar waveguide includes a high resistance silicon substrate having one primary surface on which an amorphous silicon layer is formed, an insulated layer formed on the amorphous silicon layer, a signal line arranged on the insulated layer and a pair of ground planes arranged on the insulated layer so as to put the signal line between the planes. The coplanar waveguide is not structured as conventionally having a thick insulated layer formed on a single-crystalline silicon substrate, thereby reducing attenuation otherwise caused by leakage of electromagnetic wave in a frequency bandwidth of millimeter wave. | 02-24-2011 |
20110049517 | BIPOLAR TRANSISTOR - A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector. | 03-03-2011 |
20110133187 | PHOTO DETECTOR AND METHOD OF MANUFACTURING THE SAME - Provided is a manufacturing method of a photo detector. The method includes: forming a first single crystal semiconductor layer and an optical waveguide protruding from the first single crystal semiconductor layer; forming an insulation layer on the first single crystal semiconductor layer to cover the optical waveguide; forming an opening by etching the insulation layer to expose the top surface of the optical waveguide; forming a second single crystal semiconductor layer from the top surface of the exposed optical waveguide, in the opening; and selectively forming a poly semiconductor layer from the top surface of the second single crystal semiconductor layer, the poly semiconductor layer being doped with dopants. | 06-09-2011 |
20110133188 | Process for Simultaneous Deposition of Crystalline and Amorphous Layers with Doping - One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics. | 06-09-2011 |
20110180795 | ELECTRO-OPTIC DEVICE AND A METHOD FOR MANUFACTURING THE SAME - An electro-optic device is disclosed. The electro-optic device includes an insulating layer, a first semiconducting region disposed above the insulating layer and being doped with doping atoms of a first conductivity type, a second semiconducting region disposed above the insulating layer and being doped with doping atoms of a second conductivity type and an electro-optic active region disposed above the insulating layer and between the first semiconducting region and the second semiconducting region. The electro-optic active region includes a first semiconducting partial active region being doped with doping atoms of the first conductivity type, a second semiconducting partial active region being doped with doping atoms of the second conductivity type and an insulating structure between the first semiconducting partial active region and the second semiconducting partial active region, wherein the insulating structure extends perpendicular to the surface of the insulating layer such that there is no overlap of the first semiconducting partial active region and the second semiconducting partial active region in the direction perpendicular to the surface of the insulating layer. A method for manufacturing an electro-optic device is also disclosed. | 07-28-2011 |
20110186841 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A semiconductor device ( | 08-04-2011 |
20110198591 | METHOD OF MANUFACTURING HETEROJUNCTION BIPOLAR TRANSISTOR AND HETEROJUNCTION BIPOLAR TRANSISTOR - Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer ( | 08-18-2011 |
20110204360 | Photoelectric Conversion Device And Manufacturing Method Thereof - In order to form a metal thin film, a silicide film, or the like between an upper-layer unit cell and a lower-layer unit cell in stacked-layer photoelectric conversion devices, a step of forming the thin film is additionally needed. Therefore, a problem such as decline in productivity of the photoelectric conversion devices occurs. A first unit cell including a single crystal semiconductor layer with a thickness of 10 μm or less as a photoelectric conversion layer and a second unit cell including a non-single-crystal semiconductor layer as a photoelectric conversion layer, which is provided over the first unit cell, are at least included, and conductive clusters are dispersed between the unit cells. The conductive clusters are located between the lower-layer unit cell and the upper-layer unit cell to form an ohmic contact; thus, current flows between the both unit cells. | 08-25-2011 |
20110215322 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm | 09-08-2011 |
20110248265 | Backside texturing by cusps to improve IR response of silicon solar cells and photodetectors - The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing comprises a plurality of cusped features providing diffusive scattering. Constructing the solar cell with a smooth front surface results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. | 10-13-2011 |
20110278570 | SCALING OF BIPOLAR TRANSISTORS - Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor. | 11-17-2011 |
20120074404 | SUPPORTING SUBSTRATE, BONDED SUBSTRATE, METHOD FOR MANUFACTURING SUPPORTING SUBSTRATE, AND METHOD FOR MANUFACTURING BONDED SUBSTRATE - Provided is a supporting substrate ( | 03-29-2012 |
20120074405 | Process for the Simultaneous Deposition of Crystalline and Amorphous Layers with Doping - One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics. | 03-29-2012 |
20120112188 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, MANUFACTURING METHOD THEREOF, AND LAMP - A semiconductor light-emitting device which includes: a single-crystal substrate formed with a plurality of projection portions on a c-plane main surface; an intermediate layer which is formed to cover the main surface of the single-crystal substrate, in which a film thickness t | 05-10-2012 |
20120112189 | SPIN INJECTION DEVICE HAVING SEMICONDUCTOR-FERROMAGNETIC-SEMICONDUCTOR STRUCTURE AND SPIN TRANSISTOR - A spin injection device and spin transistor including a spin injection device. A spin injection device includes different semiconductor materials and a spin-polarizing ferromagnetic material there between. The semiconductor materials may have different crystalline structures, e.g., a first material can be polycrystalline or amorphous silicon, and a second material can be single crystalline silicon. Charge carriers are spin-polarized when the traverse the spin-polarizing ferromagnetic material and injected into the second semiconductor material. A Schottky barrier height between the first semiconductor and ferromagnetic materials is larger than a second Schottky barrier height between the ferromagnetic and second semiconductor materials. A spin injection device may be a source of a spin field effect transistor. | 05-10-2012 |
20120112190 | EPITAXIAL SILICON WAFER AND METHOD FOR MANUFACTURING SAME - It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A silicon epitaxial layer is grown by a CVD method on the surface of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration. After that, a PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced. | 05-10-2012 |
20120132913 | III-V Compound Semiconductor Material Passivation With Crystalline Interlayer - The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure. | 05-31-2012 |
20120146023 | THERMAL EXPANSION ENGINEERING FOR POLYCRYSTALLINE ALUMINUM NITRIDE SINTERED BODIES - Disclosed are methods and materials useful in the preparation of semiconductor devices. In particular embodiments, disclosed are methods for engineering polycrystalline aluminum nitride substrates that are thermally matched to further materials that can be combined therewith. For example, the polycrystalline aluminum nitride substrates can be engineered to have a coefficient of thermal expansion (CTE) that is closely matched to the CTE of a semiconductor material and/or to a material that can be used as a growth substrate for a semiconductor material. The invention also encompasses devices incorporating such thermally engineered substrates and semiconductor materials grown using such thermally engineered substrates. The thermally engineered substrates are advantageous for overcoming problems caused by damage arising from CTE mismatch between component layers in semiconductor preparation methods and materials. | 06-14-2012 |
20120181536 | Hybrid Silicon Wafer - A hybrid silicon wafer which is a silicon wafer having a structure wherein the main plane orientation of polycrystalline silicon that is prepared by a unidirectional solidification/melting method is (311), and monocrystalline silicon is embedded in the polycrystalline silicon. The hybrid silicon wafer according to any one of claims | 07-19-2012 |
20120193623 | CARBON ADDITION FOR LOW RESISTIVITY IN SITU DOPED SILICON EPITAXY - Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device. The devices include epitaxial layers having a resistivity of less than about 0.381 milliohm-centimeters. | 08-02-2012 |
20120228611 | BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE - Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base. | 09-13-2012 |
20120235143 | VERTICAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter. | 09-20-2012 |
20120241741 | SILICON CARBIDE SUBSTRATE - A first single crystal substrate has a first side surface and it is composed of silicon carbide. A second single crystal substrate has a second side surface opposed to the first side surface and it is composed of silicon carbide. A bonding portion connects the first and second side surfaces to each other between the first and second side surfaces, and it is composed of silicon carbide. At least a part of the bonding portion has polycrystalline structure. Thus, a large-sized silicon carbide substrate allowing manufacturing of a semiconductor device with high yield can be provided. | 09-27-2012 |
20120298995 | WAFER AND EPITAXIAL WAFER, AND MANUFACTURING PROCESSES THEREFOR - Provided is a silicon wafer which is stabilized in quality exerting no adverse influence on device characteristics and manufactured by restricting a boron contamination from the environment, and a manufacturing process therefor. Concretely, the silicon wafer is characterized by an attached boron amount thereon being 1×10 | 11-29-2012 |
20130009153 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion. | 01-10-2013 |
20130056731 | Semiconductor Device and Method for Manufacturing the Semiconductor Device - A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region. | 03-07-2013 |
20130069065 | SILICON CARBIDE MOSFET WITH HIGH MOBILITY CHANNEL - A semiconductor device may include a semiconductor body of silicon carbide (SiC) and a field effect transistor. The field effect transistor has the semiconductor body that includes a drift region. A polycrystalline silicon layer is formed over or on the semiconductor body, wherein the polycrystalline silicon layer has an average particle size in the range of 10 nm to 5 μm, and includes a source region and a body region. Furthermore, the field effect transistor includes a layer adjacent to the body region gate structure. | 03-21-2013 |
20130075729 | Fin-Based Bipolar Junction Transistor and Method for Fabrication - According to one exemplary embodiment, a fin-based bipolar junction transistor (BJT) includes a wide collector situated in a semiconductor substrate. A fin base is disposed over the wide collector. Further, a fin emitter and an epi emitter are disposed over the fin base. A narrow base-emitter junction of the fin-based BJT is formed by the fin base and the fin emitter and the epi emitter provides increased current conduction and reduced resistance for the fin-based BJT. The epi emitter can be epitaxially formed on the fin emitter and can comprise polysilicon. Furthermore, the fin base and the fin emitter can each comprise single crystal silicon. | 03-28-2013 |
20130075730 | VERTICAL PNP DEVICE IN A SILICON-GERMANIUM BICMOS PROCESS AND MANUFACTURING METHOD THEREOF - A vertical PNP device in a silicon-germanium (SiGe) BiCMOS process is disclosed. The device is formed in a deep N-well and includes a collector region, a base region and an emitter region. The collector region has a two-dimensional L-shaped structure composed of a lightly doped first P-type ion implantation region and a heavily doped second P-type ion implantation region. The collector region is picked up by P-type pseudo buried layers formed at bottom of the shallow trench field oxide regions. A manufacturing method of vertical PNP device in a SiGe BiCMOS process is also disclosed. The method is compatible with the manufacturing processes of a SiGe heterojunction bipolar transistor in the SiGe BiCMOS process. | 03-28-2013 |
20130092939 | BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film. | 04-18-2013 |
20130153902 | STRUCTURES INCLUDING PASSIVATED GERMANIUM - A passivated germanium surface that is a germanium carbide material formed on and in contact with the germanium material. A semiconductor device structure having the passivated germanium having germanium carbide material on the substrate surface is also disclosed. | 06-20-2013 |
20130175529 | Semiconductor Diode and Method for Forming a Semiconductor Diode - A semiconductor diode is provided. The semiconductor diode includes a monocrystalline silicon semiconductor body including a first semiconductor region of a first conductivity type extending to a first surface of the semiconductor body and having a first maximum doping concentration, and a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region. The semiconductor diode further includes a polycrystalline silicon semiconductor region of the first conductivity type having a second maximum doping concentration which is higher than the first maximum doping concentration and adjoining the first semiconductor region on the first surface, a first metallization arranged on the polycrystalline silicon semiconductor region and in electric contact with the polycrystalline semiconductor region, and an edge-termination structure arranged next to the first semiconductor region. Further, a method for producing a semiconductor diode is provided. | 07-11-2013 |
20130214275 | TRANSISTOR HAVING A NARROW IN-SUBSTRATE COLLECTOR REGION FOR REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region. | 08-22-2013 |
20130264569 | SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT - In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article. | 10-10-2013 |
20130285060 | UNIT FOR LIQUID PHASE EPITAXIAL GROWTH OF MONOCRYSTALLINE SILICON CARBIDE, AND METHOD FOR LIQUID PHASE EPITAXIAL GROWTH OF MONOCRYSTALLINE SILICON CARBIDE - The cost of liquid phase epitaxial growth of a monocrystalline silicon carbide is reduced. A feed material | 10-31-2013 |
20130313551 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction. | 11-28-2013 |
20130313552 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer. | 11-28-2013 |
20140048805 | BONDING-SUBSTRATE FABRICATION METHOD, BONDING SUBSTRATE, SUBSTRATE BONDING METHOD, BONDING-SUBSTRATE FABRICATION APPARATUS, AND SUBSTRATE ASSEMBLY - [Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the interface with the substrate is surface-treated using energetic particles/metal particles. | 02-20-2014 |
20140061647 | Field-Effect Semiconductor Device and Manufacturing Method Therefor - According to an embodiment of a field-effect semiconductor device, the field-effect semiconductor device includes a semiconductor body and a source electrode. The semiconductor body includes a drift region, a gate region and a source region of a first semiconductor material having a first band-gap and an anode region of a second semiconductor material having a second band-gap lower than the first band-gap. The drift region is of a first conductivity type. The gate region forms a pn-junction with the drift region. The source region is of the first conductivity type and in resistive electric connection with the drift region and has a higher maximum doping concentration than the drift region. The anode region is of the second conductivity type, forms a heterojunction with the drift region and is spaced apart from the source region. The source metallization is in resistive electric connection with the source region and the anode region. | 03-06-2014 |
20140097433 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE DEVICE - A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals. | 04-10-2014 |
20140138687 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium. | 05-22-2014 |
20140246676 | BIPOLAR DEVICE HAVING A MONOCRYSTALLINE SEMICONDUCTOR INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION - A bipolar device with an entirely monocrystalline intrinsic base to extrinsic base link-up region. To form the device, a first extrinsic base layer, which is amorphous or polycrystalline, is deposited such that it contacts an edge portion of a monocrystalline section of an intrinsic base layer through an opening in a dielectric layer. A second extrinsic base layer is deposited on the first. An anneal is performed, either before or after deposition of the second extrinsic base layer, so that the extrinsic base layers are monocrystalline. An opening is formed through the extrinsic base layers to a dielectric landing pad aligned above a center portion of the monocrystalline section of the intrinsic base layer. The dielectric landing pad is removed and a semiconductor layer is grown epitaxially on exposed monocrystalline surfaces of the extrinsic and intrinsic base layers, thereby forming the entirely monocrystalline intrinsic base to extrinsic base link-up region. | 09-04-2014 |
20140252358 | Methods and Apparatus for MEMS Devices with Increased Sensitivity - Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed. | 09-11-2014 |
20140264343 | DEVICE ARCHITECTURE AND METHOD FOR TEMPERATURE COMPENSATION OF VERTICAL FIELD EFFECT DEVICES - A field effect device is disclosed that provides a reduced variation in on-resistance as a function of junction temperature. The field effect device, having a source junction, gate junction and drain junction, includes a resistive thin film adjacent the drain junction wherein the resistive thin film comprises a material having a negative temperature coefficient of resistance. The material is selected from one or more materials from the group consisting of doped polysilicon, amorphous silicon, silicon-chromium and silicon-nickel, where the material properties, such as thickness and doping level, are chosen to create a desired resistance and temperature profile for the field effect device. Temperature variation of on-resistance for the disclosed field effect device is reduced from the temperature variation for a similar field effect device without the resistive thin film. | 09-18-2014 |
20140291681 | PHASE NOISE REDUCTION IN TRANSISTOR DEVICES - Semiconductor devices are disclosed having modified transistor dimensions configured to provide reduced phase noise in certain amplifier applications. Transistor devices having expanded emitter-poly overlap of the emitter window, which serves to separate the external base area from the lateral emitter-base junction, may experience a reduction of free electrons and holes that diffuse into the electric field of the emitter-base junction, thereby reducing phase noise. | 10-02-2014 |
20140361300 | BIPOLAR DEVICE HAVING A MONOCRYSTALLINE SEMICONDUCTOR INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION - Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers. A semiconductor layer is then formed by epitaxial deposition on the exposed monocrystalline surfaces, thereby forming the entirely monocrystalline link-up region. | 12-11-2014 |
20150041811 | Power Transistor - A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width. | 02-12-2015 |
20150053981 | METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE - A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess. | 02-26-2015 |
20150053982 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer. | 02-26-2015 |
20150303188 | BiCMOS Integration with Reduced Masking Steps - A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and an NPN bipolar device in the bipolar region. The NPN bipolar device has an extrinsic base being self-aligned with an emitter of the NPN bipolar device. The extrinsic base of the NPN bipolar device and an emitter of the PNP bipolar device share a P type dopant. | 10-22-2015 |
20150340431 | ZENER DIODE HAVIING A POLYSILICON LAYER FOR IMPROVED REVERSE SURGE CAPABILITY AND DECREASED LEAKAGE CURRENT - A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material. | 11-26-2015 |
20160043203 | SELF-ALIGNED EMITTER-BASE BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE AND BASE-COLLECTOR CAPACITANCE - Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor. | 02-11-2016 |
20160049503 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer. | 02-18-2016 |
20160093615 | Power Transistor - A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width. | 03-31-2016 |
20160093722 | BIPOLAR TRANSISTOR - A bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region. | 03-31-2016 |
20160169833 | BIOSENSOR BASED ON HETEROJUNCTION BIPOLAR TRANSISTOR | 06-16-2016 |
20160190249 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region. | 06-30-2016 |
20190148560 | SYNAPTIC SEMICONDUCTOR DEVICE AND NEURAL NETWORKS USING THE SAME | 05-16-2019 |