| Entries |
| Document | Title | Date |
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| 20080197351 | TESTKEY DESIGN PATTERN FOR GATE OXIDE - A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction. | 08-21-2008 |
| 20080197352 | BUMP STRUCTURE ON SUBSTRATE - A bump structure on a substrate including at least one first electrode, at least one first bump, at least one second bump is provided. The first electrode is disposed on the substrate. The first bump is disposed on the first electrode. The second bump is disposed on the substrate. The height of the second bump is greater than that of the first bump. The elastic bump of the present invention can be used for measuring the bonding process quality. | 08-21-2008 |
| 20080197353 | SEMICONDUCTOR DEVICE FOR WHICH ELECTRICAL TEST IS PERFORMED WHILE PROBE IS IN CONTACT WITH CONDUCTIVE PAD - A semiconductor device that comprises a conductive pad that is provided on the insulating film and that is obtained by forming a main conductive film and a surface conductive film harder than the main conductive film in that order. | 08-21-2008 |
| 20080203388 | Apparatus and method for detection of edge damages - Embodiments of the invention enable detection of edge damages in semiconductor devices. To this purpose, one or more continuity structures may be provided, where each structure comprises an undulating arrangement disposed between active circuits of the semiconductor device and a perimeter of the metallization layers. The continuity structure(s) forms one or more conductive paths intersecting a plurality of metallization layers in the semiconductor device. A relative change in an electrical characteristic of the continuity structure(s) is monitored to ascertain whether or not an edge damage is present. | 08-28-2008 |
| 20080210935 | Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method - A semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the plurality of chip areas from each other. The bonding pad is configured to be connected with an external terminal. The probing pad is configured to be contacted with a probe wire. The pad connection wiring is configured to electrically connect the bonding pad to the probing pad. The bonding pad and the probing pad are located at a predetermined distance from each other in each of the plurality of chip areas. The pad connection wiring has a portion located in the scribe line area. | 09-04-2008 |
| 20080217612 | STRUCTURE AND METHOD OF MAPPING SIGNAL INTENSITY TO SURFACE VOLTAGE FOR INTEGRATED CIRCUIT INSPECTION - Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage. | 09-11-2008 |
| 20080217613 | POSITIONAL OFFSET MEASUREMENT PATTERN UNIT FEATURING VIA-PLUG AND INTERCONNECTIONS, AND METHOD USING SUCH POSITIONAL OFFSET MEASUREMENT PATTERN UNIT - In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be electrically connected to the first interconnection. A second interconnection is formed in the insulating layer at substantially the same level as the first interconnection so as to be spaced from the first interconnection by a given distance. A voltage is applied between the first and second interconnections to measure a relative positional offset amount between the via-plug and the second interconnection. | 09-11-2008 |
| 20080217614 | Systems and Methods for Controlling of Electro-Migration - Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed. | 09-11-2008 |
| 20080217615 | Method for arranging chips of a first substrate on a second substrate - The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the second substrate in such a way that each of the first chips on the second substrate is unambiguously assigned to the associated first chip on the first substrate. | 09-11-2008 |
| 20080224134 | Test Structures for Identifying an Allowable Process Margin for Integrated Circuits and Related Methods - A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality of floating conductive lines are provided, each of the plurality of conductive lines being spaced apart from the grounded conductive lines and electrically separated from the grounded conductive lines on the substrate. A plurality of supplementary patterns are provided for measuring the allowable process margin by a voltage contrast between the grounded conductive lines and the floating conductive lines. Related methods of testing are also provided. | 09-18-2008 |
| 20080224135 | METHOD AND STRUCTURE FOR DETERMINING THERMAL CYCLE RELIABILITY - A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling. | 09-18-2008 |
| 20080237586 | Semiconductor Integrated Test Structures For Electron Beam Inspection of Semiconductor Wafers - Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features. | 10-02-2008 |
| 20080237587 | Method and circuit for stressing upper level interconnects in semiconductor devices - A device or method for effectively stressing an interconnect in a test current path of a semiconductor device, which test current path is other than a current path used during normal operation of the semiconductor device. An operational voltage is adjusted to a test voltage, the test current path is opened and the test voltage is supplied to the test current path. | 10-02-2008 |
| 20080237588 | METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES - By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified. | 10-02-2008 |
| 20080237589 | Semiconductor device comprising circuit substrate with inspection connection pads and manufacturing method thereof - A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof, respectively. A second circuit substrate is provided on a lower side of the first circuit substrate, the second circuit substrate having an opening which exposes part of the first circuit substrate, the second circuit substrate also having, on the lower surface side thereof, a plurality of external-connection connection pads and a plurality of test connection pads connected to the lower wiring lines. A first semiconductor construct is disposed on the lower side of the first circuit substrate within the opening of the second circuit substrate, the first semiconductor construct having a plurality of external connection electrodes connected to the lower wiring lines. A third circuit substrate and/or an electronic component is provided on an upper side of the first circuit substrate and connected to the upper wiring lines. | 10-02-2008 |
| 20080237590 | DESIGN STRUCTURE FOR ELECTRICALLY TUNABLE RESISTOR - A design structure for an electrically tunable resistor. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes a resistor including: a first resistive layer; at least one second resistive layer; and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. | 10-02-2008 |
| 20080237591 | Vertical system integration - The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs. | 10-02-2008 |
| 20080237592 | Semiconductor device and its test method - A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module. | 10-02-2008 |
| 20080246030 | TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS - Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area. | 10-09-2008 |
| 20080246031 | PCM pad design for peeling prevention - A semiconductor structure is provided. The semiconductor structure includes a semiconductor chip and a scribe line adjoining the semiconductor chip. A conductive feature is formed in the scribe line and exposed on the surface of the scribe lines, wherein the conductive feature has an edge facing the semiconductor chip. A kerf path is in the scribe line. A first cut is formed in the conductive feature, wherein the first cut extends from the first edge to the kerf path. | 10-09-2008 |
| 20080246032 | TEST STRUCTURE FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS - A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area. | 10-09-2008 |
| 20080251787 | Thin film transistor substrate and flat panel display comprising the same - A thin film transistor (TFT) substrate includes a TFT that including a gate electrode, a source electrode, and a drain electrode formed on an insulating substrate divided into a display area and a non-display area to provide test driving signals provided from the outside to the display area, a test signal line connected to the drain electrode of the TFT, a pad unit signal line insulated from the test signal line by an insulating layer and connected to signal lines formed in the display area, and a jumping pad electrode electrically connecting the test signal line and the pad unit signal line to each other through a contact hole that penetrates the insulating layer, connected to a driving circuit for driving the display area, and providing driving signals provided from the driving circuit to the pad unit signal line and a flat panel display (FPD) including the same. | 10-16-2008 |
| 20080251788 | Wafer-level package having test terminal - A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member. | 10-16-2008 |
| 20080258144 | SEMICONDUCTOR WAFER, SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING SEMICONDUCTOR CHIP - A semiconductor wafer of the present invention is provided with a substrate having a semiconductor element formation layer, a lowermost metal layer formed on the semiconductor element formation layer and an uppermost layer formed on the lowermost metal layer, and the semiconductor wafer also has plural chip regions and an evaluation element region that is that is defined as a region between the plurality of chip regions and that has a cutaway region that is subjected to dicing when separating an individual chip and a remnant region that is not subjected to dicing when separating the chip, and a lowermost layer electrode pad and an uppermost layer electrode pad that are formed at the remnant region and at a pad region are configured by a combination of metals having a line width of less than or equal to a predetermined value. | 10-23-2008 |
| 20080265247 | UNIFIED TEST STRUCTURE FOR STRESS MIGRATION TESTS - A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration. | 10-30-2008 |
| 20080265248 | Leadframe Configuration to Enable Strip Testing of SOT-23 Packages and the Like - A sacrificial lead and a common lead hold a die paddle of each integrated circuit SOT-23 package to a leadframe within a strip of leadframes after isolating signal leads from the leadframe. Strip testing of most devices in the SOT-23 three and five lead packages may then be performed. The common lead may be at the center of an edge of the SOT-23 package. Also the common lead may be any one of the leads of the SOT-23 package. In addition the sacrificial lead may be at the center of an opposite edge of the SOT-23 package. | 10-30-2008 |
| 20080265249 | STACKED SEMICONDUCTOR DEVICE ASSEMBLY AND PACKAGE - In a stacked semiconductor device assembly, solder balls | 10-30-2008 |
| 20080265250 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, an active device array, an detecting circuit, a plurality of driver chip pads, a plurality of flexible printed circuit (FPC) pads, a plurality of connection lines and an inner shorting ring is provided. The active device array and the detecting circuit are disposed on the substrate, and the detecting circuit is electrically connected to the active device array. The driver chip pads and the FPC pads are disposed on the substrate, wherein the driver chip pads are electrically connected to the active device array. The connection lines are disposed on the substrate, and each of the connection lines is respectively connected to the detecting circuit and the corresponding FPC pad. The inner shorting ring is disposed on the substrate, and the inner shorter ring is respectively electrically connected to the corresponding FPC pad and the active device array. | 10-30-2008 |
| 20080265251 | STRUCTURE AND METHOD FOR DETERMINING A DEFECT IN INTEGRATED CIRCUIT MANUFACTURING PROCESS - The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas. | 10-30-2008 |
| 20080265252 | Semiconductor device - Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex. | 10-30-2008 |
| 20080272371 | RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D | 11-06-2008 |
| 20080272372 | Test structures for stacking dies having through-silicon vias - A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads. | 11-06-2008 |
| 20080272373 | Flash Memory Device Having Resistivity Measurement Pattern and Method of Forming the Same - A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to be measured even in the SAFG scheme. Contacts for resistivity measurement are directly connected to the resistivity measurement floating gate. Therefore, variation in resistivity measurement values, which is incurred by the parasitic interface, can be reduced. | 11-06-2008 |
| 20080277659 | Test structure for semiconductor chip - A test structure for use in a semiconductor chip. In a preferred embodiment, a number of die are formed in an array on a semiconductor wafer substrate. Each die includes an active area defined by a seal ring and is separated from those adjacent to it by a thin scribe line. In addition to the operational structures formed in the active area of each die, one or more test structures are formed. In a preferred embodiment, these test structures are formed into one or more PCM (process control monitor) test pattern layout areas that are positioned near the seal ring and outside of the operational bond pads. Some or all of individual pads in the PCM test pattern layout area may then be connected to corresponding features on adjacent dice, and in some applications enable the simultaneous performance of WAT (wafer acceptance test) and CP (circuit probe) testing. | 11-13-2008 |
| 20080277660 | Semiconductor Device, Manufacturing Method Thereof, and Measuring Method Thereof - To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed. | 11-13-2008 |
| 20080277661 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A technique of manufacturing a semiconductor device capable of performing a probe test by a common test apparatus as normal LSI chips even for large-area chips is provided. A chip comprising a device formed on a device area by a semiconductor process and including a plurality of test areas sectioned by chip areas is prepared. Next, pads to be electrically connected to the device are formed at corresponding positions on the respective plurality of test areas. Subsequently, the respective test areas are tested by a same probe card via the plurality of pads. | 11-13-2008 |
| 20080290340 | Method for fabricating a semiconductor device having embedded interconnect structures to improve die corner robustness - In a method for fabricating a semiconductor device a redundant scribe seal structure is formed. The semiconductor device includes a die having a rectangular shape with sloped corners. A scribe seal is formed to surround the die, the scribe seal having sides to form sloped corners that match the sloped corners of the die. A scribe seal extension having sharp corners is formed by extending the sides of the scribe seal that have a perpendicular orientation towards one another. The scribe seal extension redundantly encloses a corresponding one of the sloped corners of the scribe seal. | 11-27-2008 |
| 20080290341 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME - A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal circuit; a second switch arranged between the through electrode and the test wiring; and a control circuit that exclusively turns on the first and the second switches. Thereby, it becomes possible to perform an insulation test in a state that the through electrode and the internal circuit are cut off. Thus, even when a slight short-circuit that does not lead to a current defect occurs, the short circuit can be detected. | 11-27-2008 |
| 20080290342 | METHODS AND APPARATUS FOR A FLEXIBLE CIRCUIT INTERPOSER - A substrate having a bending region and conductive paths formed therethrough is provided. In one embodiment, conductive paths are formed from a first region on the bottom surface of the substrate, through the bending region and to a second region on the top surface of the substrate. Methods of using the flexible substrate are also provided. | 11-27-2008 |
| 20080296570 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer. | 12-04-2008 |
| 20080296571 | MULTI-PROJECT WAFER AND METHOD OF MAKING SAME - A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type. | 12-04-2008 |
| 20080303021 | Optimized Thermally Conductive Plate and Attachment Method for Enhanced Thermal Performance and Reliability of Flip Chip Organic Packages - Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature. | 12-11-2008 |
| 20080308798 | Semiconductor Device - A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and assembly are provided in a first area above a main surface of the semiconductor substrate, an application of pressure by a probe during the probing test being permitted in the first area, and a plurality of assembly pads which are not used in the probing test are provided in a second area above the main surface of the semiconductor substrate, the application of pressure by the probe during the probing test being not permitted in the second area. | 12-18-2008 |
| 20080308799 | WIRING STRUCTURE AND MANUFACTURING METHOD THEREFOR - A wiring structure including a wiring pattern formed in an insulation film on a substrate, a pattern for measurement which is formed in the insulation film on the substrate in a region different from a region where the wiring pattern is formed and is irradiated with measuring light, and a light transmission inhibiting film formed directly below the pattern for measurement, wherein the pattern for measurement is the same pattern as the wiring pattern, and the light transmission inhibiting film is made of a material having light transmissivity that is smaller than light transmissivity of a material of the insulation film forming the pattern for measurement. | 12-18-2008 |
| 20080308800 | METHOD OF EVALUATING THERMAL STRESS RESISTANCE OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR WAFER HAVING TEST ELEMENT - A thermal stress resistance evaluating method of a semiconductor device includes: forming a test circuit on a corner of each of unit regions arranged on a wafer in an array arrangement; forming a TEG chip by dicing a TEG chip region which is determined by grouping at least two of the unit regions in a predetermined shape; assembling a packaged TEG chip from the TEG chip; and executing a temperature cycling test on the packaged TEG chip by using the test circuit on the TEG chip. According to such a configuration, by adjusting the predetermined shape, the packaged TEG chip of various sizes can be formed in accordance with the design of the product chip size. | 12-18-2008 |
| 20080308801 | STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION - A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter. | 12-18-2008 |
| 20080315195 | Method and Apparatus for Monitoring VIA's in a Semiconductor Fab - A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured. | 12-25-2008 |
| 20080315196 | TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER - The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed. | 12-25-2008 |
| 20090001364 | Semiconductor Device - Plural I/O cells ( | 01-01-2009 |
| 20090001365 | MEMORY CARD FABRICATED USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 01-01-2009 |
| 20090001366 | Wafer Arrangement and Method for Manufacturing a Wafer Arrangement - A wafer arrangement in accordance with an embodiment of the invention includes a wafer having a plurality of dice, wherein at least some of the dice have a first connection, and at least one contact pad formed at the wafer edge, wherein a plurality of first connections are coupled by means of a section of a redistribution layer and the contact pad is formed by the section of the redistribution layer. | 01-01-2009 |
| 20090001367 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, STACKED MODULE INCLUDING THE SAME, CARD INCLUDING THE SAME, AND SYSTEM INCLUDING THE STACKED MODULE - A semiconductor device in which a plurality of chips can be reliably stacked without reducing integration thereof. The semiconductor device includes a substrate on which a circuit is provided. Pads are disposed on the substrate for testing the circuit. At least one terminal is provided on the substrate. First conductors are used to electrically couple the pads and the circuit. Second conductors are used to electrically couple the at least one terminal and the circuit. A switching element is disposed in the middle of the first conductors to control the electrical connection between the pads and the circuit. A plurality of semiconductor devices may be stacked on top of one another to form a stacked module, wherein chip selection lines are formed, which extend to the bottom of each of the semiconductor devices to electrically couple chip selection terminals from among the at least one terminal of the semiconductor devices. | 01-01-2009 |
| 20090001368 | Semiconductor device including semiconductor evaluation element, and evaluation method using semiconductor device - Provided are a semiconductor evaluation element capable of analytically estimating the amount of DC variation of a MOS transistor which is caused by formed contacts, and an evaluation circuit and an evaluation method using the semiconductor evaluation element. The semiconductor evaluation element such as a MOS transistor includes: a gate; diffusion layers; measurement contacts; and floating contacts. The diffusion layers are formed on both sides of the gate and serve as a source and a drain. The measurement contacts are provided in positions apart from the gate on the diffusion layers. The floating contacts are provided between the gate and the measurement contacts to connect electrically isolated metal layers with the diffusion layers. | 01-01-2009 |
| 20090001369 | Evaluation method for interconnects interacted with integrated-circuit manufacture - A design and evaluation method for interconnect wires of integrated circuits is provided to detect, analyze and predict response of interconnect layout to integrated-circuit manufacture processes. | 01-01-2009 |
| 20090001370 | Method and apparatus for extracting properties of interconnect wires and dielectrics undergoing planarization process - The present invention provides a novel solution for simultaneously extracting the properties of the interconnect wires and the inter-wire dielectrics exposed to the IC planarization process. | 01-01-2009 |
| 20090008640 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bonding pads as bonding option, and a test circuit for performing an operation test using particular bonding pads and testing interconnects connecting internal circuits to the remaining bonding pads which are not used in the operation test. | 01-08-2009 |
| 20090008641 | Probe resistance measurement method and semiconductor device with pads for probe resistance measurement - A probe resistance measuring method includes measuring first resistances at three or more nodes by making contact at least a part of a plurality of probes of a probe unit with three or more pads for resistance measurement based on a first correspondence relation. The measured resistances are stored as a first measurement result and contact resistances of the plurality of probes of the probe unit are calculated based on the first measurement result. | 01-08-2009 |
| 20090014717 | TEST IC STRUCTURE - A test IC structure is described, which is disposed in a scribe line region of a wafer and includes first and second test keys, first and second conductive plugs, first and second test pads, and a passivation layer over the scribe line region. The first/second test key includes a first/second active device and a first/second interconnect structure electrically connected thereto, wherein the second test key is arranged substantially parallel with the first one. The first/second plug is disposed over the first/second interconnect structure and contacts with the upmost metal layer thereof. The first/second test pad is disposed over the first and the second test keys and contacts with the first/second conductive plug. The passivation layer has therein a first opening exposing a portion of the first test pad and a second opening exposing a portion of the second test pad. | 01-15-2009 |
| 20090014718 | TEST ELEMENT GROUP FOR MONITORING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A test element group for monitoring leakage current in a semiconductor device and a method of manufacturing the same are disclosed. The test element group for monitoring leakage current in a semiconductor device includes device isolation layers formed over a first conductivity type semiconductor substrate. A second conductivity type well may be formed over the first conductivity type semiconductor substrate. First conductivity type impurity regions may be formed in first active areas between the device isolation layers in the second conductivity type well. Monitoring contacts may be formed within the first active areas to monitor leakage current, using layout data such that a distance from each of the monitoring contacts to a border of each of the first active areas is set to have an allowable minimum value under a predetermined design rule. Accordingly, the test element group can monitor leakage current caused by PN junction diodes formed by junction of the impurity regions and the well in the active areas in a semiconductor device or misalignment of contacts, and can accurately monitor micro-leakage current in a semiconductor device during manufacturing. | 01-15-2009 |
| 20090020754 | Test structure for determining gate-to-body tunneling current in a floating body FET - In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regions. The floating body test structure further includes a second gate and a first contact situated over the first source/drain region. A gate-to-channel current measured between the second gate and the first contact is utilized to determine the gate-to-body tunneling current. The gate-to-body tunneling current can be determined by subtracting the gate-to-channel current from twice a source/drain current of the floating body FET. The test structure may also include a second contact situated on a doped region in the semiconductor layer, where a diode current flow through the doped region determines a body voltage for the floating body FET. | 01-22-2009 |
| 20090020755 | TEST STRUCTURE OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A test structure includes a transistor, a dummy transistor and a pad unit. The transistor is formed on a first active region of a substrate. The dummy transistor is formed on a second active region of the substrate and electrically connected to the transistor. The pad unit is electrically connected to the transistor. Plasma damage to the transistor is reduced due to the presence of dummy transistor. | 01-22-2009 |
| 20090020756 | Test structures of a semiconductor device and methods of forming the same - A test structure including a transistor, a conductive pattern and a pad unit is provided. The transistor may be formed on a substrate having circuit patterns. The conductive pattern is electrically connected to the transistor. The conductive pattern may be used in aligning the circuit patterns and/or sensing plasma damage to the semiconductor device. The conductive pattern may be used in reducing etching damage to the circuit patterns and sensing plasma damage to the semiconductor device. The pad unit is electrically connected to the transistor, and provides electrical signals to the transistor. The conductive pattern may serve as an antenna pattern and/or an align/overlay pattern or a dummy pattern. | 01-22-2009 |
| 20090032813 | Test Wafer, Manufacturing Method Thereof and Method for Measuring Plasma Damage - Embodiments of the present invention provide a test wafer capable of analyzing plasma damage, a manufacturing method thereof, and a method for measuring plasma damage using the same. A test wafer according to an embodiment includes a transistor device having at least one probe contact and a gate insulating film comprising a charging trap layer. The plasma process in the process for manufacturing the semiconductor device can be optimized by using the test wafer to determine plasma damage, making it possible to inhibit defect occurrence and malfunction of the semiconductor device and extend the life of the gate insulating layer. | 02-05-2009 |
| 20090039347 | PROGRAMMING A MICROCHIP ID REGISTER - A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip. | 02-12-2009 |
| 20090039348 | MULTIPLE TESTING BARS FOR TESTING LIQUID CRYSTAL DISPLAY AND METHOD THEREOF - A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines. | 02-12-2009 |
| 20090045400 | Method for monitoring fuse integrity in a semiconductor die and related structure - According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs. | 02-19-2009 |
| 20090050885 | Semiconductor wafers and methods of fabricating semiconductor devices - A semiconductor wafer includes a plurality of unitary semiconductor chips formed on a semiconductor substrate. Scribe lane region separate the unitary semiconductor chips from each other. Test element group (TEG) pads are configured to apply testing signals for testing respective test elements. A TEG pad is arranged such that an acute angle formed at an intersection of a line extending from portion of a perimeter of the TEG pad and at least a portion of the outer edge of a corresponding scribe lane region is greater than 0° and less than or equal to 60°. | 02-26-2009 |
| 20090050886 | Test device, SRAM test device, semiconductor integrated circuit device and methods of fabricating the same - A test device, SRAM test device, semiconductor integrated circuit, and methods of fabricating the same are provided. The test device may include a first test active region extending in one direction on a semiconductor substrate, a second test active, apart from the first test active region, extending in one direction on a semiconductor substrate, a plurality of test gate lines crossing the test active regions, a plurality of test contacts on at least one of the test active regions and test gate lines, a plurality of conducting regions electrically connecting the test contacts, and a plurality of conductive wiring lines interconnecting the plurality of test contacts, wherein an open contact chain, which electrically connects the plurality of test contacts, is formed. | 02-26-2009 |
| 20090050887 | CHIP ON FILM (COF) PACKAGE HAVING TEST PAD FOR TESTING ELECTRICAL FUNCTION OF CHIP AND METHOD FOR MANUFACTURING SAME - A chip on film (COF) package comprising a test pad for testing the electrical function of a semiconductor chip and a method for manufacturing same are provided. The COF package comprises a semiconductor chip mounted on a base film, a signal-input portion for receiving data and control signals and transmitting the data and control signals to the semiconductor chip, a plurality of passive elements connected to terminals of the semiconductor chip, and a plurality of test pads for testing one or more terminals of the semiconductor chip that are not connected to the signal-input portion. The test pads of the COF package are capable of testing a plurality of internal terminals which are integrated into one terminal and do not connected to the signal-input portion, thereby easily testing the electrical function of the chip. | 02-26-2009 |
| 20090057664 | E-BEAM INSPECTION STRUCTURE FOR LEAKAGE ANALYSIS - A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/ one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage. | 03-05-2009 |
| 20090057665 | Power managing semiconductor die with reduced power consumption - According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block. | 03-05-2009 |
| 20090065772 | APPARATUS FOR DETECTING PATTERN ALIGNMENT ERROR - An apparatus for detecting pattern alignment error includes a first conductive pattern disposed over a first insulation member with a power source applied to the first conductive pattern; a second insulation member for covering the first conductive pattern; a second conductive pattern disposed on the second insulation member; a conductive via connected to the second conductive pattern and passing through the second insulation member; and an insulation pattern disposed in the first conductive pattern for detecting an alignment error in response to a position of the conductive via. The apparatus for detecting pattern alignment error can detect the alignment of lower wiring in a device with multi-layer wiring | 03-12-2009 |
| 20090065773 | SEMICONDUCTOR DEVICE - Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip. | 03-12-2009 |
| 20090065774 | MULTILAYER SEMICONDUCTOR DEVICE - The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation. | 03-12-2009 |
| 20090065775 | TEST-KEY FOR CHECKING INTERCONNECT AND CORRESPONDING CHECKING METHOD - A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages. | 03-12-2009 |
| 20090072234 | Test Stuctures for development of metal-insulator-metal (MIM) devices - In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto. | 03-19-2009 |
| 20090078935 | SEMICONDUCTOR DEVICE - Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region. | 03-26-2009 |
| 20090085030 | INCREASED RELIABILITY FOR A CONTACT STRUCTURE TO CONNECT AN ACTIVE REGION WITH A POLYSILICON LINE - By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria. | 04-02-2009 |
| 20090085031 | Wafer-Shaped Measuring Apparatus and Method for Manufacturing the Same - The present invention provides a temperature measuring apparatus with favorable temperature measuring performance and a method of manufacturing the same. A temperature measuring apparatus ( | 04-02-2009 |
| 20090090908 | Providing A Duplicate Test Signal Of An Output Signal Under Test In An Integrated Circuit - Providing a duplicate test signal of an output signal under test in an integrated circuit including selecting through a multiplexer an output signal under test, the output signal under test selected from a plurality of output signals of the integrated circuit; providing through the multiplexer a duplicate signal of the selected output signal under test; adding a high impedance load on the duplicate signal thereby reducing the amplitude of the duplicate signal; and amplifying the reduced duplicate signal thereby creating the duplicate test signal. | 04-09-2009 |
| 20090095955 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF - A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection signal. The detector activates the detection signal in response to the check signal. | 04-16-2009 |
| 20090101896 | SEMICONDUCTOR DEVICE - In a semiconductor device, a semiconductor chip is connected to a board through an interconnection layer. A plurality of first terminals, a plurality of second terminals and a plurality of third terminals are provided on the board, the interconnection layer and the semiconductor chip, respectively. The second terminals are connected to the first terminals through the board. The third terminals are connected to the second terminals. The interconnection layer is rotatable about a rotation axis perpendicular to an upper surface of the interconnection layer. A first terminal having a specific function out of the first terminals and a third terminal having the specific function out of the third terminals are connected to each other by rotating the interconnection layer. | 04-23-2009 |
| 20090101897 | PACKAGE FOR A LIGHT EMITTING ELEMENT - A high-brightness LED module includes a substrate with a recess in which a light emitting element is mounted. The recess is defined by a sidewalls and a relatively thin membrane. At least two micro-vias are provided in the membrane and include conductive material that passes through the membrane. A p-contact of the light emitting element is coupled to a first micro-via and an n-contact of the light emitting element is coupled to a second micro-via. | 04-23-2009 |
| 20090101898 | METHOD AND RESULTING STRUCTURE FOR FABRICATING TEST KEY STRUCTURES IN DRAM STRUCTURES - A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1. | 04-23-2009 |
| 20090108257 | CRITICAL DIMENSION FOR TRENCH AND VIAS - Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings. | 04-30-2009 |
| 20090108258 | Semiconductor Device And Method for Fabricating The Same - A semiconductor device and a method for fabricating the same are disclosed, which are capable of improving the performance and the production yield of the device. The semiconductor device may include a semiconductor wafer having semiconductor chips thereon, a lower metal layer on the semiconductor wafer, a dielectric layer on the lower metal layer, upper conductive layers on the dielectric layer, separated into a plurality of pieces; and a passivation layer enclosing lateral sides of the pieces of the upper conductive layer. Accordingly, when dicing and separating the respective chips on the semiconductor wafer, the upper metal layer does not lift off the dielectric layer. Therefore, the performance and the production yield of the semiconductor device can be enhanced. | 04-30-2009 |
| 20090114912 | MASK DESIGN ELEMENTS TO AID CIRCUIT EDITING AND MASK REDESIGN - An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing. | 05-07-2009 |
| 20090114913 | TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES - A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C | 05-07-2009 |
| 20090114914 | High performance sub-system design and assembly - A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry. | 05-07-2009 |
| 20090121220 | High performance sub-system design and assembly - A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry. | 05-14-2009 |
| 20090121221 | High performance sub-system design and assembly - A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry. | 05-14-2009 |
| 20090121222 | Test Structure - A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads. | 05-14-2009 |
| 20090121223 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips. | 05-14-2009 |
| 20090127553 | WAFER WITH SCRIBE LANES COMPRISING EXTERNAL PADS AND/OR ACTIVE CIRCUITS FOR DIE TESTING - A wafer (W) comprises i) at least one independent die (D | 05-21-2009 |
| 20090134391 | High performance sub-system design and assembly - A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry. | 05-28-2009 |
| 20090140244 | SEMICONDUCTOR DEVICE INCLUDING A DIE REGION DESIGNED FOR ALUMINUM-FREE SOLDER BUMP CONNECTION AND A TEST STRUCTURE DESIGNED FOR ALUMINUM-FREE WIRE BONDING - In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon. | 06-04-2009 |
| 20090140245 | Structure for a Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS Process - A design structure of a method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not. | 06-04-2009 |
| 20090140246 | METHOD AND TEST STRUCTURE FOR MONITORING CMP PROCESSES IN METALLIZATION LAYERS OF SEMICONDUCTOR DEVICES - By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency. | 06-04-2009 |
| 20090140247 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions. | 06-04-2009 |
| 20090140248 | On-Chip Test Circuit for an Embedded Comparator - A semiconductor chip including an embedded comparator is provided with an on-chip test circuit for the comparator. The test circuit includes an analog input unit which, during a test mode of the chip, produces a range of analog voltage signals that are applied to a first input of the comparator and a threshold voltage signal that is applied to a second input of the comparator. A switch control unit is provided to control the application of a predetermined sequential pattern of these analog voltage signals to the first input of the comparator in synchrony with a clock signal supplied to the switch control unit during a predetermined test period. A digital measurement unit is provided to receive output signals from the comparator during the test period in response to the input patterns, to compare the output signals with the clock signal, and to measure and to store data relating thereto. | 06-04-2009 |
| 20090146143 | TEST STRUCTURE FOR DETERMINING OPTIMAL SEED AND LINER LAYER THICKNESSES FOR DUAL DAMASCENE PROCESSING - A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions. | 06-11-2009 |
| 20090146144 | Method and system supporting production of a semiconductor device using a plurality of fabrication processes - There is provided a tuning method for use by a semiconductor device capable of being fabricated using a plurality of fabrication processes comprising reading a fabrication identification included in the semiconductor device, associating the fabrication identification with one of the plurality of fabrication processes to determine an associated fabrication process used for fabrication of the semiconductor device, and tuning at least one parameter of the semiconductor device based on the associated fabrication process. | 06-11-2009 |
| 20090146145 | PROCESSING CONDITION INSPECTION AND OPTIMIZATION METHOD OF DAMAGE RECOVERY PROCESS, DAMAGE RECOVERING SYSTEM AND STORAGE MEDIUM - A processing condition inspection method of a damage recovery process for reforming a film having OH groups generated by damages from a predetermined process by using a processing gas includes preparing a substrate having an OH group containing resin film, measuring an initial film thickness of the OH group containing resin film, performing a damage recovery process on the substrate after measuring the initial film thickness, measuring a film thickness of the OH group containing resin film after the damage recovery process, calculating a film thickness difference of the OH group containing resin film before and after the damage recovery process, and determining whether processing conditions of the damage recovery process are appropriate or inappropriate based on the film thickness difference. | 06-11-2009 |
| 20090152542 | TESTING THE QUALITY OF LIFT-OFF PROCESSES IN WAFER FABRICATION - Test methods and components are disclosed for testing the quality of lift-off processes in wafer fabrication. A wafer is populated with one or more test components along with the functional components. These test components are fabricated with holes in an insulation layer that is deposited between conductive layers, where the holes were created by the same or similar lift-off process that is used to fabricate the functional components on the wafer. The test components may then be measured in order to determine the quality of the holes created by the lift-off process. The quality of the lift-off process used to fabricate the functional components may then be determined based on the quality of the holes in the test components. | 06-18-2009 |
| 20090152543 | System, Structure and Method of Providing Dynamic Optimization of Integrated Circuits Using a Non-Contact Method of Selection, and a Design Structure - A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit resides. The method is provided for optimizing an electronic system having at least one integrated circuit. The method includes storing a target performance voltage of the at least one integrated circuit; remotely querying the at least one integrated circuit to obtain the target performance voltage; and providing an operational voltage of a next-level assembly according to the stored target performance voltage. | 06-18-2009 |
| 20090152544 | DISGUISING TEST PADS IN A SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads. | 06-18-2009 |
| 20090152545 | Feature Dimension Measurement - A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared. | 06-18-2009 |
| 20090152546 | WAFER WITH SCRIBE LANES COMPRISING ACTIVE CIRCUITS FOR DIE TESTING OF COMPLEMENTARY SIGNAL PROCESSING PARTS - A wafer (W) comprises at least one die (D | 06-18-2009 |
| 20090152547 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base integrated circuit, by: providing a metal sheet, mounting an integrated circuit die on the metal sheet, injecting a molded package body on the integrated circuit die and the metal sheet, and forming a ball pad, a bond finger, or a combination thereof from the metal sheet that is not protected by the molded package body; coupling a circuit package on the ball pad; and forming a component package on the substrate, the base integrated circuit, and the leadframe interposer. | 06-18-2009 |
| 20090152548 | Semiconductor Component - A semiconductor component (has at least one semiconductor chip in which an electrical circuit is integrated. The semiconductor chip is surrounded by an electrically insulating encapsulating compound and has on its surface at least one termination surface for a test signal, which is covered by the encapsulating compound. The termination surface is connected in an electrically conductive manner to an analysis contact that projects above the surface of the semiconductor chip, that is located in the interior of the encapsulating compound at a distance from its exterior surface, and that can be exposed by removing a layer of the encapsulating compound located near the exterior. | 06-18-2009 |
| 20090159881 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - The present invention is a method for manufacturing a semiconductor apparatus including a chip which is fabricated in large numbers on a wafer and has a plurality of information blocks. In the method, a unique information bit is written in a chip discrimination block of each chip | 06-25-2009 |
| 20090159882 | Test Pattern of Semiconductor Device and Manufacturing Method Thereof - A test pattern of a semiconductor device and manufacturing method thereof are provided. The test pattern can include an isolation layer on a semiconductor substrate to define an active area, a gate electrode on the active area, and a source/drain area at a first area of the active area between the gate electrode and the isolation layer, a third area of the active area spaced apart from the gate electrode, and a second area of the active area electrically connecting the first area with the third area. | 06-25-2009 |
| 20090159883 | TEST PATTERN FOR SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE TEST PATTERN - A test pattern for a semiconductor device and a method for forming the test pattern that can determine the degree of over etching of contact holes and obviate the need to perform a physical analysis using SEM, FIB or the like after the wafer is destroyed. | 06-25-2009 |
| 20090166617 | INTEGRATED CIRCUIT AND METHOD FOR OPERATING - An integrated circuit and a method for operating an integrated circuit is disclosed. One embodiment provides a semi-conductor component, an electronic system, and a method for operating an integrated circuit. A method for operating an integrated circuit provides applying a voltage to a line or a connection in accordance with data to be input. A current is applied to the line or the connection in accordance with data to be output. | 07-02-2009 |
| 20090166618 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 07-02-2009 |
| 20090166619 | TEST PATTERN OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a test pattern for a semiconductor device includes the steps of forming, on a semiconductor substrate, a moat mask pattern including plural moat lines patterned in a comb-shape and etching a portion of the semiconductor substrate exposed by the moat mask pattern, to form a trench. The method further includes gap-filling the trench with an insulation material to form a field separator, planarizing the semiconductor substrate having the field separator formed thereon, and forming a poly comb pattern on the planarized semiconductor substrate. The poly comb pattern is formed such that the moat lines are arranged between lines of the poly comb pattern. | 07-02-2009 |
| 20090166620 | SEMICONDUCTOR CHIP - In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit. | 07-02-2009 |
| 20090166621 | RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D | 07-02-2009 |
| 20090184316 | Method to extract gate to source/drain and overlap capacitances and test key structure therefor - A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region. | 07-23-2009 |
| 20090189157 | Device for measuring or inspecting substrates of the semiconductor industry - A device for measuring or inspecting substrates of the semiconductor industry, including a base frame and a module detachably mounted thereon via a module frame, wherein the module frame is detachably connected to the base frame via at least two self-aligning coupling elements and at least one alignment element, wherein the base frame and the module frame are in exactly defined spatial alignment with each other, when the module frame is detachably connected to the base frame. | 07-30-2009 |
| 20090189158 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wring board having a first surface with external connection terminals and a second surface with internal connection terminals. On the second surface of the wiring board, a semiconductor chip having electrode pads is mounted. The electrode pads of the semiconductor chip and the internal connection terminals of the wiring board are electrically connected via connecting members. The external connection terminals are arranged along two opposite outer sides of the wiring board and each have a rectangular shape elongated in a direction toward the outer side. | 07-30-2009 |
| 20090194768 | Vertical system integration - The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs. | 08-06-2009 |
| 20090200546 | Test Structures and Methods - Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece. | 08-13-2009 |
| 20090200547 | TRENCH DEPTH MONITOR FOR SEMICONDUCTOR MANUFACTURING - A method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor substrate and determining an etch ratio. The least one device trench and at least one monitor trench are simultaneously formed in the first main surface of the semiconductor material layer. The at least one monitor trench is monitored to detect when it extends to a second depth position. A ratio of the first depth position to the second depth position is generally equal to the etch ratio. | 08-13-2009 |
| 20090200548 | GUARD RING EXTENSION TO PREVENT REALIABILITY FAILURES - An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation. | 08-13-2009 |
| 20090200549 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer. | 08-13-2009 |
| 20090206334 | DISPLAY SUBSTRATE, DISPLAY PANEL HAVING THE SAME, AND METHOD OF TESTING A DISPLAY SUBSTRATE - A display substrate includes a gate wire, a data wire which crosses the gate wire, a display part, a dummy pixel part and a test part. The display part includes a pixel element electrically connected to the gate wire and the data wire, and the pixel element includes a display element. The dummy pixel part surrounds the display part to protect the pixel element from static electricity. The test part is formed adjacent to the display part and includes a test element having a test display element formed in a substantially same manner as the display element. | 08-20-2009 |
| 20090212284 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads. | 08-27-2009 |
| 20090236599 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate at least including a substrate, a plurality of pixel units, a plurality of first signal lines, a first connecting wire, a plurality of first switching devices, and a plurality of second signal lines is provided. The pixel units are disposed within an active area. One ends of two neighbouring first signal lines are respectively connected to a first test line and a second test line. The other ends of the two neighbouring first signal lines are both connected to the first switching devices. Moreover, the first connecting wire is electrically connected to the first switching devices. One ends of two neighbouring second signal lines are respectively connected to a third test line and a fourth test line. | 09-24-2009 |
| 20090242882 | THREE-DIMENSIONAL MICROSTRUCTURES AND METHODS FOR MAKING SAME - Microstructures can be formed as patterned layers on a substrate and then erecting the microstructures out of the plane of the substrate. The microstructures may be formed over circuits in the substrate. In some embodiments the patterned layer provides resiliently-flexible members such as cantilevers or springs that can be buckled to permit an edge defined by the patterned layer to engage a surface of the substrate. In some embodiments deformation of the resiliently-flexible members results the edge being forced against the substrate. Such microstructures may be applied in a wide range of applications including supporting optical elements, sensors, antennas or the like out of the plane of a substrate. Examples of accelerometer structures are described. | 10-01-2009 |
| 20090250697 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - Methods for detecting a void in an element portion of a semiconductor device having an element portion and a void detection structure are disclosed. As a part of the method, an insulating film is formed on a substrate, a plurality of holes is formed in the insulating film, and a metal portion is formed on the insulating film to fill the plurality of holes. The metal portion is polished until the insulating film is exposed and a recessed portion is formed in the void detection structure. It is determined if a void exists in the element portion of the semiconductor device by determining whether or not a void is exposed at a surface of the recessed portion of the void detection structure. | 10-08-2009 |
| 20090250698 | FABRICATION MANAGEMENT SYSTEM - With the evolution of technology, there is a continual demand for enhanced speed, capacity and efficiency. A modular, chip testing system associated with a single chip on a wafer is described. This system includes a performance structure for measuring chip performance during a testing period; a power structure for measuring chip power during the testing period; an interconnect structure for measuring characteristics of interconnects within the chip during the testing period; a device structure for measuring characteristics of devices within the chip during the testing period; and a plurality of probe pads coupled to the performance structure, power structure, interconnect structure, and the device structure, wherein the plurality of probe pads receive signals during the testing period that enable the modular, chip testing system to measure characteristics of the interconnects, characteristics of the devices, chip power, and chip performance. | 10-08-2009 |
| 20090256149 | Structure for Measuring Body Pinch Resistance of High Density Trench MOSFET Array - A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes:
| 10-15-2009 |
| 20090261326 | DIE TESTING USING TOP SURFACE TEST PADS - Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size. | 10-22-2009 |
| 20090272973 | Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line - The present invention discloses a semiconductor wafer having a scribe line dividing the semiconductor wafer into a matrix of plural semiconductor chips. The semiconductor wafer includes a polysilicon layer, a poly-metal interlayer insulation film formed on the polysilicon layer, and a first metal wiring layer formed on the poly-metal interlayer insulation film. The semiconductor wafer includes a process-monitor electrode pad formed on a dicing area of the scribe line. The process-monitor electrode pad has a width greater than the width of the dicing area. The process-monitor electrode pad includes a contact hole formed in the poly-metal insulation film for connecting the first metal wiring layer to the polysilicon layer. | 11-05-2009 |
| 20090272974 | Interposer chip and multi-chip package having the interposer chip - An interposer chip may include an insulating substrate, conductive patterns, and a test pattern. The conductive patterns may be formed on the insulating substrate. Further, the conductive patterns may be electrically connected to conductive wires. The test pattern may be connected to the conductive patterns. A test current for testing an electrical connection between the conductive patterns and the conductive wires may flow through the test pattern. Thus, the interposer chip may have the test pattern connected to the conductive patterns, so that the test current may flow to the test pattern through the conductive wires and the conductive patterns. As a result, an electrical connection between the conductive wires and the conductive patterns may be identified based on the test current supplied to the test pattern. | 11-05-2009 |
| 20090278123 | TESTING WIRING STRUCTURE AND METHOD FOR FORMING THE SAME - The invention provides a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The testing wiring structure comprises a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring. The gate layer metallic testing wiring are connected to a portion of the plurality of signal lines and the drain layer metallic testing wiring both are connected to remaining portion of the plurality of signal lines. A pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring. The pixel electrode layer testing wiring is electrically connected to the drain layer metallic testing wiring to be a redundant testing wiring of the drain layer metallic testing wiring. | 11-12-2009 |
| 20090278124 | SCRIBE BASED BOND PADS FOR INTEGRATED CIRCUITS - An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad. | 11-12-2009 |
| 20090283764 | TEG PATTERN FOR DETECTING VOID IN DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME - Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer. | 11-19-2009 |
| 20090283765 | SEMICONDUCTOR UNIT - A semiconductor unit includes a semiconductor chip, a ceramic substrate having a circuit pattern on which the semiconductor chip is mounted, and a temperature sensor for detecting a temperature. The semiconductor unit further includes a pressing member for retaining the temperature sensor by pressing against the ceramic substrate. | 11-19-2009 |
| 20090289253 | Semiconductor Wafer and Method of Forming Sacrificial Bump Pad for Wafer Probing During Wafer Sort Test - A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each interconnect bump pad and proximate sacrificial bump pad. The sacrificial bump pads, interconnect bump pads, and conductive link are formed concurrently or during bump formation. The wafer is electrically tested by contacting the sacrificial bump pads. The electrical test identifies known good die and defective die. The sacrificial bump pads and a portion of the conductive link are removed after wafer probing. Bumps are formed over the interconnect bump pads. The semiconductor wafer can be sold or transferred to a third party after wafer probing without bumps. | 11-26-2009 |
| 20090302317 | SWITCHING DEVICE AND TESTING APPARATUS - There is provided a switching device that electrically connects or disconnects a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, where the floating gate retains a charge therein, and a tunnel gate that is formed on the floating gate, the tunnel gate supplying a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate. | 12-10-2009 |
| 20090309097 | TESTING DEVICE ON WATER FOR MONITORING VERTICAL MOSFET ON-RESISTANCE - The present invention is to provide a testing device on wafer for monitoring vertical MOSFET on-resistance, formed on a substrate and the substrate comprising a first testing region; and a second testing region; wherein the first testing region and the second testing region are vertical MOSFETs respectively, which comprise at least a common gate region, at least a common drain region, and a plurality of source regions which are separated for each corresponding testing region. | 12-17-2009 |
| 20090309098 | INTERCONNECTION OF ELECTRONIC DEVICES WITH RAISED LEADS - An embodiment of a process of manufacturing an interconnection element for contacting electronic devices is proposed. The process starts with the step of forming a plurality of leads on a main surface of a first substrate; each lead has a first end and a second end. The second end of each lead is coupled with a second substrate. The second substrate and the first substrate are then spaced apart, so as to extend the leads between the first substrate and the second substrate. The process also includes the step of treating the main surface before forming the leads to control an adhesion of the leads on the main surface. | 12-17-2009 |
| 20090315028 | Semiconductor substrate and production process thereof - A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitoring pattern, the first film-thickness monitoring pattern and the first pattern group having a third area occupation ratio on the surface, while the second film-thickness monitoring pattern and the second pattern group having a fourth area occupation ratio on the surface, wherein the third area occupation ratio is different from the fourth area occupation ratio. | 12-24-2009 |
| 20090315029 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING TERMINAL FOR MEASURING BUMP CONNECTION RESISTANCE AND SEMICONDUCTOR DEVICE PROVIDED WITH THE SAME - An integrated circuit is formed in a chip. Positioning marks are provided on at least two of four regions respectively near four corners of a first main surface of the chip. Terminals are provided on the first main surface to measure bump connection resistance. The terminals adjoin the positioning marks respectively. A connection wire is provided in the chip. The connection wire is connected to the terminals electrically. | 12-24-2009 |
| 20090321734 | CAPACITOR-BASED METHOD FOR DETERMINING AND CHARACTERIZING SCRIBE SEAL INTEGRITY AND INTEGRITY LOSS - One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed. | 12-31-2009 |
| 20100001268 | Semiconductor Device and Method of Shunt Test Measurement for Passive Circuits - A semiconductor device has an inductor and capacitor formed on the substrate. The inductor and capacitor are electrically connected in series. The inductor is a coiled conductive layer. The capacitor has first and second conductive layers separated by an insulating layer. A first test pad and second test pad are formed on the substrate. A terminal of the inductor is coupled to the first and second test pads. A third test pad and fourth test pad are formed on the substrate. A terminal of the capacitor is coupled to the third and fourth test pads such that the inductor and capacitor are connected in shunt between the first and second test pads and the third and fourth test pads. An electrical characteristic of the inductor and capacitor such that resonant frequency and quality factor are tested using a two-port shunt measurement which negates series resistance of test probes. | 01-07-2010 |
| 20100001269 | Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate - In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions. | 01-07-2010 |
| 20100006838 | ACTIVE MATRIX SUBSTRATE, DISPLAY DEVICE, AND ACTIVE MATRIX SUBSTRATE INSPECTING METHOD - By feeding inspection signals independent from each other to upper first and second gate lead inspection lines ( | 01-14-2010 |
| 20100006839 | METHOD OF MANUFACTURING TFT SUBSTRATE AND TFT SUBSTRATE - In a method of manufacturing a TFT substrate in accordance with an exemplary aspect of the present invention, an intrinsic semiconductor film, an impurity semiconductor film, and a conductive film for source lines are formed in succession, and a resist having a thin-film portion and a thick-film portions is formed on the conductive film for source lines. Then, etching is performed by using the resist as a mask, and after that, a part of the conductive film for source lines is exposed by removing the thin-film portion of the resist. Next, the exposed conductive film for source lines is etched by using the thick-film portions of the resist a mask, so that the impurity semiconductor film is exposed. Then, by etching the exposed impurity semiconductor film, a back channel region of a TFT | 01-14-2010 |
| 20100012933 | TEST DEVICE AND A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A test device includes a semiconductor substrate having a first test region and a second test region defined thereon, wherein a layout of the first test region includes a pair of first active regions separated from each other by isolation regions in the semiconductor substrate, a pair of second active regions formed between the first active regions, a pair of first gate lines formed on the semiconductor substrate, wherein each of the first gate lines has a first end adjacent to one of the first active regions and a second end adjacent to an end of one of the second active regions, respectively, a pair of first shared contacts each formed over a respective one of the second ends of the first gate lines and an upper part of one of the first active regions, and a pair of first nodes formed on the first shared contacts to be electrically connected to the first shared contacts, respectively, and wherein a layout of the second test region includes a pair of third active regions, a pair of fourth active regions, a pair of second shared contacts, and a pair of second nodes, wherein the pair of third active regions is surrounded by the isolation regions in the semiconductor substrate to correspond to the first active regions, the pair of fourth active regions is formed between the third active regions to correspond to the second active regions, each of the pair of second shared contacts is formed on part of one of the second active regions and parts of one of the isolation regions, respectively, to correspond to the first shared contacts, and the pair of second nodes is formed to correspond to the first nodes to be electrically connected to the second shared contacts, respectively. | 01-21-2010 |
| 20100012934 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP STACKED PACKAGE - A semiconductor chip in a semiconductor chip stacked package may include a semiconductor substrate formed with a semiconductor device, an insulating layer over the semiconductor substrate, a deep via passing through the semiconductor substrate and the insulating layer, an interconnection layer electrically connecting the semiconductor device with the deep via, and a test device electrically connected with both the deep via and the interconnection layer. | 01-21-2010 |
| 20100019241 | SEMICONDUCTOR DEVICE, FABRICATION METHOD THEREOF, AND PHOTOMASK - There is provided a semiconductor device including a wafer and a focus monitoring pattern formed on the wafer. The focus monitoring pattern has at least one pair of first and second patterns. The first pattern has an unexposed region surrounded by an exposed region and the second pattern has an exposed region surrounded by an unexposed region. In addition, the present invention provides a method of fabricating a semiconductor device comprising the steps of forming at least one pair of first and second patterns on a wafer. The first pattern has an unexposed region surrounded by an exposed region and the second pattern has an exposed region surrounded by an unexposed region. The method further comprises checking a focusing condition on exposure by measuring widths of the first and second patterns formed on the wafer. | 01-28-2010 |
| 20100025681 | IC CHIP PACKAGE AND IMAGE DISPLAY DEVICE INCORPORATING SAME - A liquid crystal driver mounting package in accordance with an embodiment of the present invention contains a film base material and a liquid crystal driver connected to each other via an interposer. The liquid crystal driver includes first alignment marks on its face opposite the interposer. The interposer includes second alignment marks on its face opposite the liquid crystal driver. The first alignment marks and the second alignment marks are separated by about a distance which is in a tolerable range as a combining position where the liquid crystal driver and the interposer are attached when viewed from the normal of the face of the interposer opposite the liquid crystal driver. Thus, an IC chip (liquid crystal driver) package is provided which enables efficient positing of the IC chip and the interposer. | 02-04-2010 |
| 20100025682 | Interface device for wireless testing, semiconductor device and semiconductor package including the same, and method for wirelessly testing using the same - In an interface device for wireless testing capable of testing a semiconductor chip in a non-contact manner, a semiconductor device and a semiconductor package including the same, and a method for wirelessly testing a semiconductor device using the same are provided, the interface device for wireless testing includes an interface substrate, interface antennas on the interface substrate, and interface transmitting and receiving circuits on the interface substrate, wherein the interface transmitting and receiving circuits are electrically connected to input/output pads of a semiconductor chip via interface vias passing through the interface substrate. | 02-04-2010 |
| 20100032669 | SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING TEST MODES WITHOUT STOPPING TEST - A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state. | 02-11-2010 |
| 20100032670 | ELECTRICAL TEST STRUCTURE TO DETECT STRESS INDUCED DEFECTS USING DIODES - A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects. | 02-11-2010 |
| 20100032671 | DEGRADATION CORRECTION FOR FINFET CIRCUITS - A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a digital-to-analog-converter (DAC), is connected to the control gate of one of the finFETs, is disclosed. Threshold measurement circuits on the signal gates enable a threshold adjustment voltage from the adjustable voltage source to reduce the threshold mismatch between the finFETs. Adding a second DAC to the second finFET allows a simpler DAC design. Threshold correction may be performed during the operational life of the IC. Implementations in a differential input stage of an amplifier and in a current mirror circuit are described. | 02-11-2010 |
| 20100038640 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment of the invention, an array substrate includes a first test line, a second test line, a first source line group, a second source line group, a plurality of gate lines and a switching device. The first test line extends along a first direction. The second test line is substantially in parallel with the first test line. The first source line group that extends along a second direction that is substantially perpendicular to the first direction, and electrically connected to the first test line. The second source line group extends along the second direction and is electrically connected to the second test line. Each of the gate lines extends along the first direction. The switching device is formed on a region surrounded by the first source line, the second source line and the gate lines. Therefore, defects induced by static electricity generated during manufacturing process are reduced. | 02-18-2010 |
| 20100051944 | SILICON PROCESSING METHOD AND SILICON SUBSTRATE WITH ETCHING MASK - A silicon processing method includes: forming a mask pattern on a principal plane of a single-crystal silicon substrate; and applying crystal anisotropic etching to the principal surface to form a structure including a (111) surface and a crystal surface equivalent thereto and having width W | 03-04-2010 |
| 20100065846 | SYSTEM IN PACKAGE AND SOCKET - This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost. | 03-18-2010 |
| 20100072473 | TACK ADHESION TESTING DEVICE - A tack adhesion testing device for quantitatively measuring tack adhesion between a material and an object with a planar surface for contact with the material. The device has a material mount for mounting a quantity of the material such that the quantity of material presents an exposed flat face, an object mount for securely holding the object such that the planar surface is in flat contact with the exposed flat surface, the material mount and the object mount being movable relative to each other, a contact force applicator for applying a known force urging the exposed flat face and the planar surface into contact and, separation mechanism for applying a variable force to the material mount and the object mount to slide the flat face and the planar surface relative to each other such that the variable force can be increased until the flat face and the planar surface slide relative to each other. | 03-25-2010 |
| 20100078635 | SEMICONDUCTOR DEVICE - As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path. Further, an interposer for facilitating the connection with the processor LSI is connected to the input terminal of the memory LSI to be stacked thereby increasing the degree of freedom in selecting memories. | 04-01-2010 |
| 20100078636 | SEMICONDUCTOR DEVICE WITH BACKSIDE TAMPER PROTECTION - A tamper-resistant semiconductor device ( | 04-01-2010 |
| 20100084656 | PARTICLE EMISSION ANALYSIS FOR SEMICONDUCTOR FABRICATION STEPS - A structure and a method for operating the same. The method includes providing a detecting structure which includes N detectors. N is a positive integer. A fabrication step is simultaneously performed on the detecting structure and M product structures in a fabrication tool resulting in a particle-emitting layer on the detecting structure. The detecting structure is different than the M product structures. The M product structures are identical. M is a positive integer. An impact of emitting particles from the particle-emitting layer on the detecting structure is analyzed after said performing is performed. | 04-08-2010 |
| 20100084657 | THIN FILM TRANSISTOR ARRAY SUBSTRATE - A thin film transistor array substrate includes a substrate having a display area and a peripheral area, a plurality of pixel units, a plurality of signal lines, and a testing circuit. The signal lines are electrically connected with the pixel units disposed in the display area. The testing circuit disposed in the peripheral area is electrically connected with terminals, located in the peripheral area, of a portion of the signal lines. The testing circuit includes a common gate line having a plurality of notches formed on an edge thereof, a plurality of channel layers, source electrodes, and drain electrodes. The source electrodes and the drain electrodes are disposed correspondingly on the channel layers disposed above the common gate line. Each drain electrode extends from the top of the common gate line to the top of one notch and extends to the terminal of one signal line for electrically connecting thereto. | 04-08-2010 |
| 20100096629 | MULTI-CHIP MODULE FOR AUTOMATIC FAILURE ANALYSIS - The invention provides a multi-chip module. In one embodiment, the multi-chip module comprises a serial flash die and a primary die, and the primary die comprises a built-in self-test controller and a serial flash controller. The built-in self-test controller generates a write command to write first data to a memory location of the serial flash die, generates a read command to read second data from the memory location of the serial flash die, and compares the second data with the first data to determine whether the memory location is defective for generating failed address information about the serial flash die. The serial flash controller accesses the serial flash die according to the write command and the read command. | 04-22-2010 |
| 20100102316 | TEST STRUCTURE FOR CHARGED PARTICLE BEAM INSPECTION AND METHOD FOR FABRICATING THE SAME - A test structure and a method for fabricating the same are disclosed. The test structure includes a plurality of sampling lines over a substrate located between a plurality of a first grounding lines and a plurality of a second grounding lines. The sampling lines are selectively electrically coupled to the first grounding line or the second grounding line and include at least one programmed defect. A double-patterning fabricating approach is utilized to produce such test structure which may be applied to a charged particle beam such as an electron-beam defect inspection system. | 04-29-2010 |
| 20100102317 | Semiconductor wafer, semiconductor device, semiconductor module and electronic apparatus including guard ring patterns and process monitoring pattern - A semiconductor wafer includes semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other. | 04-29-2010 |
| 20100102318 | Semiconductor device, semiconductor module, and electronic apparatus including process monitoring pattern overlapping with I/O pad - A semiconductor device includes a process monitoring pattern overlapping with an input/output (I/O) pad. The semiconductor device may include a semiconductor substrate having a cell array region and a peripheral circuit array region, and a plurality of process monitoring patterns disposed in the peripheral circuit array region. The semiconductor device may further include a plurality of input/output (I/O) pads, where each I/O pad is disposed on a corresponding process monitoring pattern. | 04-29-2010 |
| 20100109005 | SEMICONDUCTOR DEVICE COMPRISING A DISTRIBUTED INTERCONNECTED SENSOR STRUCTURE FOR DIE INTERNAL MONITORING PURPOSES - In a semiconductor device, electrical measurement data may be obtained with enhanced spatial resolution, for instance from within the entire die region, by providing a distributed sensor structure, each of which may be individually accessed by an appropriate interconnect structure, while nevertheless maintaining the required number of terminals and test signals at a low level. | 05-06-2010 |
| 20100109006 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor device layer, a multilayered wiring section formed of a plurality of wiring layers and a plurality of interlayer insulating films on one surface of the semiconductor device layer, an external connection electrode formed on one of the plurality of wiring layers, and an opening formed in a concave shape extending from the semiconductor device layer to the multilayered wiring section so as to expose a surface of the external connection electrode; the opening has a larger opening diameter at an end farther from the external connection electrode than at the other end closer to the external connection electrode. | 05-06-2010 |
| 20100117080 | SEMICONDUCTOR TEST PAD STRUCTURES - A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer. | 05-13-2010 |
| 20100117081 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor integrated circuit device for driving an LCD, COG chip packaging is performed. To achieve this, an elongate and relatively thick gold bump electrode is formed over an aluminum-based pad having a relatively small area. In a wafer probe test performed after formation of the gold bump electrode, a cantilever type probe needle having gold as a main component and having an almost perpendicularly bent tip portion is used. The diameter of this probe needle in the vicinity of its tip is usually almost the same as the width of the gold bump electrode. This makes it difficult to perform the wafer probe test stably. To counteract this, a plurality of bump electrode rows for outputting a display device drive signal are formed such that the width of inner bump electrodes is made greater than the width of outer bump electrodes. | 05-13-2010 |
| 20100117082 | SEMICONDUCTOR DEVICE CAPABLE OF COMPENSATING FOR ELECTRICAL CHARACTERISTIC VARIATION OF TRANSISTOR ARRAY - A semiconductor device capable of compensating for an electrical characteristic variation of a transistor array is provided. The semiconductor device includes an N-well region and a transistor array spaced from the N-well region and including a plurality of transistors. A characteristic of each of the transistors is adjusted to enable the transistors to have a same electrical characteristic. | 05-13-2010 |
| 20100117083 | SEMICONDUCTOR DEVICE - Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex. | 05-13-2010 |
| 20100117084 | METHOD FOR SORTING AND ACQUIRING SEMICONDUCTOR ELEMENT, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map. | 05-13-2010 |
| 20100123133 | SPIN-POLARISED CHARGE-CARRIER DEVICE - A device comprising a channel for charge carriers comprising non-ferromagnetic semiconducting in which charge carriers exhibit spin-orbit coupling, a region of semiconducting material of opposite conductivity type to the channel and configured so as to form a junction with the channel for injecting spin-polarised charge carriers into an end of the channel and at least one lead connected to the channel for measuring a transverse voltage across the channel. | 05-20-2010 |
| 20100123134 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SOQ (SILICON ON QUARTZ) SUBSTRATE USED IN THE METHOD - A method of producing a semiconductor device includes the steps of preparing an SOQ (Silicon On Quartz) substrate in which a semiconductor layer is formed on a quartz substrate; forming a plurality of semiconductor device forming regions in the SOQ substrate; forming a crack inspection pattern in the SOQ substrate; inspecting the crack inspection pattern to detect a crack in the crack inspection pattern in a first inspection step; and inspecting the semiconductor device forming regions to detect a crack in the semiconductor device forming regions in a second inspection step when the crack is detected in the crack inspection pattern in the first inspection step. | 05-20-2010 |
| 20100123135 | PAD STRUCTURE AND METHOD OF TESTING - An interconnect structure includes: a plurality of dielectric layers having aligned process control monitor (PCM) pads, and a conductive structure above a topmost one of the PCM pads. The conductive structure electrically connects the topmost PCM pad to a device under test above a level of the topmost PCM pad. The conductive structure is sized and shaped so as to leave a majority portion of the topmost PCM pad exposed for access by a test probe. | 05-20-2010 |
| 20100127258 | LCD PANEL HAVING SHARED SHORTING BARS FOR ARRAY INSPECTION AND PANEL INSPECTION - An LCD panel includes a panel area, a plurality of shorting bars, a plurality of panel test pads, and a plurality of array test pads. The panel area includes a plurality of scan lines and a plurality of data lines. The plurality of shorting bars is located inside the panel area. The plurality of scan lines and the plurality of data lines are electrically connected to corresponding shorting bars of the plurality of shorting bars through a switch circuit. The plurality of panel test pads is located inside the panel area. The plurality of panel test pads is electrically connected to the plurality of shorting bars respectively. The plurality of array test pads is located outside the panel area. The plurality of array test pads is electrically connected to corresponding panel test pads of the plurality of panel test pads. | 05-27-2010 |
| 20100133534 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interposer having a first side and a second side with the first side having a device contact and an interconnect contact and with the second side having a test pad; mounting an integrated circuit over the device contact; and applying an underfill between the integrated circuit and the interposer. | 06-03-2010 |
| 20100133535 | SEMICONDUCTOR DEVICE WITH REDUCED PAD PITCH - A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided. | 06-03-2010 |
| 20100140615 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, a pixel array, and peripheral circuit is provided. The substrate has a display region and a peripheral region. The pixel array is disposed on the display region of the substrate, wherein the pixel array includes signal lines and pixels, each of the pixels is electrically connected to the signal lines respectively and extends from the display region to the peripheral region. The peripheral circuit is disposed on the peripheral region and includes a testing circuit electrically connected to the signal lines. Additionally, the testing circuit includes shorting bars and connecting conductors, wherein each of the signal lines is electrically connected to one of the shorting bars through one of the connecting connectors respectively, and at least two of the signal lines connected to the same shorting bar are electrically connected to each other through one of the connecting conductors. | 06-10-2010 |
| 20100140616 | Electronic device and method for manufacturing the same - Disclosed herewith is an electronic device capable of preventing the surfaces of the analyzing terminals from such external factors as oxidation, etc. so as to improve the accuracy of the analysis of the electronic device. The electronic device has plural signal lines and is to be mounted on a wiring substrate. The electronic device also includes plural lead terminals connected to the signal lines electrically and to be mounted on the wiring substrate, as well as analyzing terminals connected electrically to the signal lines and to be connected to an analyzing device upon analyzing the electronic device respectively and a protective member with insulating performance, which covers at least one of the analyzing terminals | 06-10-2010 |
| 20100140617 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes the steps of: forming a transistor on a surface side of a silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate being formed by laminating a substrate, an insulating layer, and the silicon layer; forming a first insulating film covering the transistor and a wiring section including a part electrically connected to the transistor on the silicon-on-insulator substrate; measuring a threshold voltage of the transistor through the wiring section; forming a supporting substrate on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; removing at least a part of the substrate and the insulating layer on a back side of the silicon-on-insulator substrate; and adjusting the threshold voltage of the transistor on a basis of the measured threshold voltage. | 06-10-2010 |
| 20100148172 | Semiconductor device - A semiconductor device includes: a semiconductor chip; a plurality of electrode pads on the semiconductor chip; a wiring board fixed to the semiconductor chip; a plurality of connection pads on the wiring board; a plurality of bonding pads aligned along two sides of the wiring board; and a plurality of leads on the wiring board. The plurality of electrode pads is in a center region of the semiconductor chip. The plurality of second connection pads faces the plurality of electrode pads. The plurality of leads connects the plurality of connection pads to the plurality of bonding pads. | 06-17-2010 |
| 20100148173 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device includes: a semiconductor element ( | 06-17-2010 |
| 20100155724 | Flat panel display including electrostatic protection circuit - A flat panel display is disclosed. The flat panel display includes a display panel having a display area on which a plurality of pixels are formed, an inspection pad formed in a non-display area outside the display area of the display panel, an inspection switch formed in the non-display area, and an electrostatic protection circuit including a plurality of dummy thin film transistors (TFTs) whose gate electrodes are commonly connected to a signal line connecting the inspection pad to the inspection switch. The inspection pad contacts an external inspection device. The inspection switch applies an inspection signal received from the inspection pad to the pixels. | 06-24-2010 |
| 20100155725 | INSERT MODULE FOR A TEST HANDLER - An insert module for a test handler includes an insert body and a support frame. The insert body has a receiving space for receiving a semiconductor device. The semiconductor device having connection pads protruding externally from a surface of the semiconductor device. The support frame is formed in an inner side portion of the insert body defining the receiving space to provide a seating surface for contacting and supporting the semiconductor device. The support frame includes a fixing frame and a guide pattern. The fixing frame is inserted into and fixed with the insert body and defines an opening that exposes the semiconductor device. The guide pattern extends from the fixing frame to the inside of the opening to contact the semiconductor device and guide the connection pads. | 06-24-2010 |
| 20100155726 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes an I/O buffer provided in a semiconductor chip, single-layer pads, and multilayer pads. The single-layer pads are formed above the I/O buffer. The multilayer pads are formed above the I/O buffer separately from the single-layer pads. The single-layer pads are pads dedicated to bonding, and the multilayer pads are pads on which both probing and bonding are performed. | 06-24-2010 |
| 20100155727 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 06-24-2010 |
| 20100163869 | BONDING INSPECTION STRUCTURE - A bonding inspection structure is provided. The bonding inspection structure includes at least a elastic bump located on a substrate. At least an opening is formed in the top portion of the elastic bump. An inspection area of the top portion of the elastic bump is larger than an area of the opening. | 07-01-2010 |
| 20100163870 | Structure and Method for Testing MEMS Devices - A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a plane, the at least one structure being clamped at at least one side. The method further includes exerting a force, such as a mechanical force, on the at least one structure. The force may have a predetermined amplitude and a component perpendicular to the substrate. Still further, the method includes determining the deflection of the at least one structure perpendicular to the plane of the substrate, and correlating the deflection of the at least one structure to the presence of a sacrificial layer between the substrate and the structure. | 07-01-2010 |
| 20100163871 | METHOD FOR INDEXING DIES COMPRISING INTEGRATED CIRCUITS - An embodiment of a method for indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers is disclosed. Each die is obtained in a respective position of the wafer; the plurality of dies is obtained by means of a manufacturing process performed in at least one manufacturing stage using at least one lithographic mask for treating a surface of the material wafer trough an exposition to a proper radiation. Said at least one manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die. Said forming the external index may comprise forming in a set of material layers of the die a first reference structure adapted to define a mapping of the superficial portions of the wafer; said first reference structure may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line. The method may further comprise interrupting the control line in a position based on the position of the superficial portion corresponding to the subset of the plurality of dies including the die. | 07-01-2010 |
| 20100176396 | PROBE, PROBE CARD, AND METHOD OF PRODUCTION OF PROBE - A probe comprises: a beam part having a Si layer composed of monocrystalline silicon; an interconnect part provided along the longitudinal direction of the beam part on one main surface of the beam part; a contact part provided at a front end part of the interconnect part and to be electrically connected to input/output terminals of an IC device; and a base part supporting a plurality of beam parts all together in a cantilever fashion, and a longitudinal direction of the beam part substantially matches with a crystal orientation <100> of monocrystalline silicon of the Si layer. | 07-15-2010 |
| 20100181567 | Semiconductor device including bonding pads and semiconductor package including the semiconductor device - Provided is a semiconductor device that may prevent a test pad planned not to be wire bonded from being wire bonded. The semiconductor device may include a bonding pad planned to be wire bonded and a test pad planned not to be wire bonded, and a passivation layer including a first opening portion exposing part of the bonding pad and a second opening portion exposing part of the test pad, wherein the diameter of the first opening portion is greater than the diameter of a tip of a bonding wire, and the diameter of the second opening portion is less than the diameter of the tip of the bonding wire. | 07-22-2010 |
| 20100181568 | INTEGRATED CIRCUITS ON A WAFER AND METHODS FOR MANUFACTURING INTEGRATED CIRCUITS - Integrated circuits ( | 07-22-2010 |
| 20100187525 | IMPLEMENTING TAMPER EVIDENT AND RESISTANT DETECTION THROUGH MODULATION OF CAPACITANCE - A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including the circuitry to be protected. A change in the capacitor value results responsive to the semiconductor chip being thinned, which is detected and a tamper-detected signal is generated. | 07-29-2010 |
| 20100187526 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device semiconductor device allowing for use of a test circuit that withstands only low voltages and has a small circuit area. A high-voltage operational circuit, which is operated at a high voltage, is connected to first and second pads. A multiplexer used to test the high-voltage operational circuit is connected to a third pad in addition to the first and second pads. Fuses are arranged on wires connecting the first and second pads to the multiplexer. An inspection board connects the third pad to ground after testing the high-voltage operational circuit, provides a breakage signal to the multiplexer, and applies voltage to the first or second pad. The multiplexer, which receives the breakage signal, connects the first or second pad with the third pad so that current flows therebetween. This breaks the corresponding fuse and insulates the multiplexer from the high-voltage operational circuit. | 07-29-2010 |
| 20100187527 | TAMPER-RESISTANT SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THEREOF - The invention relates to a tamper-resistant semiconductor device comprising a substrate ( | 07-29-2010 |
| 20100187528 | GUARD RING EXTENSION TO PREVENT RELIABILITY FAILURES - An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation. | 07-29-2010 |
| 20100193786 | Structures for measuring misalignment of patterns - A structure for measuring misalignment of patterns may include a first wiring and a second wiring. The first wiring may include a first lower pattern and a first upper pattern. The first upper pattern may extend in a y-direction, and a first end portion of the first upper pattern that is relatively further toward (proximal to) a negative y-direction may contact the first lower pattern. The second wiring may include a second lower pattern and a second upper pattern. The second upper pattern may extend in the y-direction, a second end portion of the second upper pattern that is relatively further toward (proximal to) a positive y-direction may contact the second lower pattern. The second wiring may be spaced apart from the first wiring along the negative y-direction. | 08-05-2010 |
| 20100193787 | Semiconductor device - A semiconductor device, includes a package substrate having a first surface and a second surface opposite to the first surface, and a semiconductor element installed in the first surface of the package substrate. The package substrate includes a plurality of first land pads disposed in the first surface, second land pads disposed in the second surface and a second testing-dedicated pad disposed in the second surface. The semiconductor element is electrically coupled to the first land pads, an inter-pad distance for the second land pads is larger than an inter-pad distance for the first land pads, the first land pad contains a first testing-dedicated pad electrically coupled to the semiconductor element, the first testing-dedicated pad and the second testing-dedicated pad each include a dedicated terminal, which is essential for applying a specified electrical signal from an LSI tester, when an LSI testing is conducted for a semiconductor wafer and the first testing-dedicated pad is electrically coupled to only the second testing-dedicated pad through a wiring. | 08-05-2010 |
| 20100200853 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes: (a) performing an inspection using an evaluation element formed on a scribe line of a semiconductor wafer; (b) marking a character on the semiconductor wafer, the character representing information based on a result obtained in step (a); and (c) performing a step subsequent to step (b) while using the information represented by the character marked in step (b). | 08-12-2010 |
| 20100224874 | TCP-type semiconductor device - A TCP-type semiconductor device has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connected to the semiconductor chip. Each of the plurality of leads has a test pad section at a position other than both ends of the each lead. | 09-09-2010 |
| 20100224875 | SUBSTRATE WITH TEST CIRCUIT - The present invention relates to a substrate with a substrate test circuit. In an embodiment, by making the length of the wiring from a first data-line-test input terminal to a first panel equal to that of the wiring from a second data-line-test input terminal to the first panel, the input resistances between two test input terminals of a first data-line-test line and the first panel are identical, and thus when a data line of the first panel is detected, the voltage drops of test signals inputted from the two test input terminals are the same, and the test signals actually loaded to the first panel are the same and the detecting abilities are identical. | 09-09-2010 |
| 20100230672 | PRODUCTION OF INTEGRATED CIRCUITS COMPRISING DIFFERENT COMPONENTS - It is described a method for producing an integrated circuit element comprising a first electric component of a first type and a second electric component of a second type, wherein the two components require different measurement conditions for testing the components as to be defective or as to be defect free. The production method comprises the steps of (a) forming the first and the second component on a substrate, (b) providing a conductor path on the substrate in order to contact the first and the second component, the conductor path comprising a galvanic gap, wherein the galvanic gap provides the possibility to individually connect the first component with a measurement device, (c) accomplishing a test of the first component with the measurement device and (d) in case the test shows a defect free first component, closing the galvanic gap with a conductive connection, and in case the test shows a defective first component, identifying the corresponding integrated circuit element as to be defective. Furthermore, there is described a method for producing an integrated circuit comprising a plurality of circuit elements, a circuit element and an integrated circuit. | 09-16-2010 |
| 20100237345 | WAFER AND MANUFACTURING METHOD OF ELECTRONIC COMPONENT - The present invention relates to a wafer formed with an evaluation element and capable of improving productivity and a manufacturing method of an electronic component using the same. In a wafer according to the present invention, a plurality of elements connected to electrode films through lead-out conductive films are arranged and a chip area is defined for cutting out the plurality of elements in a given number. In the wafer, at least one evaluation element is formed in an area outside the chip area. The lead-out conductive films extend to the outside area and are connected to the evaluation elements. With this wafer, since the lead-out conductor is shared between the element and the evaluation element, the electrode film connected therewith can be shared, too. Accordingly, evaluation can be performed by using the evaluation element without the need of providing the wafer with a lead-out conductor and an electrode film exclusively for the evaluation element, so that the chip area to be cut out from the wafer can be made larger than before. | 09-23-2010 |
| 20100244023 | Programmable resistance memory - A rewritable nonvolatile memory includes a test cell that is dedicated to testing the storage characteristics of other, similar, storage cells formed within the same integrated circuit memory. The test cell may be share the same structure and composition as storage cells and may be positioned proximate storage cells. | 09-30-2010 |
| 20100244024 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interposer having device contacts, interconnect contacts, and test pads including the interconnect contacts along an interconnect perimeter region of the interposer, the device contacts at a device perimeter region of the interposer with the device perimeter region within the interior of the interconnect perimeter region, and the test pads at a test perimeter region of the interposer with the test perimeter region encompassing the device perimeter region; and mounting an integrated circuit over the device contacts. | 09-30-2010 |
| 20100244025 | ACTIVE DEVICE ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL - An active device array substrate, having at least a substrate, a first metal layer, an insulator layer, a second metal layer, a plurality of pixel electrodes and a plurality of active devices, is provided. The substrate has a display area and a narrow frame area. The first metal layer disposed on the substrate includes a plurality of first gate lines arranged laterally. The insulator layer is disposed on the first metal layer. The second metal layer disposed above an insulator layer includes a plurality of data lines and second gate lines arranged vertically. The first gate lines and the data lines divide the display area into a plurality of pixel areas. The second gate line disposed between the pixel areas is electrically connected to the first gate line. Each pixel electrode is electrically connected to the data line and the first gate line via each active array device. | 09-30-2010 |
| 20100244026 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate is provided. The active device array substrate includes an active matrix device, first bonding pads electrically connected to the active matrix device, second bonding pads electrically insulated from the first bonding pads, test bonding pads disposed between the first and the second bonding pads and separated from the second bonding pads, switch devices disposed between the test bonding pads and the first bonding pads and electrically connected to the test bonding pads, a test signal pad, a switch device control pad, and at least one driving chip electrically connected to the first bonding pads, the second bonding pads, and the test bonding pads. Each test bonding pad is corresponding to one of the second bonding pads. Both the test signal pad for inputting/outputting a test signal and the switch device control pad for turning on/off the switch devices are electrically connected to the switch devices. | 09-30-2010 |
| 20100244027 | Semiconductor device and method of controlling the same - A semiconductor device includes a capacitor element that stores charge to perform as a memory that stores information. The capacitor may include, but is not limited to, an insulating layer, a first electrode, and a second electrode. The insulating layer includes metal oxide. The insulating layer has a high dielectric constant. The first electrode contacts with a first surface of the insulating layer. The first electrode is made of a first conductive material including at least one of precious metals and compounds thereof. The second electrode contacts with a second surface of the insulating layer. The second electrode is made of a second conductive material including at least one of metals and compounds thereof. The metals are different from the precious metals. The second conductive material is lower in work function than the first conductive material. The first electrode is lower in potential than the second electrode. | 09-30-2010 |
| 20100244028 | TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein. | 09-30-2010 |
| 20100252828 | SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS - A test structure or a circuit element acting temporarily as a test structure may be provided within the die region of sophisticated semiconductor devices, while probe pads may be located in the frame in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads may be established by a conductive path including a buried portion, which extends from the die region into the frame below a die seal, thereby maintaining the electrical and mechanical characteristics of the die seal. Hence, enhanced availability of electrical measurement data and superior authenticity of the data may be accomplished, wherein the measurement data may be obtained during the production process. | 10-07-2010 |
| 20100252829 | SEMICONDUCTOR DEVICE, CIRCUIT SUBSTRATE, ELECTRO-OPTIC DEVICE AND ELECTRONIC APPARATUS - A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection. | 10-07-2010 |
| 20100252830 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first external connection terminal at a first row is disposed to position at upside of a first I/O cell, and a second external connection terminal at a second row is formed at upside of a boundary portion between two adjacent first I/O cells. Here, the first external connection terminal and the second external connection terminal are disposed to be separated for a predetermined distance so as not to have an overlapped portion with each other, and formed in an identical layer. According to the constitution, it is possible to prevent disadvantages such as characteristic deterioration of a semiconductor integrated circuit and accuracy deterioration of an electrical inspection. | 10-07-2010 |
| 20100258798 | INTEGRATED CIRCUIT HAVING A FILLER STANDARD CELL - An integrated circuit includes a functional block having a plurality of standard cells. The plurality of standard cells includes a plurality of functional standard cells and a filler standard cell. Each functional standard cell of the plurality of functional standard cells has a rectangular boundary. The filler standard cell has a rectangular boundary adjacent to at least one of the functional standard cells. The filler standard cell is selectable between a first state and a second state. The filler standard cell is non-functional in the first state. The filler standard cell has functional test structures coupled to a first metal layer in the second state. This allows for test structures helpful in analyzing functionality of circuit features such as transistors without requiring additional space on the integrated circuit. | 10-14-2010 |
| 20100264413 | Replacement of Scribeline Padframe with Saw-Friendly Design - An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure. | 10-21-2010 |
| 20100264414 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING SAME - In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. An invention of the present application is to remove the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad. | 10-21-2010 |
| 20100276690 | Silicon Wafer Having Testing Pad(s) and Method for Testing The Same - The present invention relates to a silicon wafer having testing pad(s) and a method for testing the same. The silicon wafer includes a silicon substrate, an insulation layer, at least one testing pad and a dielectric layer. The testing pad includes a first metal layer, a second metal layer and at least one first interconnection metal. The first metal layer is disposed on the insulation layer, and has a first area and a second area. The first area and the second area are electrically insulated with each other. The second metal layer is disposed above the first metal layer. The first interconnection metal connects the second area of the first metal layer and the second metal layer. Therefore, when a through hole and a seed layer are formed in the following processes, the through hole is estimated whether it is qualified by probing the testing pad to know whether the seed layer connects the second area of the first metal layer of the testing pad, thus the yield rate of the following processes is increased. | 11-04-2010 |
| 20100283051 | MONITOR CELL AND MONITOR CELL PLACEMENT METHOD - The present invention relates to a monitor cell ( | 11-11-2010 |
| 20100283052 | Metrology Systems and Methods for Lithography Processes - Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask. | 11-11-2010 |
| 20100289021 | SCRIBE LINE STRUCTURE AND METHOD FOR DICING A WAFER - A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction. | 11-18-2010 |
| 20100295043 | SEMICONDUCTOR DEVICE - A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad. | 11-25-2010 |
| 20100295044 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film. | 11-25-2010 |
| 20100295045 | Tape carrier package, individual tape carrier package product, and method of manufacturing the same - A tape carrier package includes: a tape base; and interconnections formed on the tape base and extending to intersect a cutting line. At least a slit is formed along each of the interconnections, to intersect the cutting line and to divide the interconnection into a plurality of interconnection elements. | 11-25-2010 |
| 20100301331 | BODY CONTACT STRUCTURE FOR IN-LINE VOLTAGE CONTRAST DETECTION OF PFET SILICIDE ENCROACHMENT - Test structures for in-line voltage contrast detection of PFET silicide encroachment defects are disclosed. Embodiments of the present invention provide for improved PFET test structures for detecting encroachment defects using VC imaging techniques. The test structures use body contacts, and the PFET components (source, drain, body, and gate) are either grounded, or floating, depending on the configuration. Some embodiments of the present invention also enable the use of positive mode conditions with PFET test structures, which provides for improved contrast in the VC images, improving the effectiveness of the defect detection achieved with VC imaging. | 12-02-2010 |
| 20100301332 | Detecting a Fault State of a Semiconductor Arrangement - Disclosed is a method for detecting a mechanical fault state of a semiconductor arrangement, using a temperature profile. | 12-02-2010 |
| 20100301333 | SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING AN ELECTRICAL CHARACTERISTIC OF A SEMICONDUCTOR DEVICE - A semiconductor device is provided with an electrode pad; and a lower layer arranged under the electrode pad. The electrode pad includes a slit section, penetrating a whole thickness of the electrode pad from a higher surface to a lower surface in contact with the lower layer; a contact start region, arranged in the higher surface, on which a probe makes a contact; and an inspection region, arranged in the higher surface, on which the probe makes an inspection upon the semiconductor. The slit section includes a first group of aperture open to the inspection region; a second group of aperture open to the contact start region smaller than the first group of aperture; and a vacant region able to store a part of shavings produced by the probe while shifting from the contact start region to the inspection region, by grinding the higher surface of the electrode pad. | 12-02-2010 |
| 20100301334 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF - In a semiconductor integrated circuit device, testing pads ( | 12-02-2010 |
| 20100308328 | SEMICONDUCTOR DEVICE - A semiconductor device has a floating gate structure in which charge storage layers are stacked on a SiO | 12-09-2010 |
| 20100308329 | LITHOGRAPHY ROBUSTNESS MONITOR - The present invention relates to a method and device for monitoring a lithographic process of an integrated circuit. In a first step a design for an integrated circuit is provided. The integrated circuit comprises at least an integrated circuit transistor pair having a gate of a first transistor connected to a gate of a second transistor. The gate of the second transistor is designed such that it has a predetermined overlap with respect to a source and a drain of the second transistor. A detection circuit is connected to the at least an integrated circuit transistor pair for detecting if in operation functionality of the second transistor of each of the at least an integrated circuit transistor pair is one of a transistor and a short circuit. The integrated circuit is then manufactured in dependence upon the desogn. After manufacturing, the detection circuit is used to determine the functionality of the second transistor of each of the at least an integrated circuit transistor pair. | 12-09-2010 |
| 20100314619 | Test Structures and Methods for Semiconductor Devices - Test structures for semiconductor devices, methods of forming test structures, semiconductor devices, methods of manufacturing thereof, and testing methods for semiconductor devices are disclosed. In one embodiment, a test structure for a semiconductor device includes at least one first contact pad disposed in a first material layer in a scribe line region of the semiconductor device. The at least one first contact pad has a first width. The test structure also includes at least one second contact pad disposed in a second material layer proximate the at least one first contact pad in the first material layer. The at least one second contact pad has a second width that is greater than the first width. | 12-16-2010 |
| 20100314620 | SEMICONDUCTOR DEVICE - To suppress or prevent the generation of a crack in an insulating film below an external terminal which could be caused by an external force added to the external terminal of a semiconductor device. A top wiring layer MH of wiring layers formed on a main surface of a silicon substrate has a pad comprising a conductor pattern containing aluminum. On an undersurface of the pad, there are arranged a barrier conductor film formed by laminating, from below, a first barrier conductor film and a second barrier conductor film. Of a fifth wiring layer which is one layer lower than the top wiring layer, in an area overlapping with a probe contact area of the pad in a plane, the conductor pattern is not arranged. Further, the first and second barrier conductor films are the conductor films including titanium and titanium nitride as principal components, respectively. Also, the first barrier conductor film is thicker than the second barrier conductor film. | 12-16-2010 |
| 20100320460 | SYSTEM FOR SEPARATION OF AN ELECTRICALLY CONDUCTIVE CONNECTION - An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section. | 12-23-2010 |
| 20100320461 | INTEGRATION OF SENSE FET INTO DISCRETE POWER MOSFET - A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical isolation structure that surrounds the main FET is configured to electrically isolate source and body regions of the main FET from source and body regions of the sense FET. A sense FET source pad is located at an edge of the main FET and spaced apart from the transistor portion of the sense FET. The sense FET source pad is connected to the transistor portion of the sense FET by a sense FET probe metal. The isolation structure is configured such that the transistor portion of the sense FET and the sense FET source pad are located outside an active area of the main FET. | 12-23-2010 |
| 20100327279 | MICRO VACUUM GAUGE - A micro vacuum gauge includes a substrate, a floating structure that is held above the substrate by a supporting structure extending from the substrate in a state where the floating structure is thermally isolated from the substrate, a heat generator that is arranged in the floating structure to generate heat, and a temperature sensor that is arranged in the floating structure to measure a difference in temperature between the substrate and the floating structure. A second member having a lower emissivity than a first member surrounding the heat generator and the temperature sensor is formed at least on a surface of the floating structure by being joined to the first member. | 12-30-2010 |
| 20110006303 | SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS - Provided is a semiconductor apparatus which may check a state of connection of a penetrating electrode in a semiconductor substrate with ease. A semiconductor apparatus manufacturing method includes: forming in a semiconductor substrate at least three kinds of the through-holes each having a large area, a middle area, and a small area of openings; forming a conductive layer on an inner surface of the at least three kinds of the through-holes having different areas of the openings to form the penetrating electrodes; and measuring resistance values of the penetrating electrode including the through-hole having the large area of the opening and the penetrating electrode including the through-hole having the small area of the opening among the three kinds of the penetrating electrodes to determine states of connection of the penetrating electrodes. | 01-13-2011 |
| 20110012108 | Semiconductor device having process failure detection circuit and semiconductor device production method - A semiconductor device includes a cell array and a plurality of process failure detection circuits each having a layout pattern substantially identical to that of a cell of the cell array in a dummy region arranged around the cell array. Each of the process failure detection circuits includes a dummy pattern that equalizes a degree of density/sparsity of a peripheral part of the cell array with that of a central part of the cell array. The process failure detection circuits include a process failure detection circuit having a layout pattern formed with a stricter pattern margin in at least one manufacturing process, compared with the layout pattern of the cell of the cell array. | 01-20-2011 |
| 20110024743 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line. | 02-03-2011 |
| 20110024744 | CONNECTION PAD STRUCTURE FOR AN ELECTRONIC COMPONENT - The invention relates to electronic components on thinned substrates, for example image sensors. Preferably, connection pads are connected through the thinned substrate to underlying layers and notably to a test pad by way of openings through which the metal of the pad passes. The openings are elongate openings extending along one edge of the pad of rectangular shape and a circular area of at least 50% (and preferably 65 to 75%) of the area of the pad contains no opening for connection with the underlying layers. This circular area is intended for bonding an external connection wire. The connection pads are testable from the back side by test probes and the front side may be tested (before bonding and thinning) by test probes with the same geometric configuration. | 02-03-2011 |
| 20110024745 | System With Semiconductor Components Having Encapsulated Through Wire Interconnects (TWI) - A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate. | 02-03-2011 |
| 20110024746 | Semiconductor Device with Test Pads and Pad Connection Unit - A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode. | 02-03-2011 |
| 20110037069 | METHOD AND APPARATUS FOR VISUALLY DETERMINING ETCH DEPTH - Etch depth of a material in a semiconductor wafer may be determined by forming a production region and a test region of the wafer, the test region having a test pattern for determining etch depth on a the wafer. The semiconductor wafer is comprised of a base layer, an intermediate layer above and visually distinguishable from the base layer, and a mask of photoresist material formed atop the intermediate layer. The mask of photoresist material has an areal photoresist coverage that varies across a horizontal axis. When the wafer is etched, a visible boundary can be seen between a region where the intermediate layer has been entirely etched away, and a region where at least some of the intermediate layer remains. The horizontal position of this visible boundary corresponds to the vertical etch depth in the production region., after etching of the semiconductor wafer. | 02-17-2011 |
| 20110042671 | Semiconductor Device Test Structures and Methods - Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test structure includes a temperature adjuster proximate at least the conductive feature, and at least one feedback device coupled to the temperature adjuster and at least the conductive feature. | 02-24-2011 |
| 20110049513 | SEMICONDUCTOR DEVICE HAVING MULTILAYER WIRING STRUCTURE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device having a multilayer wiring structure includes a function block and a test pad. The function block contains a DFT circuit. The test pad is formed in an intermediate wiring layer, and connected to the DFT circuit of the function block. A functional operation test of the function block is executed by using the test pad. | 03-03-2011 |
| 20110049514 | TCP TYPE SEMICONDUCTOR DEVICE - A TCP type semiconductor device includes a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connected with the semiconductor chip. Each of the plurality of leads has an external terminal portion exposed externally. The external terminal portion of the each lead includes: a first portion having a first thickness; and a second portion having a second thickness which is thinner than the first thickness. The first portion and the second portion are arranged to oppose to each other between adjacent two of the plurality of leads. | 03-03-2011 |
| 20110049515 | CHIP STRUCTURE WITH BUMPS AND TESTING PADS - A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening. | 03-03-2011 |
| 20110049516 | MULTI-PROJECT WAFER AND METHOD OF MAKING SAME - A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type. | 03-03-2011 |
| 20110062442 | Semiconductor Device Test Structures and Methods - Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer. | 03-17-2011 |
| 20110073858 | Test Structure for Determination of TSV Depth - A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel. | 03-31-2011 |
| 20110079779 | SHAPE CHARACTERIZATION WITH ELLIPTIC FOURIER DESCRIPTOR FOR CONTACT OR ANY CLOSED STRUCTURES ON THE CHIP - Shapes and orientations of contacts or other closed contours on an integrated circuit are characterized by calculating Elliptic Fourier descriptors. The descriptors are then used for generating design rules for the integrated circuit and for assessing process capability for the manufacturing of the integrated circuit. Monte Carlo simulation can be performed in conjunction with the elliptic Fourier descriptors. | 04-07-2011 |
| 20110095289 | Laminated chips package, semiconductor substrate and method of manufacturing the laminated chips package - In a laminated chip package, a plurality of semiconductor plates each having a semiconductor device and a wiring electrode connected to the semiconductor device are laminated. On a side surface for wiring of the laminated chip package, an end face of an inner electrode for examination formed inside the side surface for wiring in the semiconductor plate is formed. The laminated chip package further has an outer electrode for examination connecting the end faces of the inner electrodes for examination along a lamination direction of the semiconductor plates, only for two adjacent semiconductor plates among the semiconductor plates. | 04-28-2011 |
| 20110095290 | DISPLAY PANEL - A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line. | 04-28-2011 |
| 20110101347 | Interconnect Sensor for Detecting Delamination - An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination. | 05-05-2011 |
| 20110101348 | DEVICE FOR ANALYZING CHARGE AND ULTRAVIOLET (UV) LIGHT - Provided is a device for analyzing at least one of a generated amount of positive charges, a generated amount of negative charges, and a generated amount of ultraviolet (UV) light. The device includes a substrate on which at least one of a first device configured to detect a variation in threshold voltage relative to the generated amount of positive charges, a second device configured to detect a variation in threshold voltage relative to the generated amount of negative charges, and a third device configured to detect a variation in threshold voltage relative to the generated amount of UV light is formed. Each of the first through third devices includes a first isolation region disposed in the substrate which define first and third active regions each of a first conductivity type and second and fourth active regions each of a second conductivity type different from the first conductivity type, first impurity regions disposed in the first active region and spaced apart from each other and having the second conductivity type, a floating gate crossing over the first active region between the first impurity regions and extending over the second active region, a second impurity region disposed in the second active region and having the first conductivity type, and a conductive structure electrically connected to the second impurity region. | 05-05-2011 |
| 20110101349 | SEMICONDUCTOR PACKAGE, METHOD OF EVALUATING SAME, AND METHOD OF MANUFACTURING SAME - A semiconductor package includes a wiring board, a semiconductor device mounted on the wiring board, an electrically-conductive thermal interface material provided on the semiconductor device, a test electrode in contact with a first surface of the thermal interface material to be electrically connected to the thermal interface material, and an electrically-conductive heat spreader in contact with a second surface of the thermal interface material opposite to its first surface. | 05-05-2011 |
| 20110101350 | SEMICONDUCTOR-BASED SUB-MOUNTS FOR OPTOELECTRONIC DEVICES WITH CONDUCTIVE PATHS - The disclosure facilitates testing and binning of multiple LED chip or other optoelectronic chip packages fabricated on a single semiconductor wafer. The testing can take place prior to dicing. For example, in one aspect, metallization on the front-side of a semiconductor wafer electrically connects together cathode pads (or anode pads) of adjacent sub-mounts such that the cathode pads (or anode pads) in a given column of sub-mounts are electrically connected together. Likewise, metallization on the back-side of the wafer electrically connects together anode pads (or cathode pads) of adjacent sub-mounts such that the anode pads (or cathode pads) in a given row of sub-mounts are electrically connected together. Probe pads, which can be located one or both sides of the wafer, are electrically connected to respective ones of the rows or columns. | 05-05-2011 |
| 20110114949 | TEST CHIPLETS FOR DEVICES - A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a defect programmed into the cell to facilitate defect detection. | 05-19-2011 |
| 20110114950 | Integrated Circuit Wafer and Integrated Circuit Die - An integrated circuit wafer and integrated circuit dice are provided. The integrated circuit wafer includes a wafer substrate, a plurality of integrated circuits, a plurality of test-keys, an isolation film, and a plurality of ditches. The integrated circuits are disposed on the wafer substrate in matrix. The test-keys are respectively disposed between the adjacent integrated circuits. The isolation film covers at least one side of the integrated circuits on the wafer substrate. The ditches extend downwardly from the surface of the isolation film and are disposed between the integrated circuit and the adjacent test-key. The integrated circuit die includes a wafer substrate, an integrated circuit disposed on the wafer substrate, and an isolation film covering at least one side of the integrated circuit on the wafer substrate, wherein the side walls of the wafer substrate and the isolation film are respectively smooth walls. The side wall of the wafer substrate is substantially vertical. | 05-19-2011 |
| 20110114951 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - Disclosed is a semiconductor device fabrication method that comprises a fabrication process, wherein device structural patients are formed in a device formation area inside a chip formation area and wherein inspection patterns are formed in multiple inspection areas inside the aforementioned chip formation area, on the film-side of a semiconductor wafer that has a film for pattern formation, and an inspection process. The aforementioned inspection patterns have a repeating pattern with identical lines and identical spaces formed in a first inspection area among the aforementioned multiple inspection areas, and a uniform pattern without spaces formed in a second inspection area among the multiple inspection areas. The aforementioned inspection process has at least a pattern inspection process that comprises a first inspection, which uses an optical measurement method capable of measuring three-dimensional pattern shapes to measure the parameters of the repeating pattern in the aforementioned first inspection area in the direction of repetition in which the lines and spaces are repeated, and a second inspection, which uses an optical measurement method capable of measuring film thickness to measure the thickness of the uniform pattern in the aforementioned second inspection area. | 05-19-2011 |
| 20110121292 | CALIBRATION OF TEMPERATURE SENSITIVE CIRCUITS WITH HEATER ELEMENTS - One or more heating elements are disposed on a semiconductor substrate proximate a temperature sensitive circuit disposed on the substrate (e.g., bandgap circuit, oscillator). The heater element(s) can be controlled to heat the substrate and elevate the temperature of the circuit to one or more temperature points. One or more temperature measurements can be made at each of the one or more temperature points for calibrating one or more reference values of the circuit (e.g., bandgap voltage). | 05-26-2011 |
| 20110121293 | Apparatus and method for predetermined component placement to a target platform - The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly. | 05-26-2011 |
| 20110121294 | Semiconductor device - A semiconductor device includes a plurality of first data input/output terminals, a plurality of second data input/output terminals, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a plurality of first data input/output pads connected with the first data input/output terminals, a first test circuit, and a first memory portion. The first test circuit generates a first test result in response to a data output from the first memory portion at a test operation. The second semiconductor chip includes a plurality of second data input/output pads connected with the second data input/output terminals, a second and a third test circuits, and a second memory portion. The second test circuit generates a second test result in response to a data output from the second memory portion, and the third test circuit generates a third test result in response to the second test result and the first test result input from the first test circuit of the first semiconductor chip and outputs the third test result from a specified second data input/output terminal. | 05-26-2011 |
| 20110121295 | Structure for Bumped Wafer Test - A semiconductor device includes a substrate having a first conductive layer disposed on a top surface of the substrate. A first insulation layer is formed over the substrate and contacts a sidewall of the first conductive layer. A second conductive layer is formed over the first insulation layer. The second conductive layer includes a first portion disposed over the first conductive layer and a second portion that extends beyond an end of the first conductive layer. A second insulation layer is formed over the second conductive layer. A first opening in the second insulation layer exposes the first portion of the second conductive layer. A second opening in the second insulation layer away from the first opening exposes the second portion of the second conductive layer. The second insulation layer is maintained around the first opening. A conductive bump is formed over the first portion of the second conductive layer. | 05-26-2011 |
| 20110133184 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating film formed on a substrate; an interconnect layer including a plurality of interconnects formed in the insulating film; and a pad formed on the insulating film. In a region containing at least a part of a section below the pad, a narrow spacing region is formed, where a spacing between the adjacent interconnects is shorter than that in a section outside the region containing at least a part of the section below the pad. | 06-09-2011 |
| 20110133185 | SEMICONDUCTOR DEVICE FORMATION SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A dummy columnar electrode having the same outer size and cross section as a columnar electrode formed in a semiconductor device formation region is formed in the peripheral part of a semiconductor device test region in the same process as the columnar electrode. The semiconductor device test regions are provided at several places on the peripheral edge of an effective semiconductor wafer region. Each of the semiconductor device test regions is formed to partly protrude out of the effective semiconductor wafer region. Thus, the number of the semiconductor device formation regions to be products can be prevented from decreasing. | 06-09-2011 |
| 20110133186 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR WAFER HAVING SOI-INSULATED WELLS AND SEMICONDUCTOR WAFER THEREBY MANUFACTURED - A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region. | 06-09-2011 |
| 20110140104 | EMBEDDED STRUCTURE FOR PASSIVATION INTEGRITY TESTING - The present invention relates to a method and system for testing integrity of a passivation layer ( | 06-16-2011 |
| 20110140105 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy. | 06-16-2011 |
| 20110156031 | SEMICONDUCTOR DEVICE - A semiconductor device is protected from static electricity introduced through bump pads and probe test pads. The semiconductor device includes a bump pad through which data is inputted, a first electrostatic discharge unit configured to discharge static electricity introduced through the bump pad, a probe test pad through which data is inputted, the probe test pad having a larger size than the bump pad, a second electrostatic discharge unit configured to discharge static electricity introduced through the probe test pad, and an input buffer unit configured to buffer the data transferred through the bump pad or the probe test pad. | 06-30-2011 |
| 20110156032 | METHOD OF REPAIRING PROBE PADS - A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced. | 06-30-2011 |
| 20110156033 | METHOD AND SYSTEM FOR TRACING DIE AT UNIT LEVEL - A method and system for tracing die at unit level, comprising: assigning a first identification to a support member including a plurality of die support units; generating a second identification corresponding to a die support unit, the second identification including the first identification and a coordinate of the die support unit within the support member; correlating the second identification to a third identification of a die; attaching the die to the die support unit to generate a packaged die; and assigning the second identification to the packaged die. | 06-30-2011 |
| 20110156034 | REPAIR CIRCUIT AND REPAIR METHOD OF SEMICONDUCTOR APPARATUS - A repair circuit of a semiconductor apparatus includes a plurality of through-silicon vias including repeated sets of one repair through-silicon via and an M number of normal through-silicon vias; a transmission unit configured to multiplex input data at a first multiplexing rate based on control signals, and transmit the multiplexed data to the plurality of through-silicon vias; a reception unit configured to multiplex signals transmitted through the plurality of through-silicon vias at a second multiplexing rate based on the control signals, and generate output data; and a control signal generation unit configured to generate sets of the control signals based on an input number of a test signal. | 06-30-2011 |
| 20110156035 | DISGUISING TEST PADS IN A SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads. | 06-30-2011 |
| 20110156036 | METHOD FOR DETECTING A VOID - Methods for detecting a void in an element portion of a semiconductor device having an element portion and a void detection structure are disclosed. As a part of the method, an insulating film is formed on a substrate, a plurality of holes is formed in the insulating film, and a metal portion is formed on the insulating film to fill the plurality of holes. The metal portion is polished until the insulating film is exposed and a recessed portion is formed in the void detection structure. It is determined if a void exists in the element portion of the semiconductor device by determining whether or not a void is exposed at a surface of the recessed portion of the void detection structure. | 06-30-2011 |
| 20110163313 | BULK SILICON WAFER PRODUCT USEFUL IN THE MANUFACTURE OF THREE DIMENSIONAL MULTIGATE MOSFETS - A method for preparing a semiconductor structure for use in the manufacture of three dimensional transistors, the structure comprising a silicon substrate and an epitaxial layer, the epitaxial layer comprising an endpoint detection epitaxial region comprising an endpoint detection impurity selected from the group consisting of carbon, germanium, or a combination. | 07-07-2011 |
| 20110168995 | Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits - Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated. | 07-14-2011 |
| 20110186838 | CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER - A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group. | 08-04-2011 |
| 20110186839 | Method and System for Hermetically Sealing Packages for Optics - A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions. | 08-04-2011 |
| 20110193085 | Methods of Forming Structures with a Focused ION Beam for Use in Atomic Force Probing and Structures for Use in Atomic Force Probing - Methods for forming structures to use in atomic force probing of a conductive feature embedded in a dielectric layer and structures for use in atomic force probing. An insulator layer is formed on the dielectric layer such that the conductive feature is covered. A contact hole penetrates from a top surface of the insulator layer through the insulator layer to the conductive feature. The contact hole is at least partially filled with a conductive stud that is in electrical contact with the conductive feature and exposed at the top surface of the insulator layer so as to define a structure. A probe tip of an atomic force probe tool is landed on a portion of the structure and used to electrically characterize a device structure connected with the conductive feature. | 08-11-2011 |
| 20110193086 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR PACKAGES - A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption. | 08-11-2011 |
| 20110198587 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus according to aspects of the invention includes a power MOSFET including a main MOSFET and sensing MOSFET's. The main MOSFET and the sensing MOSFET's are formed on a semiconductor substrate, and a sensing MOSFET is selected for changing the sensing ratio and further for confining the sensing ratio variations within a certain narrow range stably from a low main current range to a high main current range. A semiconductor apparatus according to aspects of the invention facilitates reducing the manufacturing costs thereof, obviating the cumbersomeness caused in the use thereof, and confining the sensing ratio variations within a certain narrow range stably. | 08-18-2011 |
| 20110198588 | Polysilicon control etch-back indicator - This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions. | 08-18-2011 |
| 20110198589 | SEMICONDUCTOR CHIP - A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe. | 08-18-2011 |
| 20110204356 | METHOD FOR STAINING SAMPLE - A method for staining a sample includes the following steps. A test device is provided. The test device is sampled to obtain a sample. The sample includes a substrate, an active area disposed within the substrate and having a first doped substrate region and a second doped substrate region, at least one gate disposed between the first doped substrate region and the second doped substrate region, and an exposed shallow trench isolation embedded in the substrate and surrounding the active area. A first staining procedure is then carried out to selectively remove the shallow trench isolation to form a first void and to entirely expose the active area. A second staining procedure is subsequently carried out to selectively stain the first doped substrate region and the second doped substrate region to form a second void. | 08-25-2011 |
| 20110204357 | Semiconductor device and penetrating electrode testing method - Disclosed herein is a semiconductor device, including: a semiconductor substrate; an integrated circuit formed on a first main surface of the semiconductor substrate; a penetrating electrode that penetrates the semiconductor substrate in the thickness direction and has its one end electrically connected to the integrated circuit; a bump electrode formed on a second main surface of the semiconductor substrate and electrically connected to another end of the penetrating electrode; and a test pad electrode formed on the second main surface of the semiconductor substrate and electrically connected to the bump electrode. | 08-25-2011 |
| 20110204358 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGN METHOD, DESIGN APPARATUS, AND PROGRAM - An antenna ratio calculation section extracts components from which two or more independent metal wires are coupled to one of diffusion layer regions based on layout data read from a layout data accumulation section, determines, for each of the components, the area of each of the two or more independent metal wires and electrodes coupled to the respective metal wires, determines an antenna ratio between the area of each of the metal wires and the area of the electrode coupled to the metal wire, and determines a moderation value for moderating a design standard associated with plasma charge damage related to one of the metal wires based on the ratio of the total area of all the metal wires coupled to the one of the diffusion layer regions to the area of the one of the metal wires. | 08-25-2011 |
| 20110204359 | Semiconductor device - A semiconductor device includes a substrate, an insulator layer on the substrate, an inductor on the insulator layer, and a film including a ferromagnetic particle on the inductor. | 08-25-2011 |
| 20110210329 | Apparatus and method for predetermined component placement to a target platform - The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly. | 09-01-2011 |
| 20110227069 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR CHIP - A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n | 09-22-2011 |
| 20110233543 | TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS - A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks. | 09-29-2011 |
| 20110233544 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device according to the present invention, which has a termination structure in which a field plate is provided on an insulating film filled in a recessed region formed in a semiconductor substrate and includes a plurality of unit cells connected in parallel, includes: a gate wiring region in which gate wiring electrically connected to each gate electrode of the plurality of unit cells is provided; and a gate pad region electrically connected to the gate wiring region, wherein the gate wiring region is disposed on the insulating film filled in a recessed region formed in the semiconductor substrate. | 09-29-2011 |
| 20110233545 | Semiconductor Chip Having Double Bump Structure And Smart Card Including The Same - Provided is a semiconductor chip having a double bump structure. The semiconductor chip may include a semiconductor substrate, a circuit region on a surface of the semiconductor substrate, a pad on the semiconductor substrate and connected to the circuit region, a first bump on the pad, and a second bump on the first bump. The second bump may be arranged at one side of an upper surface of the first bump and the upper surface of the first bump may include a test area configured to interface with a probe tip, wherein the test area is an area of the upper surface of the first bump exposed by the second bump | 09-29-2011 |
| 20110233546 | WAFER-TYPE TEMPERATURE SENSOR AND MANUFACTURING METHOD THEREOF - A wafer-type temperature sensor may include a wafer for temperature detection; a circuit board bonded to one surface of the wafer for temperature detection; at least one temperature data detector provided on the one surface of the wafer for temperature detection and capable of detecting temperature data; and a temperature detecting unit mounted on the circuit board and capable of detecting a temperature of the wafer for temperature detection from the temperature data detected by the temperature data detector. Here, a difference between a linear expansion coefficient of the circuit board and a linear expansion coefficient of the wafer for temperature detection may be equal to or less than a predetermined value. | 09-29-2011 |
| 20110233547 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - In a display apparatus and a method of manufacturing the display apparatus, a gate line, a data line, and a plurality of layers are formed on an array substrate on which a pixel area, a pad area, and a peripheral area are defined. During the forming processes of the gate line, the data line, and the layers, the gate line and the data line are partially exposed in the peripheral area, or contact portions formed on the gate line and the data line in the peripheral area are exposed. Thus, the gate line and the data line may be tested using the contact portions as electrical terminals during the manufacturing process of the display apparatus. | 09-29-2011 |
| 20110233548 | TEST CIRCUIT FOR USE IN A SEMICONDUCTOR APPARATUS - A test circuit that senses a misaligned probe during a test includes a first power control section that senses voltage levels of a plurality of sensing lines and controls power supplied to a lower circuit section provided below a part of a pad group, and a second power control section that selectively provides an internal voltage in response to a sensing result of the first power control section. | 09-29-2011 |
| 20110248263 | INTEGRATED CIRCUITS HAVING BACKSIDE TEST STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating an integrated circuit having a backside test structure are provided. In one embodiment, the method includes the steps of providing a semiconductor substrate, forming at least one Through-Silicon-Via (TSV) through the semiconductor substrate, forming a backside probe pad over the backside of the semiconductor substrate and electrically coupled to the at least one TSV, and forming a frontside bondpad over the frontside of the semiconductor substrate. The frontside bondpad is electrically coupled to the backside probe pad by the at least one TSV. | 10-13-2011 |
| 20110248264 | Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate - In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions. | 10-13-2011 |
| 20110253999 | SEMICONDUCTOR WAFER HAVING SCRIBE LINE TEST MODULES INCLUDING MATCHING PORTIONS FROM SUBCIRCUITS ON ACTIVE DIE - A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension. | 10-20-2011 |
| 20110254000 | SEMICONDUCTOR CHIP EMBEDDED WITH A TEST CIRCUIT - A semiconductor chip includes a semiconductor chip body having a first surface on which pad parts are formed and an opposing second surface. Through-electrodes may be connected to the pad parts and formed to pass through the semiconductor chip body. Determination units may be connected to the through-electrodes and may be enabled to determine whether the pad parts and the through-electrodes are electrically connected with each other. | 10-20-2011 |
| 20110254001 | HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY - A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry. | 10-20-2011 |
| 20110260161 | Test device and semiconductor integrated circuit device - Test devices and integrated circuits with improved productivity are provided. In accordance with example embodiments, a test device may include a first test region with a first test element and a second test region with a second test element defined on a semiconductor substrate. The first test element may include a pair of first secondary test regions in the semiconductor substrate and a pair of first test gate lines. One of the first test gate lines may overlap one of the first secondary test regions and the other first test gate line may overlap the other first secondary test region. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions and the pair of first test gate lines. | 10-27-2011 |
| 20110260162 | Device for Protecting an Electronic Integrated Circuit Housing Against Physical or Chemical Ingression - The invention relates to the creation of a housing for an integrated circuit which makes it possible to detect physical ingression into said housing. The invention applies in particular to the protection of secrets which may possibly be contained in said integrated circuit, in the event of physical attack, for example by destroying the secrets contained in an integrated circuit in the event of ingression into the housing thereof. | 10-27-2011 |
| 20110266539 | High Performance Compliant Wafer Test Probe - An electrical connection includes a first electrical contact made of electrically conductive material. The first electrical contact is formed with a depression therein. Also included are a deformable pad, having a Young's modulus of less than 1,000,000 psi, which bears on the first contact; and a second electrical contact, made of electrically conductive material, which contacts the first electrical contact and is at least partially received into the depression. The deformable pad at least partially causes at least one lateral force on the first electrical contact, so as to induce the first electrical contact to make an electrical connection with the second electrical contact. An array of such contacts is also contemplated, as is an array of cantilevered contacts, which may or may not have depressions, and which are supported by at least one elastomeric pad, having a Young's modulus of less 72,500 psi. | 11-03-2011 |
| 20110266540 | SEMICONDUCTOR DEVICE - Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region. | 11-03-2011 |
| 20110266541 | Probe Pad On A Corner Stress Relief Region In A Semiconductor Chip - A semiconductor chip includes a circuit region and a corner stress relief (CSR) region. The CSR region is in a corner of the semiconductor chip. A device under test (DUT) structure or a functional circuit is disposed on the circuit region. A probe pad is disposed on the CSR region. A metal line extends from the circuit region to the CSR region to electrically connect the probe pad to the DUT structure or a functional circuit. | 11-03-2011 |
| 20110272692 | SIZE VARIABLE TYPE SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE USING THE SAME - A size variable semiconductor chip includes a semiconductor chip area formed with a circuit layer and at least one cutting area extending parallel to at least one side of the semiconductor chip area. A plurality of scribe line parts and a plurality of active parts alternately formed with each other in the cutting area. | 11-10-2011 |
| 20110272693 | MANUFACTURING METHOD OF ULTRASONIC PROBE AND ULTRASONIC PROBE - The manufacturing yield of semiconductor devices (CMUTs) is improved. Before a polyimide film serving as a protective film is formed, a membrane is repeatedly vibrated to evaluate the breakdown voltage between an upper electrode and a lower electrode, and the upper electrode of a defective CMUT cell whose breakdown voltage between the upper electrode and the lower electrode is reduced due to the repeated vibrations of the membrane is removed in advance to cut off the electrical connection with other normal CMUT cells. By this means, in a block RB or a channel RCH including the recovered CMUT cell RC, reduction in the breakdown voltage between the upper electrode and the lower electrode after the repeated vibrations of the membrane is prevented. | 11-10-2011 |
| 20110278568 | MANUFACTURING PROCESS OF INTEGRATED ELECTRONIC CIRCUITS AND CIRCUITS THEREBY OBTAINED - An embodiment of a manufacturing process of an integrated electronic circuit is proposed; the process comprises forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe and running an electric test of the electronic circuit. In an embodiment, the process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe. | 11-17-2011 |
| 20110278569 | WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS - A wafer level integration module and method for forming are disclosed. A construction includes semiconductor functional device fabrication carried out after interconnect structures are processed on a bare wafer. Interconnect structures are formed in a first side of the wafer. An insulation layer is deposited on the first side of the wafer to insulate walls of the interconnect structures. A conductive layer is deposited on the insulation layer filling the interconnect structures so as to contact the insulation layer on the walls of the interconnect structures. The conductive layer forms interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer. The first conductive layer including the interconnection contacts is exposed on the first side of the wafer and a semiconductor functional device is formed on the first side of the wafer. The semiconductor functional device is interconnected with the interconnection contacts during the fabricating. At least portions of the conductive layer associated with the interconnection vias are exposed from the second side of the wafer. | 11-17-2011 |
| 20110284840 | Process Monitor for Monitoring an Integrated Circuit Chip - A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals. | 11-24-2011 |
| 20110284841 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to one embodiment of this invention includes: a semiconductor chip; a plurality of external connection pads and a plurality of first test pads, both of which are formed in a central region of a top surface of the semiconductor chip; a plurality of external connection electrodes each formed on a corresponding one of the external connection pads, the external connection electrodes being for connecting the external connection pads and an outside of the semiconductor device. | 11-24-2011 |
| 20110284842 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LAMINATE BASE - An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated. | 11-24-2011 |
| 20110284843 | Probe Pad On A Corner Stress Relief Region In A Semiconductor Chip - A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure. | 11-24-2011 |
| 20110297932 | Semiconductor device and integrated semiconductor device - The present disclosure provides a semiconductor device including: a semiconductor identifier holding portion configured to hold a semiconductor identifier for identifying a semiconductor device; and a control portion configured such that upon elapse of a predetermined time period following receipt of an externally input instruction to hold the semiconductor identifier, the control portion issues an instruction to the semiconductor device immediately downstream of the semiconductor device to hold a semiconductor identifier of the immediately downstream semiconductor device and that during the time period between the point in time at which the externally input instruction is received and the point in time at which the instruction is issued to the immediately downstream semiconductor device to hold the semiconductor identifier thereof, the control portion causes the semiconductor identifier holding portion to hold the externally input identifier. | 12-08-2011 |
| 20110297933 | Semiconductor Packages - Provided are a semiconductor package, a semiconductor memory module including the semiconductor package, and a system including the semiconductor memory module. The semiconductor package may include a plurality of main terminals arranged on a surface of the semiconductor package with constant intervals, and the plurality of main terminals may include terminals of a first set including a plurality of input/output terminals to which test signals may be input, and terminals of a second set including a plurality of input/output terminals to/from which signals other than the test signals may be input/output. | 12-08-2011 |
| 20110297934 | SEMICONDUCTOR DEVICE - A reverse conducting semiconductor device having an IGBT element region and a diode element region in one semiconductor substrate is provided. An electric current detection region is arranged adjacent to the IGBT element region, and a collector region of the IGBT element region is extended to connect with a collector region of the electric current detection region. Instability in the IGBT detection current caused by a boundary portion between the IGBT and the diode can be suppressed. In the same way, an electric current detection region is arranged adjacent to the diode element region, and a cathode region of the diode element region is extended to connect with a cathode region of the electric current detection region. Instability in the diode detection current caused by the boundary portion between the IGBT and the diode can be suppressed. | 12-08-2011 |
| 20110297935 | SEMICONDUCTOR DEVICE WITH APPRAISAL CIRCUITRY - A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value. | 12-08-2011 |
| 20110303915 | Compressively Stressed FET Device Structures - Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins. | 12-15-2011 |
| 20110309357 | MEASURING APPARATUS - A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. | 12-22-2011 |
| 20110309358 | SEMICONDUCTOR CHIP WITH FINE PITCH LEADS FOR NORMAL TESTING OF SAME - A semiconductor chip includes a semiconductor substrate having a top surface and a bottom surface. A circuit layer having bonding pads may be formed over the top surface of the semiconductor substrate. Through electrodes may be formed to pass from a bottom surface to a top surface of the semiconductor substrate, and the through electrodes may comprise through parts connected with the bonding pads and projecting parts formed over the bottom surface of the semiconductor substrate and electrically connected with the through parts. Test pad parts may be disposed over the bottom surface of the semiconductor substrate and is connected with the through electrodes to test normal operation of the circuit layer and electrical connections of the through electrodes and the circuit layer. | 12-22-2011 |
| 20110309359 | SEMICONDUCTOR DEVICE - In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods. Therefore, for a device test of a Through Silicon Via through a plurality of chips, a circuit that generates a time-series test pattern having both 0 and 1 values for a delay fault test is added to a circuit portion that transmits data to a Through Silicon Via in the stacked LSIs, and a circuit that receives the test pattern and compares the pattern received with a fixed pattern for a match to detect a defect of a Through Silicon Via is added to a circuit portion that receives data from a Through Silicon Via in the stacked LSIs. | 12-22-2011 |
| 20110315984 | SEMICONDUCTOR MEMORY CARD AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory card that includes a printed substrate in which an electronic component is mounted on one surface, and an external terminal is installed on the other surface, and that is molded in a card form. The printed substrate is a laminated body in which a metallic interconnection for connecting the electronic component to the terminal and a solder resist are sequentially laminated on both surfaces of a core material. The semiconductor memory card includes an ink layer on the solder resist of the other surface, and a mark is engraved by a laser on the ink layer. | 12-29-2011 |
| 20110315985 | SENSOR-FITTED SUBSTRATE AND METHOD FOR PRODUCING SENSOR-FITTED SUBSTRATE - A sensor-fitted substrate allowing a sensor-fitted wafer for measuring the temperature or strain to be produced inexpensively, moreover, allowing measurements of the temperature or strain to be carried out with satisfactory accuracy, and a method for producing such a sensor-fitted substrate. An undercoat film is formed on the surface of a substrate, the film being configured, compared to when no undercoat film is formed, to allow the strength of close contact of a dispersed nano-particle ink with the substrate to be increased, the diffusion of the dispersed nano-particle ink into the substrate to be suppressed, and the growth of metal crystal particles contained in the dispersed nano-particle ink to be suppressed. A wiring pattern of the sensor is traced on the surface of the undercoat film of the substrate surface by using the dispersed nano-particle ink, and the dispersed nano-particle ink is baked and metalized. | 12-29-2011 |
| 20110315986 | SEMICONDUCTOR INTEGRATED CIRCUIT - Whether there is a defect such as chipping of a die or separation of a resin in a wafer level package is electrically detected. A peripheral wiring is disposed along four peripheries of a semiconductor substrate outside a circuit region and pad electrodes P | 12-29-2011 |
| 20110315987 | PORTABLE MEMORY DEVICES - Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test contacts are no longer electrically exposed. Hence, the integrated circuit products are not susceptible to accidental access or electrostatic discharge. Moreover, the integrated circuit products can be efficiently produced in a small form factor without any need for additional packaging or labels to electrically isolate the test contacts. | 12-29-2011 |
| 20120001174 | Test Structure for Controlling the Incorporation of Semiconductor Alloys in Transistors Comprising High-K Metal Gate Electrode Structures - When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved. | 01-05-2012 |
| 20120001175 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING A COUPLING EFFECT OF A TEST-DISABLE TRANSMISSION LINE - Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal. | 01-05-2012 |
| 20120001176 | ETCH DEPTH DETERMINATION STRUCTURE - A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion. | 01-05-2012 |
| 20120001177 | SEMICONDUCTOR DEVICE - In a multi-chip semiconductor device, a second semiconductor chip is stacked on a first semiconductor chip with an adhesive layer being interposed therebetween, and the first and second semiconductor chips are sealed by resin containing a mixture of, e.g., a filler. The first semiconductor chip includes a first region on a surface of which the second semiconductor chip is stacked, and a second region on a surface of which the second semiconductor chip does not stacked. In one of interconnect layers including an uppermost layer, a wiring pattern is not provided, which extends across a border between the first and second regions. | 01-05-2012 |
| 20120007073 | Semiconductor Wafer Constructions, And Methods For Quality Testing Material Removal Procedures During Semiconductor Fabrication Processes - Some embodiments include methods for quality testing material removal procedures. A test structure is formed to contain a pair of electrically conductive segments. The segments are the same relative to a detectable property as long as they are electrically connected, but becoming different relative to such property if they are disconnected from one another. A material is formed over the test structure, and across a region of a semiconductor substrate proximate to the test structure. The material is subjected to a procedure which removes at least some of it, and which fabricates a structure of an integrated circuit construction in the region proximate to the test structure. After the procedure, it is determined if the segments are the same relative to the detectable property. | 01-12-2012 |
| 20120007074 | THERMALLY SENSITIVE MATERIAL EMBEDDED IN THE SUBSTRATE - A structure and methods for using an integrated circuit structure comprise a substrate and circuitry connected to the substrate. The substrate includes a heat sensitive material that changes color when heated. The heat sensitive material has one of a plurality of colors depending upon a temperature to which the substrate was exposed. | 01-12-2012 |
| 20120007075 | SEMICONDUCTOR CHIP WITH BACKSIDE CONDUCTOR STRUCTURE - Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway. | 01-12-2012 |
| 20120007076 | LIGHT EMITTING MODULE - Disclosed is a light emitting module capable of representing improved heat radiation and improved light collection. there is provided a light emitting module. The light emitting module includes a metallic circuit board formed therein with a cavity, and a light emitting device package including a nitride insulating substrate attached in the cavity of the metallic circuit board, at least one pad part on the nitride insulating substrate, and at least one light emitting device attached on the pad part. | 01-12-2012 |
| 20120012841 | Through-silicon via testing structure - A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal. | 01-19-2012 |
| 20120012842 | SEMICONDUCTOR DEVICE HAVING FUNCTION OF TRANSMITTING/RECEIVING - In one embodiment, a semiconductor device includes an integrated circuit formed in an area enclosed by dicing lines formed in a matrix manner, and a signal wiring formed on at least one of the dicing lines. The integrated circuit includes a transmitter circuit having a signal output pad, a receiver circuit having a signal input pad and an internal circuit to process data inputted to the transmitter circuit and outputted from the receiver circuit. The signal wiring electrically connects the signal output pad and the signal input pad. | 01-19-2012 |
| 20120012843 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DESIGNING THE SAME - Unless layers over a TEG pattern are removed, a test using the TEG pattern is conducted. Multiple wiring layers are formed over a first TEG pattern. A wiring and multiple dummy patterns are formed in each of the wiring layers. An electrode pad is formed in an uppermost wiring layer. In a planar view, the first TEG pattern eliminates overlap with all of the wirings and the dummy patterns. | 01-19-2012 |
| 20120012844 | SEMICONDUCTOR MEMORY APPARATUS FOR CONTROLLING PADS AND MULTI-CHIP PACKAGE HAVING THE SAME - A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups. | 01-19-2012 |
| 20120018723 | STRUCTURE AND METHOD FOR TESTING THROUGH-SILICON VIA (TSV) - A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result. | 01-26-2012 |
| 20120018724 | Semiconductor device and stacked semiconductor apparatus - A semiconductor device includes: a through-electrode formed in a perpendicular direction so as to extend therethrough; a series circuit section formed from a plurality of test-ready switches successively connected in series and driven by a driving voltage transmitted to the through-electrode through a predetermined different layer through-electrode of a different semiconductor device stacked on an upper layer side or a lower layer side; and a pair of test terminals connected to end portions of the series circuit section and adapted to be used for measurement of conduction of the series circuit section. | 01-26-2012 |
| 20120018725 | SEMICONDUCTOR DEVICE FOR DRIVING ELECTRIC MOTOR - A FET for driving an electric motor includes a source electrode. The source electrode has main electrode surfaces to which bonding wires, through which a drive current for an electric motor passes, are joined, and inspection electrode surfaces that are arranged so as to be independent of and apart from the main electrode surfaces. The inspection electrode surfaces are provided so as to contact a probe of an inspection device that performs an inspection of the FET | 01-26-2012 |
| 20120018726 | SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor wafer in which a plurality of regions, designed to become semiconductor chips are provided in a matrix array with interposition of a dicing line(s) respectively separating the regions. The semiconductor wafer comprises: a plurality of test pads provided in an area(s) of the semiconductor wafer disposed between the semiconductor chips, inclusive of the dicing line(s); an inter-test pad interconnect(s) provided in parallel with the test pads in the area(s) of the semiconductor wafer disposed between the regions to become semiconductor chips; the inter-test pad interconnect(s) being connected to the test pads; and an inter-chip interconnect that interconnects at least two of the regions designed to become semiconductor chips; the inter-test pad interconnect being electrically connected to the inter-chip interconnect. | 01-26-2012 |
| 20120025188 | SEMICONDUCTOR DEVICE INTEGRATED WITH MONITORING DEVICE IN CENTER THEREOF - One type of a semiconductor device integrating with a monitoring device is disclosed. The device includes a plurality of gate fingers, two of which arranged in a center of the device has a space wider than a space between any other fingers to suppress the heat concentration on the center of the device. The monitoring region is arranged in this wider space to monitor the temperature dependence of the device. | 02-02-2012 |
| 20120032167 | SEMICONDUCTOR PACKAGE AND METHOD OF TESTING SAME - A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to the wire layout pattern. An encapsulation material covers at least the integrated circuit and the solder mask layer. One or more crack seal rings are disposed on the solder mask surface. The crack seal rings are copper traces with terminals that allow current to be applied to the traces. A broken trace (open circuit condition) is indicative of a crack in the package. Thus, electrical testing is performed to detect physical defects. | 02-09-2012 |
| 20120043539 | SEMICONDUCTOR CHIP WITH THERMAL INTERFACE TAPE - A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip. | 02-23-2012 |
| 20120056177 | 3D INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR DETECTING CHIP MIS-ALIGNEMENT - The present application discloses a 3D integrated circuit structure and a method for detecting whether there is misalignment between chip structures. The circuit structure comprises a first chip structure which comprises a first semiconductor substrate, a first insulating layer, and a first detection structure; the first detection structure comprises detection bodies positioned on two sides of the first insulating layer, the detection body comprising a first conductor, at least two second conductors, and at least one third conductors; wherein the first conductor is located on a side of the first insulating layer and connected with ends of the second conductors; the third conductors are formed between the second conductors and insulated from the second conductors, and the first ends of the third conductors away from the first conductor are step-wise; wherein vertical distances between the third conductors and the second conductors are equal, and in the direction of the length of the third conductors, the distances between the projections of the ends of the third conductors away from the first conductor which are corresponding to each other and located on the detection bodies on the two sides are substantially the same. The present invention is suitable for optimizing the alignment between the chip structures in manufacture of integrated circuits. | 03-08-2012 |
| 20120056178 | MULTI-CHIP PACKAGES - A multi-chip package may include a package substrate, a plurality of semiconductor chips and conductive connecting members. The semiconductor chips may be sequentially stacked on the package substrate. Each of the semiconductor chips may include a signal pad and a test pad. The conductive wires may be electrically connected between the signal pad of an upper semiconductor chip among the semiconductor chips and the package substrate via the test pad of a lower semiconductor chip under the upper semiconductor chip. The test pad may be converted into the dummy pad by cutting a fuse. | 03-08-2012 |
| 20120061669 | CHIP ON FILM (COF) PACKAGE HAVING TEST LINE FOR TESTING ELECTRICAL FUNCTION OF CHIP AND METHOD FOR MANUFACTURING SAME - A chip on film (COF) package and a method for manufacturing same are provided. The COF package comprises a base film, a semiconductor chip mounted on the base film, a signal-inputting portion mounted on the base film, a first passive element mounted on the base film and comprising first and second terminals and a first signal line formed on the base film and connecting the first passive element to the semiconductor chip, wherein the first signal line comprises a connection pad connected to the first terminal of the first passive element and a first test line connected to the signal-inputting portion. | 03-15-2012 |
| 20120068174 | ELECTRICAL MASK INSPECTION - An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain. | 03-22-2012 |
| 20120068175 | Method to Optimize and Reduce Integrated Circuit, Package Design, and Verification Cycle Time - A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements. | 03-22-2012 |
| 20120068176 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, an edge seal, a plurality of pad pieces, and an insulating film pattern. The semiconductor substrate includes a chip area formed at an inward side of the semiconductor substrate when viewed in a direction perpendicular to a surface of the semiconductor substrate. The edge seal is disposed around the chip area on the surface to protect the chip area. The plurality of pad pieces are disposed on an edge region on the surface. The insulating film pattern covers edge portions of the plurality of pad pieces at a side of the edge seal, at least at one side of the chip area on the surface in a first direction and at least at one side of the chip area on the surface in a second direction. | 03-22-2012 |
| 20120068177 | MEASURING APPARATUS - A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat. | 03-22-2012 |
| 20120074400 | MULTIPLE EDGE ENABLED PATTERNING - Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance. | 03-29-2012 |
| 20120074401 | TEST PATTERN FOR DETECTING PIPING IN A MEMORY ARRAY - A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided. | 03-29-2012 |
| 20120074402 | PACKAGING STRUCTURE - This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips. | 03-29-2012 |
| 20120080672 | TWO-PHOTON-ABSORPTION-BASED SILICON WAVEGUIDE PHOTO-POWER MONITOR - Instead of monitoring the optical power coming out of a waveguide, a direct method of monitoring the optical power inside the waveguide without affecting device or system performance is provided. A waveguide comprises a p-i-n structure which induces a TPA-generated current and may be enhanced with reverse biasing the diode. The TPA current may be measured directly by probing metal contacts provided on the top surface of the waveguide, and may enable wafer-level testing. The p-i-n structures may be implemented at desired points throughout an integrated network, and thus allows probing of different devices for in-situ power monitor and failure analysis. | 04-05-2012 |
| 20120080673 | Crack Stop Barrier and Method of Manufacturing Thereof - A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier. | 04-05-2012 |
| 20120080674 | LED PACKAGE - According to one embodiment, an LED package includes first and second lead frames spaced from each other, and an LED chip. Each of the first and second lead frames includes a base portion and a plurality of extending portions extending from the base portion. A part of a lower surface of the base portion, side surfaces of the base portion, lower surfaces of the extending portions and side surfaces of the extending portions are covered by resin. A remaining part of the lower surface of the base portion and tip surfaces of the extending portions are not covered by resin. The part of the lower surface of the base portion includes a first edge of the first lead frame and a second edge of the second lead frame. The first edge and the second edge are opposed each other. | 04-05-2012 |
| 20120086003 | SEMICONDUCTOR DEVICE AND TEST SYSTEM FOR THE SEMICONDUCTOR DEVICE - A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member. | 04-12-2012 |
| 20120086004 | ELASTIC ENCAPSULATED CARBON NANOTUBE BASED ELECTRICAL CONTACTS - Contacts of an electrical device can be made of carbon nanotube columns. Contact tips can be disposed at ends of the columns. The contact tips can be made of an electrically conductive paste applied to the ends of the columns and cured (e.g., hardened). The paste can be applied, cured, and/or otherwise treated to make the contact tips in desired shapes. The carbon nanotube columns can be encapsulated in an elastic material that can impart the dominant mechanical characteristics, such as spring characteristics, to the contacts. The contacts can be electrically conductive and can be utilized to make pressure-based electrical connections with electrical terminals or other contact structures of another device. | 04-12-2012 |
| 20120091454 | INLINE PROCESS CONTROL STRUCTURES - A method for process control is disclosed. The method includes performing an etching process on a semiconductor substrate forming a structure and a test structure having a pattern and a releasing mechanism coupled to the pattern; and monitoring the pattern of the test structure to determine whether the etching process is complete. | 04-19-2012 |
| 20120091455 | PAD STRUCTURE HAVING CONTACT BARS EXTENDING INTO SUBSTRATE AND WAFER HAVING THE PAD STRUCTURE - A pad structure in a semiconductor wafer for wafer testing is described. The pad structure includes at least two metal pads connected there-between by a plurality of conductive vias in one or more insulation layers. A plurality of contact bars in contact with the bottom-most metal pad extends substantially vertically from the bottom-most metal pad into the substrate. An isolation structure substantially surrounds the plurality of contact bars to isolate the pad structure. | 04-19-2012 |
| 20120097944 | TEST STRUCTURES FOR THROUGH SILICON VIAS (TSVs) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded. | 04-26-2012 |
| 20120104387 | Four-Terminal Metal-Over-Metal Capacitor Design Kit - A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer. | 05-03-2012 |
| 20120104388 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND TSV REPAIR METHOD THEREOF - Provided is a | 05-03-2012 |
| 20120104389 | SACRIFICIAL WAVEGUIDE TEST STRUCTURES - Sacrificial optical test structures are constructed upon a wafer ( | 05-03-2012 |
| 20120119208 | SEMICONDUCTOR APPARATUS AND FABRICATING METHOD THEREOF - A semiconductor apparatus includes a semiconductor chip formed on a predetermined area of a wafer, wafer test block formed on an area outside the predetermined area, and signal line for electrically connecting the semiconductor chip to the wafer test block. Through-silicon via is formed to vertically penetrate the signal line. | 05-17-2012 |
| 20120119209 | SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes isolation layers arranged in a memory array region and a monitoring region, wherein the isolation layers are positioned in parallel; gate lines arranged to cross the isolation layers in the memory array region, wherein the gate lines are formed in the memory array region; dummy gate lines arranged in a substantially same direction as the isolation layers in the monitoring region, wherein the dummy gate lines are formed in the monitoring region; monitoring junctions arranged between the dummy gate lines and in a substantially same direction as the dummy gate lines, wherein the monitoring junctions are arranged in the monitoring region; and spacers arranged on sidewalls of each of the gate lines and the dummy gate lines, wherein at least one of the monitoring junctions is covered by any one of the spacers. | 05-17-2012 |
| 20120126228 | Material Structure in Scribe Line and Method of Separating Chips - A method for manufacturing a chip is disclosed. The method comprises forming a material structure in a kerf adjacent the chip on a wafer. The method further comprises selectively removing the material structure in the kerf and dicing the wafer. | 05-24-2012 |
| 20120126229 | INTERCONNECTION STRUCTURES AND METHODS FOR TRANSFER-PRINTED INTEGRATED CIRCUIT ELEMENTS WITH IMPROVED INTERCONNECTION ALIGNMENT TOLERANCE - An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed. | 05-24-2012 |
| 20120126230 | METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP STACK DEVICE - A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array. | 05-24-2012 |
| 20120138924 | METHOD FOR MEASURING IMPURITY CONCENTRATION PROFILE, WAFER USED FOR SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME - According to an embodiment, a method for measuring an impurity concentration profile uses a wafer including a semiconductor layer. The method includes measuring an impurity concentration profile in a depth direction from each surface of a plurality of first portions, each of the first portions being included in any one of a plurality of first regions provided in the semiconductor layer. Each of the first regions has a different size and is surrounded by a second region including a second portion having a different structure from the first portion. The method includes determining a change between the impurity concentration profiles measured in the first regions. | 06-07-2012 |
| 20120138925 | SEMICONDUCTOR CHIP, STACK-TYPE SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor chip includes: a first substrate having a first surface and a second surface facing away from the first surface; a first test through silicon via (TSV) passing through the first substrate from the first surface to the second surface; and a conductive protrusion coupled to the first test TSV and protruding from the second surface. | 06-07-2012 |
| 20120138926 | ARRAY SUBSTRATE, MANUFACTURING METHOD AND DETECTING METHOD THEREOF, AND LIQUID CRYSTAL PANEL - An embodiment of the present disclosure provides a method of manufacturing an array substrate, comprising at least a step of forming a TFT pattern in a pixel region and correspondingly forming a TFT testing pattern in a testing region, wherein before forming a passivation layer to cover the pixel region and the testing region, a step of removing a gate insulation layer thin film above a testing line lead in the TFT testing pattern. | 06-07-2012 |
| 20120138927 | SEMICONDUCTOR DEVICE HAVING STACKED STRUCTURE INCLUDING THROUGH-SILICON-VIAS AND METHOD OF TESTING THE SAME - A semiconductor device having a stacked structure including through-silicon-vias (TSVs) and a method of testing the semiconductor device. The semiconductor device includes a first semiconductor layer, one or more second semiconductor layers stacked on the first semiconductor layer, and a plurality of input through-silicon-vias (TSVs) to transmit signals from a plurality of input pads, respectively. In a test mode, a test signal from the plurality of input pads is transmitted through at least two test paths, and the test signal transmitted through each of the test paths is output as a test result with respect to each of the plurality of input TSVs through an output pad. | 06-07-2012 |
| 20120153279 | SEMICONDUCTOR SENSOR RELIABILITY OPERATION - Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted. Based on the output, one or more functional blocks are modified by a control sensor component to reduce semiconductor system degredation in real-time. | 06-21-2012 |
| 20120153280 | INTEGRATED CIRCUIT FOR DETECTING DEFECTS OF THROUGH CHIP VIA - An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode. | 06-21-2012 |
| 20120153281 | APPARATUS AND METHODS FOR DETERMINING OVERLAY OF STRUCTURES HAVING ROTATIONAL OR MIRROR SYMMETRY - A semiconductor target for determining a relative shift between two or more successive layers of a substrate is provided. The target comprises a plurality of first structures formed in a first layer, and the first structures have a first center of symmetry (COS). The target further comprises a plurality of second structures formed in a second layer, and the second structures have second COS. The difference between the first COS and the second COS corresponds to an overlay error between the first and second layer and wherein the first and second structures have a 180° rotational symmetry, without having a 90° rotational symmetry, with respect to the first and second COS, respectively. | 06-21-2012 |
| 20120153282 | SEMICONDUCTOR DEVICE - Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip. | 06-21-2012 |
| 20120161128 | DIE PACKAGE - According to one embodiment, a die package is provided comprising a first die structure with a first plurality of switching elements wherein controlled current input terminals of the first plurality of switching elements are electrically coupled by a common contact region and wherein controlled current output terminals of the first plurality of switching elements are insulated from each other; a second die structure with a second plurality of switching elements wherein controlled current output terminals of the second plurality of switching elements are coupled by a common contact region and wherein controlled current input terminals of the second plurality of switching elements are insulated from each other; and wherein, for each of the first plurality of switching elements, the output terminal of the switching element is coupled with the input terminal of at least one switching element of the second plurality of switching elements. | 06-28-2012 |
| 20120161129 | METHOD AND APPARATUS OF FABRICATING A PAD STRUCTURE FOR A SEMICONDUCTOR DEVICE - The present disclosure involves a semiconductor device. The semiconductor device includes a substrate and an interconnect structure that is formed over the substrate. The interconnect structure has a plurality of metal layers. A first region and a second region each extend through both the interconnect structure and the substrate. The first and second regions are mutually exclusive. The semiconductor device includes a plurality of bond pads disposed above the first region, and a plurality of probe pads disposed above the second region. The semiconductor device also includes a plurality of conductive components that electrically couple at least a subset of the bond pads with at least a subset of the probe pads. Wherein each one of the subset of the bond pads is electrically coupled to a respective one of the subset of the probe pads through one of the conductive components. | 06-28-2012 |
| 20120168751 | Integrated Circuit Test Units with Integrated Physical and Electrical Test Regions - A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region. | 07-05-2012 |
| 20120168752 | TESTKEY STRUCTURE, CHIP PACKAGING STRUCTURE, AND METHOD FOR FABRICATING THE SAME - The invention provides a testkey structure for testing a chip. The testkey structure includes a metal pad and a first groove, wherein the first groove is disposed on the metal pad. The first groove is located between a first signal lead and a second signal lead of the chip. According to the first groove, the first signal lead and the second signal lead could be separated from each other to prevent the first signal lead and the second signal lead from shorting. | 07-05-2012 |
| 20120175612 | TEST STRUCTURE FOR DETERMINATION OF TSV DEPTH - A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. | 07-12-2012 |
| 20120181535 | PHOTOELECTRIC CONVERSION MODULE AND METHOD OF MANUFACTURING THE SAME - A photoelectric conversion module includes a circuit board including a plurality of first board-side electrodes and a plurality of second board-side electrodes that are alternately arranged on a mounting surface of the circuit board in an array direction and each extend into strips in a direction orthogonal to the array direction, a photoelectric conversion array element mounted on the circuit board and including, on a surface facing the mounting surface, a plurality of light receiving/emitting portions, first element-side electrodes connected to the first board-side electrodes and second element-side electrodes connected to the second board-side electrodes, and an IC chip mounted on the circuit board. The circuit board further includes, on the mounting surface, a connecting portion for connecting the first board-side electrodes to each other and a first electrode land portion connected to the first board-side electrode or the connecting portion to contact with a first test electrode probe. | 07-19-2012 |
| 20120187400 | TEST STRUCTURE FOR DETECTION OF GAP IN CONDUCTIVE LAYER OF MULTILAYER GATE STACK - A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer. | 07-26-2012 |
| 20120187401 | DEVICE ALLOWING SUPPRESSION OF STRESS ON CHIP - A device includes: a first substrate including a plurality of first electrodes; a plurality of chips each including a plurality of through electrodes, the chips being stacked with each other such that the through electrodes of a lower one of the chips are connected respectively the through electrodes of an upper one of the chips to provide a chip stacked body; and a second substrate cooperating the first substrate to sandwich the chip stacked body between the first and second substrates, the second substrate including a plurality of second electrodes on a first surface that is opposite to a second surface facing the chip stacked body, each of the second electrodes being electrically connected to an associated one of the through electrodes of an uppermost one of the chips of the chip stacked body. | 07-26-2012 |
| 20120187402 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having first and second surfaces. A first through electrode extends through the semiconductor chip. A first surface electrode is positioned on the first surface of the semiconductor chip and coupled to a first end of the first through electrode. A second surface electrode is positioned on the second surface of the semiconductor chip. The second surface electrode is coupled to a second end of the first through electrode. A second through electrode extends through the semiconductor chip and has third and fourth ends. A third surface electrode is positioned on the second surface of the semiconductor chip and is coupled to the fourth end of the second through electrode. The semiconductor device is free of a surface electrode on the first surface of the semiconductor chip and is coupled to the third end of the second through electrode. | 07-26-2012 |
| 20120187403 | TEST DEVICE AND A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A test device includes a semiconductor substrate having a first test region and a second test region defined thereon, wherein a layout of the first test region includes first active regions separated from each other by isolation regions in the semiconductor substrate, second active regions formed between the first active regions, first gate lines formed on the semiconductor substrate, wherein each of the first gate lines has a first end adjacent to one of the first active regions and a second end adjacent to an end of one of the second active regions, respectively, first shared contacts each formed over a respective one of the second ends of the first gate lines and an upper part of one of the first active regions, and first nodes formed on the first shared contacts to be electrically connected to the first shared contacts, respectively. | 07-26-2012 |
| 20120193621 | 3D SEMICONDUCTOR DEVICE - A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors. | 08-02-2012 |
| 20120193622 | DEVICE - A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge. | 08-02-2012 |
| 20120199829 | SEMICONDUCTOR DEVICE - A semiconductor device includes: plural devices to be measured; and a combined array wiring including plural unit array wirings each having a column wiring and a row wiring provided in different layers as well as each connected to any one of the plural devices to be measured, in which the plural unit array wirings are provided in layers different from each other. | 08-09-2012 |
| 20120199830 | Integrated Microelectronic Package Temperature Sensor - Temperatures in microelectronic integrated circuit packages and components may be measured in situ using carbon nanotube networks. An array of carbon nanotubes strung between upstanding structures may be used to measure local temperature. Because of the carbon nanotubes, a highly accurate temperature measurement may be achieved. In some cases, the carbon nanotubes and the upstanding structures may be secured to a substrate that is subsequently attached to a microelectronic package. | 08-09-2012 |
| 20120217497 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method for a semiconductor device includes: forming a test pattern with a metal film embedded therein through a plating process; detecting a characteristic of the test pattern; and adjusting a condition for the plating process based on the detected characteristic of the test pattern. The test pattern is formed over three or more wiring layers and includes a stacked via in an intermediate layer. | 08-30-2012 |
| 20120217498 | PHOTOELECTRIC CONVERTER AND METHOD FOR MANUFACTURING THE SAME - A photoelectric converter according to the present invention includes an insulating layer, a plurality of lower electrodes that are mutually spaced and disposed on the insulating layer, a photoabsorption layer made of a chalcopyrite compound semiconductor and formed to cover the plurality of lower electrodes all together, and a transparent conductive film formed to cover the photoabsorption layer. Variation of sensitivity among pixels due to influence (damage) by etching of the photoabsorption layer is thereby eliminated and a pixel aperture ratio can be made 100%. | 08-30-2012 |
| 20120223309 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 09-06-2012 |
| 20120228609 | TEST CIRCUIT FOR TESTING SIGNAL RECEIVING UNIT, IMAGE PICKUP APPARATUS, METHOD OF TESTING SIGNAL RECEIVING UNIT, AND METHOD OF TESTING IMAGE PICKUP APPARATUS - It is disclosed that, as an embodiment, a test circuit includes a test signal supply unit configured to supply a test signal via a signal line to signal receiving units provided in a plurality of columns, wherein the test signal supply unit is a voltage buffer or a current buffer, and the test circuit has a plurality of test signal supply units and a plurality of signal lines, and wherein at least one test signal supply unit is electrically connected to one signal line different from a signal line to which another test signal supply unit is electrically connected. | 09-13-2012 |
| 20120228610 | Display Panel - A display panel includes a plurality of pads configured to provide a driver thereon, a plurality of first contacts respectively connected to the plurality of pads, a plurality of second contacts respectively provided so as to be opposed to the plurality of first contacts, a polysilicon layer configured to form a plurality of polysilicon films that are respectively extended to connect the plurality of first contacts and the plurality of second contacts to each other, and a gate metal layer different from the polysilicon layer. Each of a plurality of transistors is formed at a position where the to gate metal layer traverses the polysilicon layer, and a plurality of transistor groups are arranged in a zigzag pattern. Each of the plurality of transistor groups include three adjacent transistors of the plurality of transistors. | 09-13-2012 |
| 20120235141 | SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed. | 09-20-2012 |
| 20120235142 | SEMICONDUCTOR LIGHT EMITTING DIODE CHIP, METHOD OF MANUFACTURING THEREOF AND METHOD FOR QUALITY CONTROL THEREOF - There are provided a semiconductor light emitting diode chip, a method of manufacturing thereof, and a method for quality control using the same. The semiconductor light emitting diode chip includes a substrate; a light emitting diode in one area of the substrate and at least one fuse signature circuit formed in the other area of substrate so as to be electrically insulated from the light emitting diode. The fuse signature circuit includes a circuit unit having unique electrical characteristic value corresponding to wafer based process information and a plurality of electrode pads connected to the circuit unit. The semiconductor light emitting diode chip may include chip information marking representing information. | 09-20-2012 |
| 20120248436 | REDUCED PATTERN LOADING FOR DOPED EPITAXIAL PROCESS AND SEMICONDUCTOR STRUCTURE - A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading. | 10-04-2012 |
| 20120248437 | Semiconductor Device And Test Method For Semiconductor Device - A semiconductor device includes a first metal pattern formed on a first metal level. The first metal pattern has a ‘U’ shaped first curved portion. A second metal pattern is formed on the first metal level. The second metal pattern has a ‘U’ shaped second curved portion facing the first curved portion. A via structure is electrically connected to one of the first metal pattern and the second metal pattern. A third metal pattern is formed on a second metal level different from the first metal level and electrically connected to the via structure. | 10-04-2012 |
| 20120248438 | FAULT-TOLERANT UNIT AND METHOD FOR THROUGH-SILICON VIA - A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV | 10-04-2012 |
| 20120248439 | SEMICONDUCTOR PACKAGES - Provided is a semiconductor package and a chip package of the same. The semiconductor package includes: a first semiconductor chip mounted on a first package substrate; a chip package stacked on the first semiconductor chip; and a first terminal connecting the chip package directly and electrically to the first semiconductor chip, wherein the chip package includes a second semiconductor chip mounted on a second package substrate, and the second package substrate includes a first pad coupled to the first terminal and a second pad electrically connected to the first pad and electrically spaced apart from the first terminal. | 10-04-2012 |
| 20120248440 | SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor module comprises a substrate, a first wiring, an electrode pad, a junction, an oscillator, and a detector. The first wiring is disposed on the substrate, and has a characteristic impedance Z | 10-04-2012 |
| 20120248441 | Space and Cost Efficient Incorporation of Specialized Input-Output Pins on Integrated Circuit Substrates - In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed. | 10-04-2012 |
| 20120256180 | METHOD OF EVALUATING A SEMICONDUCTOR WAFER DICING PROCESS - Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process. | 10-11-2012 |
| 20120261662 | INTEGRATED CIRCUIT WITH TEST CIRCUIT - An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer orprinted circuit board forming a portion of the test circuit. | 10-18-2012 |
| 20120261663 | DISPLAY PANEL AND METHOD OF MANUFACTURING DISPLAY PANEL - A display panel according to the present invention includes a first substrate including a first electrode portion and a connecting portion electrically connecting the first electrode portion to an external interconnection; a second substrate including a second electrode portion and disposed to face the first substrate; and a common transfer material electrically connecting the first electrode portion and the second electrode portion. The second electrode portion includes a detecting portion for detecting damage to the second substrate. The detecting portion is electrically connected to the first electrode portion and the external interconnection through the common transfer material. By the configuration as described above, it becomes possible to easily detect cracking, chipping and the like in the second substrate having no direct connection to the external interconnection. | 10-18-2012 |
| 20120267626 | Transmission Line Characterization Using EM Calibration - A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length. | 10-25-2012 |
| 20120273781 | Device and Method For RF Characterization of Nanostructures and High Impedance Devices - A method and device are provided for the RF characterization of nanostructures and high impedance devices. A two-terminal electronic nanostructure device is fabricated by dividing a length of a nanostructure into a plurality of shorter, identical nanostructures using a plurality of finger electrodes electrically connected in parallel. The nanostructure may include a single walled carbon nanotube subdivided into shorter identical copies of a metallic nanotube segment by situating multiple finger electrodes along the length of the single walled carbon nanotube. Each of the subdivided shorter nanotube segments are connected in parallel. This arrangement allows for close impedance matching to radio frequency (RF) systems, and serves as an important technique in understanding and characterizing metallic (and even semiconducting) nanotubes at RF and microwave frequencies. | 11-01-2012 |
| 20120273782 | INTERPOSERS OF 3-DIMENSIONAL INTEGRATED CIRCUIT PACKAGE SYSTEMS AND METHODS OF DESIGNING THE SAME - An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer. | 11-01-2012 |
| 20120273783 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another. | 11-01-2012 |
| 20120280231 | SEMICONDUCTOR DEVICE, AND TEST METHOD FOR SAME - It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop ( | 11-08-2012 |
| 20120286269 | CHIP DAMAGE DETECTION DEVICE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT - A chip damage detection device is provided that includes at least one bi-stable circuit having a first conductive line passing through an observed area of a semiconductor integrated circuit chip for damage monitoring of the observed area. The at least one bi-stable circuit is arranged to flip from a first stable state into a second stable state when a potential difference between a first end and a second end of the first conductive line changes or when a leakage current overdrives a state keeping current at the first conductive line. Further, a semiconductor integrated circuit device that includes the chip damage detection device and a safety critical system that includes the semiconductor integrated circuit device or the chip damage detection circuit is provided. | 11-15-2012 |
| 20120298992 | TEST LAYOUT STRUCTURE - A test layout structure includes a substrate, a first oxide region of a first height, a second oxide region of a second height, a plurality of border regions, and a test layout pattern. The first oxide region is disposed on the substrate. The second oxide region is also disposed on the substrate and adjacent to the first oxide region. The first height is substantially different from the second height. A plurality of border regions are disposed between the first oxide region and the second oxide region. The test layout pattern includes a plurality of individual sections. A test region is disposed between two of the adjacent individual sections which are parallel to each other. | 11-29-2012 |
| 20120298993 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including: a base material portion that includes a semiconductor substrate and an insulating film that is formed on one face of the semiconductor substrate and on which a vertical hole is formed along the thickness direction of the semiconductor substrate; a vertical hole wiring portion that includes a vertical hole electrode formed on a side wall of the base material portion that forms the vertical hole; a metallic film that is formed within the insulating film and that is electrically connected to the vertical hole wiring portion; and a conductive protective film that is formed to be in contact with the metallic film within the insulating film and that is formed in a region that includes a contact region of a probe during a probe test that is performed in the middle of manufacture on a film face of the metallic film. | 11-29-2012 |
| 20120298994 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a plurality of unit cells having a FET structure, this semiconductor device having: a gate electrode wiring connected electrically to gate electrode of the FET structure of each unit cell; a gate electrode pad connected electrically to the gate electrode wiring and connecting each gate electrode to an external element; and a probe electrode pad that is connected electrically to the gate electrode wiring and with which an inspection probe comes into contact. | 11-29-2012 |
| 20120305916 | Interposer Test Structures and Methods - An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads. | 12-06-2012 |
| 20120305917 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip that includes a driver circuit, a second semiconductor chip that includes a receiver circuit and an external terminal, and a plurality of through silicon vias that connect the first semiconductor chip and the second semiconductor chip. The first semiconductor chip further includes an output switching circuit that selectively connects the driver circuit to any one of the through silicon vias, the second semiconductor chip further includes an input switching circuit that selectively connects the receiver circuit to any one of the through silicon vias and the external terminal, the input switching circuit includes tri-state inverters each inserted between the receiver circuit and an associated one of the through silicon vias and the external terminal, and the input switching circuit activates any one of the tri-state inverters. | 12-06-2012 |
| 20120313094 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which uses a semiconductor substrate having a TEG pattern to reduce defects induced by dicing. The semiconductor device includes a semiconductor substrate which is to be or has been divided into individual semiconductor chips by dicing; an interlayer insulating layer formed over the semiconductor substrate; a seal ring provided in the interlayer insulating layer and formed along the periphery of the semiconductor chip; and a TEG wiring having one end coupled to the seal ring and the other end extending toward an end face of the periphery of the semiconductor chip. | 12-13-2012 |
| 20120319109 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads. | 12-20-2012 |
| 20120319110 | SEMICONDUCTOR STRUCTURE HAVING TEST AND TRANSISTOR STRUCTURES - A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading. | 12-20-2012 |
| 20120326146 | Sacrificial Wafer Probe Pads Through Seal Ring for Electrical Connection to Circuit Inside an Integrated Circuit - The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips. | 12-27-2012 |
| 20120326147 | SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE - Provided is a semiconductor chip in which a first rewiring connection part located in the peripheral electrode pad or relatively close to the peripheral electrode pad in the V/G line and a second rewiring connection part located relatively distant from the peripheral electrode pad in the V/G line and having a lower potential than the first rewiring connection part before formation of a rewiring line are connected by the rewiring line. The semiconductor chip includes an inspection part for wafer test in the second rewiring connection part, a part on the V/G line close to the second rewiring connection part and having a lower potential than the first rewiring connection part before the rewiring line formation, or a conductive part extended from the V/G line to a proximity of the second rewiring connection part and having a lower potential than the first rewiring connection part before the rewiring line formation. | 12-27-2012 |
| 20130001547 | METHOD FOR VERIFYING THE ALIGNMENT BETWEEN INTEGRATED ELECTRONIC DEVICES - A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals. | 01-03-2013 |
| 20130001548 | SEMICONDUCTOR APPARATUS AND STACKED SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal. | 01-03-2013 |
| 20130001549 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing of a semiconductor device according to an embodiment, an inspection transistor is subjected to silicidation and subsequently a characteristic of the inspection transistor is measured after the inspection transistor and a product transistor on a substrate are subjected to an annealing process. Thereafter, based on the measured characteristic, a characteristic adjustment annealing process to make a characteristic of the product transistor close to a desired characteristic is performed, and then the product transistor is subjected to silicidation. | 01-03-2013 |
| 20130001550 | HERMETICALLY SEALED MEMS DEVICE WITH A PORTION EXPOSED TO THE ENVIRONMENT WITH VERTICALLY INTEGRATED ELECTRONICS - A system and method for providing a MEMS device with integrated electronics are disclosed. The MEMS device comprises an integrated circuit substrate and a MEMS subassembly coupled to the integrated circuit substrate. The integrated circuit substrate includes at least one circuit coupled to at least one fixed electrode. The MEMS subassembly includes at least one standoff formed by a lithographic process, a flexible plate with a top surface and a bottom surface, and a MEMS electrode coupled to the flexible plate and electrically coupled to the at least one standoff. A force acting on the flexible plate causes a change in a gap between the MEMS electrode and the at least one fixed electrode. | 01-03-2013 |
| 20130001551 | PROBE RESISTANCE MEASUREMENT METHOD AND SEMICONDUCTOR DEVICE WITH PADS FOR PROBE RESISTANCE MEASUREMENT - A probe resistance measuring method includes measuring first resistances at three or more nodes by making contact at least a part of a plurality of probes of a probe unit with three or more pads for resistance measurement based on a first correspondence relation. The measured resistances are stored as a first measurement result and contact resistances of the plurality of probes of the probe unit are calculated based on the first measurement result. | 01-03-2013 |
| 20130001552 | TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS - A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks. | 01-03-2013 |
| 20130015440 | INTEGRATED CIRCUIT (IC) TEST PROBEAANM Dang; BingAACI ChappaquaAAST NYAACO USAAGP Dang; Bing Chappaqua NY USAANM Knickerbocker; John U.AACI MonroeAAST NYAACO USAAGP Knickerbocker; John U. Monroe NY USAANM Liu; YangAACI OSSININGAAST NYAACO USAAGP Liu; Yang OSSINING NY US - A test probe head for probing integrated circuit (IC) chips and method of making test heads. The test head includes an array of vias (e.g., annular vias or grouped rectangular vias) through, and exiting one surface of, a semiconductor layer, e.g., a silicon layer. The vias, individual test probe tips, may be on a pitch at or less than fifty microns (50 μm). The probe tips may be stiffened with SiO | 01-17-2013 |
| 20130020572 | Cap Chip and Reroute Layer for Stacked Microelectronic Module - A cap chip or high density reroute layer for use in a stacked microelectronic module. A first set of electrically conductive reroute layers are defined on a sacrificial substrate. One or more stud bump columns are defined on an exposed conducive pad on a conductive reroute layer. One or more active or passive electronic elements, or both may be electrically coupled to one or more exposed conductive pads. The layer is encapsulated in an encapsulant and the stud bump columns exposed by removing a portion of the encapsulant. A second set of electrically conductive reroute layers is defined on the layer and electrically coupled to the stud bumps. The sacrificial substrate is removed to provide a cap chip or reroute layer. | 01-24-2013 |
| 20130026464 | TEST PATTERN FOR MEASURING SEMICONDUCTOR ALLOYS USING X-RAY DIFFRACTION - A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other. | 01-31-2013 |
| 20130026465 | SEMICONDUCTOR DEVICE INCLUDING AN ASYMMETRIC FEATURE, AND METHOD OF MAKING THE SAME - A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact. | 01-31-2013 |
| 20130026466 | TESTING ARCHITECTURE OF CIRCUITS INTEGRATED ON A WAFER - An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits. | 01-31-2013 |
| 20130026467 | DUAL METAL FOR A BACKSIDE PACKAGE OF BACKSIDE ILLUMINATED IMAGE SENSOR - A method for fabricating a semiconductor device with improved bonding ability is disclosed. The method comprises providing a substrate having a front surface and a back surface; forming one or more sensor elements on the front surface of the substrate; forming one or more metallization layers over the front surface of the substrate, wherein forming a first metallization layer comprises forming a first conductive layer over the front surface of the substrate; removing the first conductive layer from a first region of the substrate; forming a second conductive layer over the front surface of the substrate; and removing portions of the second conductive layer from the first region and a second region of the substrate, wherein the first metallization layer in the first region comprises the second conductive layer and the first metallization layer in the second region comprises the first conductive layer and the second conductive layer. | 01-31-2013 |
| 20130032799 | Apparatus and Methods for De-Embedding Through Substrate Vias - A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs. | 02-07-2013 |
| 20130032800 | SEMICONDUCTOR DEVICE - A semiconductor device includes a circuit board including a ground portion, and a semiconductor package disposed on the circuit board. The semiconductor package includes an external connecting pad and an exposed pad. The exposed pad and the ground portion are electrically connected at a first surface of the exposed pad. A semiconductor chip is disposed on a second surface of the exposed pad and electrically connected to the external connecting pad. The first surface of the exposed pad is located external to the semiconductor package, and the second surface of the exposed pad is located within the semiconductor package. A test pad is disposed on the semiconductor chip and is electrically connected to the exposed pad. | 02-07-2013 |
| 20130037802 | SEMICONDUCTOR DIE ASSEMBLIES, SEMICONDUCTOR DEVICES INCLUDING SAME, AND METHODS OF FABRICATION - Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies. | 02-14-2013 |
| 20130037803 | MONITORING PAD AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A method of manufacturing a semiconductor device and a semiconductor device package are disclosed. A method of manufacturing a semiconductor device comprises the steps of testing the semiconductor device using at least a first monitoring pad connected to an internal circuit of the semiconductor device via at least a first fuse circuit; after testing the semiconductor device, electrically disconnecting the first monitoring pad from the internal circuit by opening the first fuse circuit; and after testing of the semiconductor device, electrically connecting at least a first auxiliary pad to the first monitoring pad with at least a first connecting terminal, wherein the first auxiliary pad is connected, through at least a first conductive line, to at least a first power pad of the semiconductor device. | 02-14-2013 |
| 20130043470 | CRACK STOP STRUCTURE AND METHOD FOR FORMING THE SAME - The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure. | 02-21-2013 |
| 20130048981 | ELECTRICALLY MEASURABLE ON-CHIP IC SERIAL IDENTIFIER AND METHODS FOR PRODUCING THE SAME - An apparatus comprising an integrated circuit, an interconnect layer within said integrated circuit, and one or more connections. The integrated circuit may be configured to provide an electrically measurable interconnect pattern by enabling one or more of a plurality of components. The one or more connections may each configured to enable a respective one of the components. The connections may be programmable while the apparatus is part of a wafer. The interconnect pattern may be configured to identify the apparatus after the apparatus has been manufactured. | 02-28-2013 |
| 20130048982 | BOND PAD MONITORING STRUCTURE AND RELATED METHOD OF DETECTING SIGNIFICANT ALTERATIONS - A passive bond pad condition sense structure may be configured to be electrically stimulated and tested for detecting an anomalous or altered electrical characteristic caused by stress or aging of the bond pad capacitively coupled to it. The related bond pad condition testing or monitoring system may include relatively simple stimulating and sensing circuits that may be wholly embedded in the integrated circuit device. | 02-28-2013 |
| 20130056730 | SEMICONDUCTOR DEVICE - A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line. | 03-07-2013 |
| 20130062603 | TEST STRUCTURE AND CALIBRATION METHOD - A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window. | 03-14-2013 |
| 20130062604 | Photodetector with Controllable Spectral Response - A photodetector includes a semiconductor substrate having an irradiation zone configured to generate charge carriers having opposite charge carrier types in response to an irradiation of the semiconductor substrate. The photodetector further includes an inversion zone generator configured to operate in at least two operating states to generate different inversion zones within the substrate, wherein a first inversion zone generated in a first operating state differs from a second inversion zone generated in a second operating state, and wherein the first inversion zone and the second inversion zone have different extensions in the semiconductor substrate. A corresponding method for manufacturing a photodetector and a method for determining a spectral characteristic of an irradiation are also described. | 03-14-2013 |
| 20130062605 | SEMICONDUCTOR CHIP - In a case where a semiconductor chip is mounted over a first package, 80 pads are coupled to 80 terminals of the package, and in a case where the semiconductor chip is mounted over a second package, 100 pads are coupled to 100 terminals of the second package. An internal circuit of the semiconductor chip operates as a microcomputer with 80 terminals in a case where electrodes are insulated from each other and operates as a microcomputer with 100 terminals in a case where the electrodes are shorted therebetween by an end part of a bonding wire. Therefore, a dedicated pad for setting the number of terminals of the packages is no longer required. | 03-14-2013 |
| 20130069062 | LEAKAGE MEASUREMENT OF THROUGH SILICON VIAS - A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate having a plurality of through substrate vias for current leakage. | 03-21-2013 |
| 20130069063 | INTEGRATED CIRCUIT SYSTEM WITH TEST PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate having a test pad with element pads; forming a conductive layer over the test pad, the conductive layer having element layers directly on the element pads; and mounting an integrated circuit over the substrate. | 03-21-2013 |
| 20130075724 | SEMICONDUCTOR ARRANGEMENT WITH AN INTEGRATED HALL SENSOR - A semiconductor arrangement includes a semiconductor body and a semiconductor device, the semiconductor device including first and second load terminals arranged distant to each other in a first direction of the semiconductor body and a load path arranged in the semiconductor body between the first and second load terminals. The semiconductor arrangement further includes at least one Hall sensor arranged in the semiconductor body distant to the semiconductor device in a second direction perpendicular to the first direction. The Hall sensor includes two current supply terminals and two measurement terminals. | 03-28-2013 |
| 20130075725 | ENHANCED WAFER TEST LINE STRUCTURE - A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process. | 03-28-2013 |
| 20130075726 | PROTECTION METHOD FOR AN ELECTRONIC DEVICE AND CORRESPONDING DEVICE - The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide. | 03-28-2013 |
| 20130075727 | SEMICONDUCTOR DEVICE - Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region. | 03-28-2013 |
| 20130082257 | VIA CHAINS FOR DEFECT LOCALIZATION - Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing. | 04-04-2013 |
| 20130082258 | METHOD FOR STRIP TESTING OF MEMS DEVICES, TESTING STRIP OF MEMS DEVICES AND MEMS DEVICE THEREOF - A method for testing a strip of MEMS devices, the MEMS devices including at least a respective die of semiconductor material coupled to an internal surface of a common substrate and covered by a protection material; the method envisages: detecting electrical values generated by the MEMS devices in response to at least a testing stimulus; and, before the step of detecting, at least partially separating contiguous MEMS devices in the strip. The step of separating includes defining a separation trench between the contiguous MEMS devices, the separation trench extending through the whole thickness of the protection material and through a surface portion of the substrate, starting from the internal surface of the substrate. | 04-04-2013 |
| 20130082259 | TEST CARRIER - A test carrier which can suppress the occurrence of contact defects while securing positional precision of the terminals is provided. A test carrier | 04-04-2013 |
| 20130082260 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INSPECTION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Integrated circuit layers to be stacked on top of each other are formed with a plurality of inspection rectifier device units, respectively. The plurality of inspection rectifier device units including rectifier devices are connected between a plurality of connection terminals and a positive power supply lead and a grounding lead and emit light in response to a current. After electrically connecting the plurality of connection terminals to each other, a bias voltage is applied between the positive power supply lead and the grounding lead, and the connection state between the connection terminals is inspected according to a light emission of the inspection rectifier device unit. This makes it possible to inspect, in a short time every time a layer is stacked, whether or not an interlayer connection failure exists in a semiconductor integrated circuit device constructed by stacking a plurality of integrated circuit layers in their thickness direction. | 04-04-2013 |
| 20130087787 | ELECTRICAL MASK INSPECTION - An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain. | 04-11-2013 |
| 20130087788 | DETECTION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Integrated circuit layers to be stacked on top of each other are formed with a plurality of inspection rectifier device units, respectively. The inspection rectifier device units including rectifier devices are connected between a plurality of connection terminals and a positive power supply lead and a grounding lead and emit light in response to a current. After electrically connecting the plurality of connection terminals to each other, a bias voltage is applied between the positive power supply lead and the grounding lead, and the connection state between the connection terminals is inspected according to a light emission of the inspection rectifier device unit. This makes it possible to inspect, in a short time every time a layer is stacked, whether or not an interlayer connection failure exists in a semiconductor integrated circuit device constructed by stacking a plurality of integrated circuit layers in their thickness direction. | 04-11-2013 |
| 20130092935 | Probe Pad Design for 3DIC Package Yield Analysis - An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad. | 04-18-2013 |
| 20130092936 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal. | 04-18-2013 |
| 20130092937 | DISPLAY DEVICE - A display device according to an exemplary embodiment of the present invention includes a display portion including a plurality of display pixels displaying an image and a dummy portion including a plurality of dummy pixels formed in a periphery region of the display portion. An electrostatic test element group (TEG) may be formed in at least one of the dummy pixels. | 04-18-2013 |
| 20130092938 | SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE - A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling. | 04-18-2013 |
| 20130099235 | SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING STACK PACKAGE USING THE SAME - A semiconductor wafer includes a plurality of semiconductor chips having bonding pads; and a connection wiring line coupling the plurality of semiconductor chips such that a test signal, which is inputted through bonding pads of an arbitrary semiconductor chip among the plurality of semiconductor chips, is transmitted to bonding pads of other semiconductor chips among the plurality of semiconductor chips. | 04-25-2013 |
| 20130112974 | METHOD FOR DETERMINING THE LOCAL STRESS INDUCED IN A SEMICONDUCTOR MATERIAL WAFER BY THROUGH VIAS - A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer. | 05-09-2013 |
| 20130119382 | Plating Process and Structure - A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed. | 05-16-2013 |
| 20130126865 | GRAPHENE EPITAXIED ON SIC, WITH AN OPEN BAND GAP AND MOBILITY COMPARABLE TO STANDARD GRAPHENE WITH ZERO BAND GAP - A method of manufacturing a modified structure comprising a semiconducting modified graphene layer on a substrate, comprising the subsequent following steps: supply of an initial structure comprising at least one substrate, formation of a graphene layer on the substrate, hydrogenation of the initial structure by exposure to atomic hydrogen, characterised in that the hydrogenation step of the graphene layer is done with an exposure dose between 100 and 4000 Langmuirs, and forms a modified graphene layer. | 05-23-2013 |
| 20130126866 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in one embodiment includes a wiring board having a wiring pattern; an N semiconductor elements(where N denotes a natural number equal to or greater than 2) mounted on a wiring board; and a current detection parts for detecting a current flowing through m semiconductor elements (where m denotes a natural number equal to or greater than 1 but less than M) of M semiconductor elements(where M denotes a natural number equal to or greater than 1 but equal to or less than N) mounted on the wiring board and selected from the N semiconductor elements. The M semiconductor elements are electrically connected in parallel through the wiring pattern, and the m semiconductor elements are electrically connected in parallel to the other semiconductor elements of the M semiconductor elements through the current detection part. | 05-23-2013 |
| 20130134421 | SEMICONDUCTOR CHIP HAVING PLURAL PENETRATING ELECTRODES THAT PENETRATE THERETHROUGH - Disclosed herein is a semiconductor chip that includes: a semiconductor chip body including a semiconductor substrate and a circuit element layer provided on a main surface of the semiconductor substrate, the circuit element layer including a plurality of circuit elements; first to fourth penetrating electrodes penetrating the semiconductor chip body; a first conductive path electrically connected between the first penetrating electrode and the second penetrating electrode without being in contact with any one of the circuit elements; a second conductive path electrically connected between the first penetrating electrode and the third penetrating electrode without being in contact with any one of the circuit elements; and a third conductive path electrically connected between the second penetrating electrode and the fourth penetrating electrode without being in contact with any one of the circuit elements. | 05-30-2013 |
| 20130140563 | Plating Process and Structure - A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. | 06-06-2013 |
| 20130140564 | Electrical Test Structure for Devices Employing High-K Dielectrics or Metal Gates - Disclosed herein are various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures. In one example, the test structure disclosed herein includes a first line formed over an isolation material, a first active region defined in a semiconducting substrate and a first extension formed over an isolation material, the first extension extending from a first side of the first line, wherein the first extension is positioned proximate the first active region and wherein the first line and the first extension are comprised of at least one of a high-k layer of insulating material or a metal layer. | 06-06-2013 |
| 20130140565 | TEST STRUCTURE FOR DETECTION OF GAP IN CONDUCTIVE LAYER OF MULTILAYER GATE STACK - A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer. | 06-06-2013 |
| 20130146872 | Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate - A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer. A substrate has bump material deposited over a conductive layer formed over a surface of the substrate. The bump material is melted. The semiconductor die is pressed toward the substrate to enable the melted bump material to flow into the recess or over the protrusion if the conductive pillar makes connection to the conductive layer. A presence or absence of the bump material in the recess or protrusion of the conductive pillar is detected by X-ray or visual inspection. | 06-13-2013 |
| 20130146873 | Integrated Mechanical Device for Electrical Switching - An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations. | 06-13-2013 |
| 20130146874 | SEMICONDUCTOR INTEGRATED CIRCUIT - There is offered a semiconductor integrated circuit provided with a function to electrically identify a location where a defect such as chipping of an LSI die or separation of resin is caused. Corresponding to each of the four corners of a semiconductor substrate, each of L-shaped first through fourth peripheral wirings having a first end and a second end is disposed on a periphery of the semiconductor substrate. The first end of each of the first through fourth peripheral wirings is connected with a power supply wiring. Each of first through fourth detection circuits detects breaking of corresponding each of the first through fourth peripheral wirings in response to a voltage at the second end of corresponding each of the first through fourth peripheral wirings, and outputs corresponding each of first through fourth detection signals to corresponding each of output pads. | 06-13-2013 |
| 20130153896 | SCAN TESTABLE THROUGH SILICON VIAs - The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs. | 06-20-2013 |
| 20130153897 | POWER BIPOLAR STRUCTURE, IN PARTICULAR FOR HIGH VOLTAGE APPLICATIONS - A power bipolar structure is described having at least one first, one second and one third terminal and including at least one power bipolar transistor having a finger structure coupled to at least one driving block. The power bipolar transistor includes at least one elemental bipolar cell connected to these first, second and third terminals and including at least one power elemental bipolar structure corresponding to a finger of the power bipolar transistor, electrically coupled between the first and second terminals and coupled to a driving section of the driving block by at least one sensing section able to detect information on the operation of the power elemental bipolar structure, the sensing section being in turn coupled to a control circuit and supplying it with a current value as a function of the local temperature of the power elemental bipolar structure. | 06-20-2013 |
| 20130153898 | SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIP STACKED WITH ONE ANOTHER - Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal. | 06-20-2013 |
| 20130153899 | SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS - Disclosed herein is a device that including a first chip having first to fourth terminals and a second chip having fifth to seventh terminals. The first chip further includes a penetration electrode connected between the first and fourth electrodes and a first internal node coupled to of which an electrical potential being changed in response to an electrical potential of the first terminal. The second chip further includes a second internal node coupled to of which an electrical potential being changed in response to an electrical potential of the fifth terminal. The first internal node is electrically coupled to both the second terminal and the sixth terminal. The second internal node is electrically coupled to both the third terminal and the seventh terminal. | 06-20-2013 |
| 20130153900 | SEMICONDUCTOR DEVICE - A semiconductor device capable of rapidly and accurately sensing the information regarding the temperature of a semiconductor transistor contained therein. A MOSFET includes a plurality of cells, and includes a main cell group including a cell for supplying a current to a load among the plurality of cells, and a sense cell group including a cell for sensing temperature information regarding the temperature of the MOSFET thereamong. The main cell group and the sense cell group have different temperature characteristics showing changes in electrical characteristics to changes in temperature. A temperature sensing circuit senses the temperature of the MOSFET based on, for example, a value of a main current flowing through the main cell group and a value of a sense current flowing through the sense cell group. | 06-20-2013 |
| 20130161615 | MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS - A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure. | 06-27-2013 |
| 20130161616 | Substrate for Chip on Film - The present invention discloses a substrate including a flexible film, a plurality of sprocket holes disposed along a first direction on two sides of the flexible film, and a plurality of first chip zones disposed along the first direction on the flexible film, of which each first chip zone includes at least a testing module, an input module, a chip and an output module disposed along a second direction, where the first direction is orthogonal to the second direction. | 06-27-2013 |
| 20130161617 | METHOD FOR MEASURING IMPURITY CONCENTRATION PROFILE, WAFER USED FOR SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME - According to an embodiment, a method for measuring an impurity concentration profile uses a wafer including a semiconductor layer. The method includes measuring an impurity concentration profile in a depth direction from each surface of a plurality of first portions, each of the first portions being included in any one of a plurality of first regions provided in the semiconductor layer. Each of the first regions has a different size and is surrounded by a second region including a second portion having a different structure from the first portion. The method includes determining a change between the impurity concentration profiles measured in the first regions. | 06-27-2013 |
| 20130168672 | Multichip Module with Reroutable Inter-Die Communication - A multichip module (MCM) has redundant I/O connections between its dice. That is, the number of inter-die I/O connections used is larger than the number of connections ordinarily used to provide connectivity between the dice. Defective connections are discovered through testing after MCM assembly and avoided, with signals being rerouted through good (e.g., not defective) redundant connections. The testing can be done at assembly time and the results stored in nonvolatile memory. Alternatively, the MCM can perform the testing itself dynamically, e.g., at power up, and use the test results to configure the inter-die I/O connections. | 07-04-2013 |
| 20130168673 | Intra Die Variation Monitor Using Through-Silicon Via - An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area. | 07-04-2013 |
| 20130168674 | Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated Circuits - A three-dimensional integrated circuit (3D-IC) includes a stack of semiconductor wafers, each of which includes a substrate and a device layer. Programmable components, such as memory arrays or logic circuits, are formed within the device layers. Some of the programmable components are redundant, and can be substituted for defective components by programming passive memory elements in a separate conductive layer provided for this purpose. The separate conductive layer is devoid of active devices, and is therefore relatively reliable and inexpensive. | 07-04-2013 |
| 20130168675 | Detection and Mitigation of Particle Contaminants in MEMS Devices - Detecting and/or mitigating the presence of particle contaminants in a MEMS device involves including MEMS structures that in normal operation are robust against the presence of particles but which can be made sensitive to that presence during a test mode prior to use, e.g., by switching the impedance of sensitive structures between an exceptionally sensitive condition during test and a normal sensitivity during operation; surrounding sensitive nodes with guard elements that are at the same potential as those nodes during operation, thereby offering protection against bridging particles, but are at a very different potential during test and reveal the particles by their resulting leakage currents; extending the sensitive nodes to interdigitate with or otherwise extend adjacent to the guard structures, which neither contribute to nor detract from the device operation but cover otherwise open areas with detection means during test; and/or converting benign areas in which particles might become trapped undetectably by electric fields during test to field-free regions by extending otherwise non-functional conductive layers so that the particles can then be moved into detection locations by providing some mechanical disturbance. | 07-04-2013 |
| 20130175527 | SENSOR ARRANGEMENT, A MEASUREMENT CIRCUIT, CHIP-PACKAGES AND A METHOD FOR FORMING A SENSOR ARRANGEMENT - A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region. | 07-11-2013 |
| 20130175528 | CHIP ON FILM PACKAGE INCLUDING TEST PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern. | 07-11-2013 |
| 20130181219 | SEMICONDUCTOR GROWTH SUBSTRATES AND ASSOCIATED SYSTEMS AND METHODS FOR DIE SINGULATION - Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street. | 07-18-2013 |
| 20130181220 | METHOD FOR ESTIMATING THE DIFFUSION LENGTH OF METALLIC SPECIES WITHIN A THREE-DIMENSIONAL INTEGRATED STRUCTURE, AND CORRESPONDING THREE-DIMENSIONAL INTEGRATED STRUCTURE - A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations. | 07-18-2013 |
| 20130187156 | THREE DIMENSIONAL INTEGRATED CIRCUIT HAVING A RESISTANCE MEASURMENT STRUCTURE AND METHOD OF USE - A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors. | 07-25-2013 |
| 20130187157 | METHODS OF HEATING INTEGRATED CIRCUITS AT LOW TEMPERATURES AND DEVICES USING THE METHODS - A method of heating an integrated circuit (IC) may include sensing a temperature of the IC, comparing the sensed temperature with a reference temperature and generating a comparison signal; and enabling a heating element that heats the IC based on the comparison signal. An IC may include a thermal sensor configured to sense a temperature of the IC, compare the sensed temperature with a reference temperature, and generate a comparison signal. The IC may include a heating element configured to be enabled to heat the IC based on the comparison signal. An IC may include a heating element and a thermal sensor. The sensor may be configured to sense a temperature of the IC and generate a control signal based on the sensed temperature and a reference temperature. The element may be enabled to heat the IC or disabled from heating the IC based on the control signal. | 07-25-2013 |
| 20130187158 | SEMICONDUCTOR DEVICE - The invention prevents a short circuit between bonding wires, between device pads, or between the bonding wire and the device pad due to a cut residue portion of a scribe TEG pad coming off from an end portion of a semiconductor chip. A scribe TEG pad on a semiconductor wafer is formed of a plurality of rectangular pads each extending on a scribe line toward a device forming region. The semiconductor wafer is divided into semiconductor chips by dicing. At this time, the length of each of cut residue portions of the scribe TEG pad remaining on an end portion of the semiconductor chip is shorter than an interval between the end portions of openings of a passivation film on adjacent device pads. | 07-25-2013 |
| 20130193437 | DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST BACK SIDE ATTACKS - An integrated circuit including: a semiconductor substrate of a first conductivity type having at least one well of a second conductivity type laterally delimited, on two opposite walls, by regions of the first conductivity type, defined at its surface; at least one region of the second conductivity type which extends in the semiconductor substrate under the well; and a system for detecting a variation of the substrate resistance between each association of two adjacent regions of the first conductivity type. | 08-01-2013 |
| 20130193438 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. | 08-01-2013 |
| 20130200371 | DEVICE FOR DETECTING A LASER ATTACK IN AN INTEGRATED CIRCUIT CHIP - A device for detecting a laser attack in an integrated circuit chip formed in the upper P-type portion of a semiconductor substrate incorporating an NPN bipolar transistor having an N-type buried layer, including a detector of the variations of the current flowing between the base of said NPN bipolar transistor and the substrate. | 08-08-2013 |
| 20130207107 | METHODS OF OF IMPROVING BUMP ALLOCATION FOR SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES WITH IMPROVED BUMP ALLOCATION - In a method of improving bump allocation for a semiconductor device and a semiconductor device with improved bump allocation, a predetermined signal bump is surrounded with at least three bumps, each being a ground bump or a paired differential signal bump. | 08-15-2013 |
| 20130207108 | Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques - An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure. | 08-15-2013 |
| 20130214274 | Integrated Circuit and Manufacturing Method - Disclosed is an integrated circuit comprising a substrate ( | 08-22-2013 |
| 20130221353 | Methods and Apparatus for Testing Pads on Wafers - Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer. | 08-29-2013 |
| 20130221354 | FLIP CHIP SEMICONDUCTOR DIE INTERNAL SIGNAL ACCESS SYSTEM AND METHOD - A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point. | 08-29-2013 |
| 20130221355 | STRUCTURES AND METHODS FOR TESTING PRINTABLE INTEGRATED CIRCUITS - A substrate includes an anchor area ( | 08-29-2013 |
| 20130228778 | Methods of Extracting Fin Heights and Overlap Capacitance and Structures for Performing the Same - A first test structure includes a first isolation region, a first gate electrode over the first isolation region, a first and a second semiconductor fin, and a first contact plug over the first and the second semiconductor fins. A second test structure includes a second isolation region, a second gate electrode over the second isolation region, a third semiconductor fin and a dielectric fin, and a second contact plug over the third semiconductor fin. The first, the second, and the third semiconductor fins and the dielectric fin have substantially a same fin height. A method includes measuring a first capacitance between the first gate electrode and the first contact plug, measuring a second capacitance between the second gate electrode and the second contact plug, and calculating the same fin height from a capacitance difference between the second capacitance and the first capacitance. | 09-05-2013 |
| 20130234138 | ELECTRICAL TEST STRUCTURE FOR DETERMINING LOSS OF HIGH-K DIELECTRIC MATERIAL AND/OR METAL GATE MATERIAL - Disclosed herein are various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures. In one example, the test structure disclosed herein includes a first resistor comprised of at least one of a high-k layer of insulating material or a metal layer and a silicon-containing material layer and first and second spaced-apart metal silicide regions formed on the silicon-containing material layer, wherein the silicon-containing layer further comprises a non-silicided region positioned between the first and second spaced-apart metal silicide regions. | 09-12-2013 |
| 20130234139 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of stacked slices each configured to have a plurality of vias formed therein so that signals are transferred between the slices arranged in a vertical direction, wherein each of the plurality of slices is configured to transfer a pulse signal, generated during a test section, to a lowest slice of the plurality of slices through the vias connected thereto. | 09-12-2013 |
| 20130234140 | MICROMECHANICAL COMPONENT HAVING A DIAPHRAGM - Measures are described with the aid of which not only a rupture, but also cracks may be detected in the diaphragm structure of a micromechanical component with the aid of circuit means integrated into the diaphragm structure. At least some circuit elements are integrated for this purpose into the bottom side of the diaphragm, i.e., into a diaphragm area directly adjoining the cavern below the diaphragm. | 09-12-2013 |
| 20130240882 | DIE, WAFER AND METHOD OF PROCESSING A WAFER - A die in accordance with various embodiments may include a metallization area located proximate an edge of the die, and an electrical connection connected to the metallization area and running from the metallization area to the edge, wherein the electrical connection is free from metal. A wafer in accordance with various embodiments may include a die region having a metallization area, a kerf region having an electric or electronic device, and an electrical connection connecting the electric or electronic device with the metallization area, wherein the electrical connection is free from metal. | 09-19-2013 |
| 20130240883 | Contact Test Structure and Method - A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together. | 09-19-2013 |
| 20130240884 | DETECTION OF ENVIRONMENTAL CONDITIONS IN A SEMICONDUCTOR CHIP - A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip. | 09-19-2013 |
| 20130248859 | Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration - A semiconductor device has a substrate and conductive layer over the substrate. A resistive element is formed between first and second portions of the conductive layer. A plurality of semiconductor die each with first and second bumps is mounted to the substrate with the first and second bumps electrically connected to the first and second portions of the conductive layer. A test current is routed in sequence through the first portion of the conductive layer, through the first and second bumps, and through the second portion of the conductive layer until continuity failure of the second bump. The test current originates from a single power supply. The test current continues to flow through the resistive element after the continuity failure of the second bump. The continuity failure can be detected by sensing an increase in voltage across the second bump. | 09-26-2013 |
| 20130248860 | BUNDLED MEMORY AND MANUFACTURE METHOD FOR A BUNDLED MEMORY WITH AN EXTERNAL INPUT/OUTPUT BUS - A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus. | 09-26-2013 |
| 20130248861 | Integrated Power Transistor Circuit Having a Current-Measuring Cell - An integrated power transistor circuit includes a contact structure with a first section and a second section. The first section contacts doped regions of transistor cells in a cell array. The second section includes one or more first subsections which adjoin the first section and extend beyond the cell array in the region of selected transistor cells. A second subsection adjoins the one or more first subsections and forms a tapping line, for example for making contact with source regions of power transistor cells. In the region of the cell array, an electrode structure rests on the contact structure. This electrode structure is absent over the second section. The tapping line can thus be formed at a short distance from the electrode structure, with the result that the active chip area is only insubstantially reduced by the tapping line. | 09-26-2013 |
| 20130248862 | SOLID-STATE IMAGE SENSING DEVICE AND CAMERA - According to one embodiment, a solid-state image sensing device includes a semiconductor substrate having a first and second surface, an insulating film covering an element on the first surface, a pixel array including pixels configured to photoelectrically convert light applied on the side of the second surface, contact regions in the semiconductor substrate, one or more through-electrodes respectively provided in the contact regions, and first pads provided on the side of the second surface to correspond to the respective contact regions. The first pad extends in a first direction from the contact regions toward the pixel array. | 09-26-2013 |
| 20130248863 | CHIP PACKAGING SUBSTRATE AND CHIP PACKAGING STRUCTURE - A chip packaging substrate includes a flexible substrate, a plurality of test pads, and a plurality of leads, wherein the flexible substrate has a first surface and a second surface, and the first surface has a user area and a test pad area configured thereon. The test pads are arranged in at least three rows within the test pad area. The lead connected to the test pad in the middle row includes a first section extending from the chip to the test pad area and a second section disposed on the second surface, wherein one end of the second section penetrates the flexible substrate to connect with the first section and the other end penetrates the flexible substrate to connect with the test pad, so as to increase the dimensions of the test pads. | 09-26-2013 |
| 20130248864 | DIE TESTING USING TOP SURFACE TEST PADS - Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size. | 09-26-2013 |
| 20130256659 | REDUCTION OF OCD MEASUREMENT NOISE BY WAY OF METAL VIA SLOTS - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches. | 10-03-2013 |
| 20130256660 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment has: a semiconductor substrate; an acoustic resonator formed on the semiconductor substrate, having a semiconductor layer including impurity electrically isolated from the substrate by depletion layer and configured to resonate at a predetermined resonance frequency based on acoustic standing wave excited in the semiconductor layer; a temperature detector formed on the semiconductor substrate and configured to detect temperature of the semiconductor substrate; a calculating unit formed on the semiconductor substrate and configured to perform calculation of temperature compensation based on the temperature detected by the temperature detector, kind of the impurity and concentration of the impurity; and a controller formed on the semiconductor substrate and configured to control the resonance frequency based on a result of the calculation by the calculating unit. | 10-03-2013 |
| 20130256661 | SYSTEM FOR ELECTRICAL TESTING OF THROUGH-SILICON VIAS (TSVs), AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of a process for manufacturing a system for electrical testing of a through via extending in a vertical direction through a substrate of semiconductor material envisages integrating an electrical testing circuit in the body to enable detection of at least one electrical parameter of the through via through a microelectronic buried structure defining an electrical path between electrical-connection elements towards the outside and a buried end of the through via; the integration step envisages providing a trench and forming a doped buried region at the bottom of the trench, having a doping opposite to that of the substrate so as to form a semiconductor junction, defining the electrical path when it is forward biased; in particular, the semiconductor junction has a junction area smaller than the area of a surface of the conductive region in a horizontal plane transverse to the vertical direction, in such a way as to have a reduced reverse saturation current. | 10-03-2013 |
| 20130270557 | TEST STRUCTURE FOR SEMICONDUCTOR PROCESS AND METHOD FOR MONITORING SEMICONDUCTOR PROCESS - A monitoring method of a semiconductor process includes the following steps. A semiconductor substrate is provided, and a test structure is formed thereon. The method of forming the test structure includes the following steps. A first doped region and a second doped region are formed in the semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. Subsequently, a conductive layer is directly formed on the insulating layer to complete the formation of the test structure, in which the conductive layer in a floating state partially overlaps the first doped region and partially overlaps the second doped region. Then, a voltage signal is applied to the test structure and the breakdown voltage (Vbd) between the first doped region and the second doped region is measured. | 10-17-2013 |
| 20130270558 | SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS - A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package. | 10-17-2013 |
| 20130277674 | DISPLAY PANEL - A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line. | 10-24-2013 |
| 20130285055 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion. | 10-31-2013 |
| 20130285056 | SEMICONDUCTOR STRUCTURE WITH LOW-MELTING-TEMPERATURE CONDUCTIVE REGIONS, AND METHOD OF REPAIRING A SEMICONDUCTOR STRUCTURE - A semiconductor structure includes at least a semiconductor body, a delimiting structure delimiting a cup-shaped recess in the body and a conductive region in the recess. The conductive region is made of a low-melting-temperature material, having a melting temperature lower than that of the materials forming the delimiting structure. | 10-31-2013 |
| 20130285057 | SEMICONDUCTOR DEVICE - Increase in the chip size of a semiconductor device is suppressed. The semiconductor device includes: circuit vias provided in an interlayer insulating film between upper and lower wiring layers and coupling these wiring layers together; a planar ring-shaped protecting via that is provided in the interlayer insulating film under an electrode pad and one side of which is coupled with the electrode pad; a protecting wiring layer comprised of a wiring layer coupled only with the other side of the protecting via; and a semiconductor element provided over the principal surface of a semiconductor substrate under the protecting wiring layer. The lower part of the electrode pad whose surface is exposed is encircled with the protecting via and the protecting wiring layer. The width of the protecting via is equal to or larger than the width of each circuit via. | 10-31-2013 |
| 20130292673 | Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure - A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer. | 11-07-2013 |
| 20130299828 | VIA CHAINS FOR DEFECT LOCALIZATION - Via chain and serpentine/comb test structures are in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. | 11-14-2013 |
| 20130306967 | ADJUSTING CONFIGURATION OF A MULTIPLE GATE TRANSISTOR BY CONTROLLING INDIVIDUAL FINS - In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices. | 11-21-2013 |
| 20130320340 | CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS - A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed. | 12-05-2013 |
| 20130320341 | Three dimensional memory structure - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 12-05-2013 |
| 20130328046 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement. | 12-12-2013 |
| 20130334531 | SYSTEMS AND METHODS FOR MEASURING TEMPERATURE AND CURRENT IN INTEGRATED CIRCUIT DEVICES - Embodiments relate to measurement of temperature and current in semiconductor devices. In particular, embodiments relate to monolithic semiconductor, such as power semiconductor, and sensor, such as a current or temperature sensor, device. In embodiments, temperature and/or current sensing features are monolithically integrated within semiconductor devices. These embodiments thereby can provide direct measurement of temperature and current, in contrast with conventional solutions that provide temperature and current sensing near or alongside but not integrated within the actual semiconductor device. For example, in one embodiment an additional layer structure is applied to a power semiconductor stack in backend processing. This monolithic integration provides for localized measurement of temperature and/or current, an advantage over conventional side-by-side configurations. | 12-19-2013 |
| 20130334532 | STRESS GAUGE COMPRISED OF A PIEZOELECTRIC MATERIAL FOR USE WITH INTEGRATED CIRCUIT PRODUCTS - In one example, a stress gauge for an integrated circuit product is disclosed that includes a layer of insulating material, a body positioned at least partially in the layer of insulating material, wherein the body is comprised of a material having a piezoelectric constant of at least about 0.1 pm/V, and a plurality of spaced apart conductive contacts, each of which is conductively coupled to the body. | 12-19-2013 |
| 20130341620 | Monitor Structures and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening. | 12-26-2013 |
| 20140001471 | CONFORMAL SHIELDING MODULE | 01-02-2014 |
| 20140001472 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME | 01-02-2014 |
| 20140014957 | SEMICONDUCTOR DEVICE INCLUDING A STRUCTURE FOR SCREENING CONNECTIVITY OF A TSV - A semiconductor device is provided to check through silicon via (TSV) connectivity at a wafer level. The semiconductor device includes a first metal layer formed over a through silicon via (TSV), a second metal layer and a third metal layer formed at both sides of the first metal layer to be electrically coupled to the TSV, and a fourth metal layer formed over the first metal layer to be electrically coupled to the first metal layer. | 01-16-2014 |
| 20140014958 | SEMICONDUCTOR CHIP MODULE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines. | 01-16-2014 |
| 20140014959 | PASSIVATION LAYER FOR PACKAGED CHIP - A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first passivation layer over a portion of the testing pad, and a second passivation layer covering a surface of the testing pad and a portion of the first passivation layer surrounding the testing region of the testing pad. A distance between edges of the second passivation layer covering the surface of the testing pad to edges of the testing pad is in a range from about 2 mm to about 15 mm. | 01-16-2014 |
| 20140021469 | INTEGRATED CIRCUIT INCLUDING SENSOR STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE - An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure. | 01-23-2014 |
| 20140027771 | DEVICE IDENTIFICATION ASSIGNMENT AND TOTAL DEVICE NUMBER DETECTION - Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device. In an embodiment, each die may include a respective assignment device to operate on an input and generate, as an output, the respective one of the sequence of the unique device ID values. Each die may also include a respective evaluation device to detect a total number of dice in the stack. Additional apparatuses and methods are described. | 01-30-2014 |
| 20140027772 | Wafers and Chips Comprising Test Structures - Wafers with chips thereon and corresponding chips are provided where test structures or parts thereof are provided in a peripheral chip area of the chip. Corresponding methods are also disclosed. | 01-30-2014 |
| 20140042442 | RELIABLE PHYSICAL UNCLONABLE FUNCTION FOR DEVICE AUTHENTICATION - The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device. | 02-13-2014 |
| 20140048803 | SEMICONDUCTOR DEVICE CAPABLE OF TESTING BONDING OF PAD - A test circuit includes a phase difference detection unit and a determination unit. The phase difference detection unit detects a phase difference between a first signal received through a first pad and a second signal received through a second pad. The determination unit compares the detected phase difference with a preset amount of delay and outputs a result signal. | 02-20-2014 |
| 20140061641 | METROLOGY TEST STRUCTURES IN TEST DIES - Test dies having metrology test structures and methods of manufacture are disclosed. The method includes forming one or more metrology test structures in a test die that are identical to one or more structures formed in an adjacent product chip. | 03-06-2014 |
| 20140061642 | METHOD AND APPARATUS FOR ROUTING DIE SIGNALS USING EXTERNAL INTERCONNECTS - Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die. | 03-06-2014 |
| 20140061643 | SEMICONDUCTOR DEVICE - A semiconductor device includes an AC coupling element, and a temperature monitoring unit that outputs a temperature monitor signal, the temperature monitoring unit has a first temperature monitoring element that outputs the temperature monitor signal, and the first temperature monitoring element is arranged in a region immediately below or a region adjacent to the AC coupling element. | 03-06-2014 |
| 20140061644 | SUPER-JUNCTION SEMICONDUCTOR DEVICE - An SJ-MOSFET can include an active region serving as a main current path and a temperature detection region including a temperature detecting diode. Main SJ cells in which n drift regions and p partition regions are alternately adjacent to each other are arranged in a drift layer in the active region. The temperature detection region is provided in the active region. Fine SJ cells in which n drift regions and p partition regions are alternately bonded to each other at a pitch less than that of the n drift region and the p partition region of the main SJ cell are arranged in the drift layer in the temperature detection region. The temperature detecting diode is formed above the fine SJ cells with an insulating film) interposed therebetween. The temperature detecting diode includes a p | 03-06-2014 |
| 20140070212 | SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION - A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit. | 03-13-2014 |
| 20140070213 | Methods for Discretized Processing and Process Sequence Integration of Regions of a Substrate - The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate. | 03-13-2014 |
| 20140070214 | SEMICONDUCTOR DEVICE - Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip. | 03-13-2014 |
| 20140077209 | EVALUATION PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR WAFER - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes heating a resistor pattern by scanning the resistor pattern with a first beam. The resistor pattern includes resistors, and a connection structure connecting the resistors in series. The resistors is arranged in matrix of two or more rows and two or more columns. The method includes further heating the resistor pattern by scanning the resistor pattern with a second beam having a different scan direction as that of the first beam. | 03-20-2014 |
| 20140097429 | ARRAY SUBSTRATE FOR FLEXIBLE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE - In an aspect, an array substrate for a flexible display device and a method of manufacturing the array substrate, the method including operations of arranging at least one lower protective film on which a plurality of display units that are covered by thin-film encapsulation (TFE) units are arrayed; performing half cutting and full cutting on the at least one lower protective film; and completing the manufacture of each of the plurality of display units by removing remaining parts on the at least one lower protective film from the half cutting and full cutting is provided. | 04-10-2014 |
| 20140097430 | ARRAY SUBSTRATE FOR FLEXIBLE DISPLAY DEVICE - An array substrate for a flexible display device, the array substrate including a mother substrate, a plurality of display units separated on the mother substrate, in which the plurality of display units include display regions that display images and non-display regions that extend from the display regions to edges of each of the plurality of display units, respectively, encapsulation units covering the display regions of the plurality of display units, respectively, a plurality of testing wires in a wire region between adjacent display units from among the plurality of display units, in which the plurality of testing wires are electrically connected to each of the plurality of display units, and crack preventing units in the non-display regions between edges of the encapsulation units and the edges of each of the plurality of display units, respectively. | 04-10-2014 |
| 20140097431 | SEMICONDUCTOR DEVICES AND PROCESSING METHODS - A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential. | 04-10-2014 |
| 20140103344 | DETECTION OF RECOVERED INTEGRATED CIRCUITS - An apparatus for detection of integrated circuit recovery is disclosed. An example apparatus can comprise a first sensor embedded in an integrated circuit. The example apparatus can comprise a second sensor embedded in the integrated circuit. The example apparatus can comprise a selector unit configured to select one of the first sensor or the second sensor. The example apparatus can also comprise a monitor unit configured to receive output signal from the first sensor and the second sensor and to supply the output signal to an analysis unit. | 04-17-2014 |
| 20140110710 | STACKED CHIP MODULE WITH INTEGRATED CIRCUIT CHIPS HAVING INTEGRATABLE AND RECONFIGURABLE BUILT-IN SELF-MAINTENANCE BLOCKS - Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module. | 04-24-2014 |
| 20140110711 | STACKED CHIP MODULE WITH INTEGRATED CIRCUIT CHIPS HAVING INTEGRATABLE BUILT-IN SELF-MAINTENANCE BLOCKS - Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers. | 04-24-2014 |
| 20140110712 | SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner. | 04-24-2014 |
| 20140117354 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first semiconductor package including a first terminal and a second terminal provided on a surface different from a surface on which the first terminal is formed, and a second semiconductor package including a third terminal connected to the first terminal, wherein the surface on which the first terminal is formed faces a surface on which the third terminal is formed. | 05-01-2014 |
| 20140117355 | Display Device - A display device includes a substrate having a display region with signal lines within the display region connected to respective terminals in a terminal group outside the display region via terminal wires, and an IC driver having bumps facing and connected to the terminals via an isotropic conductive film. The terminal wires have first, second, third and fourth terminal wires, and the terminals have a first terminal connected to the first terminal wire, a second terminal connected to the second terminal wire, a third terminal connected to the third terminal wire, and a fourth terminal connected to the fourth terminal wire. The first terminal and the second terminal are staggered with respect to each other, the second terminal and the third terminal are staggered with respect to each other, and the third terminal and the fourth terminal are staggered with respect to each other. | 05-01-2014 |
| 20140124782 | IMAGE SENSOR - An image sensor may include a first layer on a substrate and including a chalcogenide-containing material, and a detection part connected to the first layer and configured to detect a variation in electric characteristics of the first layer. The chalcogenide-containing material may include one of A | 05-08-2014 |
| 20140131707 | METHOD AND DEVICE FOR DETECTING TERMINATION OF ETCHING - Provide is an etching completion detection method that accurately detects an etching completion position in an SOI substrate, regardless of the width of an opening. This etching completion detection method is a method for detecting etching completion when a silicon layer is being etched to form an opening that reaches an insulating layer in an SOI substrate in which the silicon layer is disposed on the insulating layer, the method including: forming a first electrode layer on a surface of an islet region that is surrounded by a loop-shaped opening to be formed by the etching, and a second electrode layer in a region outside the stripe region; measuring an electrical resistance between the first electrode layer and the second electrode layer; and determining that the loop-shaped opening has reached an etching completion position when the electrical resistance exceeds a preset threshold. | 05-15-2014 |
| 20140131708 | SEMICONDUCTOR DEVICE INCLUDING AN ASYMMETRIC FEATURE, AND METHOD OF MAKING THE SAME - A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact. | 05-15-2014 |
| 20140131709 | Semiconductor Package with Temperature Sensor - According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package. | 05-15-2014 |
| 20140138685 | Array Substrate, Method for Fabricating and Testing Array Substrate, and Display Device - The present invention provides an array substrate, which includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode and a passivation layer, the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode and the pixel electrode are connected, the passivation layer is disposed on the active layer, the source electrode, the drain electrode and the pixel electrode, the common electrode is disposed above the pixel electrode with the passivation layer therebetween, a test electrode is disposed on the active layer and under the passivation layer, the test electrode is electrically insulated from the gate electrode, the source electrode and the drain electrode. Correspondingly, a method for fabricating and a method for testing the array substrate, and a display device including the array substrate are provided. | 05-22-2014 |
| 20140138686 | PROTECTION OF AN INTEGRATED CIRCUIT AGAINST ATTACKS - An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage. | 05-22-2014 |
| 20140145191 | VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION - A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure. | 05-29-2014 |
| 20140145192 | MASK AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUTOR DEVICE - A mask includes a substrate, an effective pixel formation region and a reference pattern formation region. A pixel pattern for forming a pixel component that constitutes a pixel is arranged in the effective pixel formation region. A reference pattern for indicating a reference position where pixel pattern should be arranged in the effective pixel formation region is arranged in the reference pattern formation region. Pixel pattern is arranged to be displaced from the reference position toward a center side of the effective pixel formation region. | 05-29-2014 |
| 20140145193 | LEAD FRAME AND POWER MODULE - A problem to be solved is to provide a lead frame and a power module having high material yield. | 05-29-2014 |
| 20140145194 | Semiconductor Device Components and Methods - Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end. | 05-29-2014 |
| 20140151697 | Semiconductor Packages, Systems, and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a current rail comprising a first contact area and a second contact area, a first groove and a second groove, and a magnetic field generating portion. Along a current flow direction, the first groove is disposed between the first contact area and the magnetic field generating portion and the second groove is disposed between the magnetic field generating portion and the second contact area. The thickness of the current rail at the first groove is smaller than the thickness of the current rail at the first contact area. | 06-05-2014 |
| 20140151698 | Test Structures for Post-Passivation Interconnect - An integrated circuit structure includes a passivation layer, a polymer layer over the passivation layer, and a PPI monitor structure. The PPI monitor structure includes a portion overlying a portion of the polymer layer. The PPI monitor structure is electrically floating. | 06-05-2014 |
| 20140151699 | Test Structure Placement on a Semiconductor Wafer - A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures. | 06-05-2014 |
| 20140151700 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A chip package may include an interconnection layer having a first surface configured to face at least one chip, and a second surface opposite the first surface; at least one first pad and at least one second pad formed at at least one of the first surface and the second surface of the interconnection layer; at least one first conductive interconnect formed over the at least one first pad; and at least one second conductive interconnect formed over the at least one second pad, wherein a height of the at least one first conductive interconnect is less than a height of the at least one second conductive interconnect. | 06-05-2014 |
| 20140151701 | EMBEDDED CHIP PACKAGE, A CHIP PACKAGE, AND A METHOD FOR MANUFACTURING AN EMBEDDED CHIP PACKAGE - An embedded chip package is provided. The embedded chip package includes a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal. | 06-05-2014 |
| 20140151702 | SEMICONDUCTOR DEVICE HAVING CHIP CRACK DETECTION STRUCTURE - A semiconductor device includes a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias, a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via; a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via, and a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal. | 06-05-2014 |
| 20140151703 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least two semiconductor chips each including a plurality of data input/output pads, a data memory portion structured so as to read/write data through the plurality of data input/output pads, a test result input/output pad, and a test circuit for controlling a first test mode that decides data read from the data memory portion and outputs the decision from the test result input/output pad and a second test mode that decides data read from the data memory portion, inputs test result of another semiconductor chip from the test result input/output pad and outputs a synthesized test result of the test result of the chip itself and the test result of the other semiconductor chip from a specified part of the plurality of data input/output pads, and a plurality of data input/output terminals each connected with different data input/output pads. | 06-05-2014 |
| 20140159040 | AUTHENTICATION USING GRAPHENE BASED DEVICES AS PHYSICAL UNCLONABLE FUNCTIONS - The present disclosure relates to secure devices having a physical unclonable function and methods of manufacturing such secure devices. One device includes at least one graphene layer representing a physical unclonable function and a measurement circuit for measuring at least one property of the at least one graphene layer. Another device includes at least a first graphene layer and a second graphene layer representing a physical unclonable function, where one of the graphene layers has been subjected to a variability enhancement such that a measurable property is different for each of the layers. A method includes providing a substrate for a secure device and providing at least one graphene layer on the substrate, the at least one graphene layer representing a physical unclonable function. The providing of the at least one graphene layer includes applying at least one variability enhancement to the at least one graphene layer. | 06-12-2014 |
| 20140159041 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first circuit block formed on a first semiconductor substrate having first and second sides extending in a first direction and third and fourth sides extending in a second direction intersecting with the first direction; a plurality of signal-line through vias that are connected to the first semiconductor substrate and transmit signals, which are output from the first circuit block, to a second circuit block formed on another second semiconductor substrate; and a plurality of power-supply through vias for supplying power to the first circuit block, and in the semiconductor device, the plurality of power-supply through vias are formed at edges of the first semiconductor substrate along the third and fourth sides and are formed in a plurality of rows in the first direction. Each circuit block has a power consuming mode in which power larger than the power consumption in a normal mode is consumed. | 06-12-2014 |
| 20140167043 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner. | 06-19-2014 |
| 20140167044 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner. | 06-19-2014 |
| 20140167045 | TEST PATTERN FOR TRENCH POLY OVER-ETCHED STEP AND FORMATION METHOD THEREOF - A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench ( | 06-19-2014 |
| 20140175439 | SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI-CHIP PACKAGE INCLUDING THE SAME - In an aspect of the present invention, a semiconductor integrated circuit includes a semiconductor chip including a through-chip via, a probe pad disposed in such a way as not to overlap with the through-chip via, and a connection part electrically coupling the probe pad and the through-chip via | 06-26-2014 |
| 20140183533 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING AN INTEGRATED CIRCUIT EQUIPPED WITH A TEMPERATURE PROBE - This integrated circuit comprises:
| 07-03-2014 |
| 20140183534 | THIN-WAFER CURRENT SENSORS - Embodiments relate to IC current sensors fabricated using thin-wafer manufacturing technologies. Such technologies can include processing in which dicing before grinding (DBG) is utilized, which can improve reliability and minimize stress effects. While embodiments utilize face-up mounting, face-down mounting is made possible in other embodiments by via through-contacts. IC current sensor embodiments can present many advantages while minimizing drawbacks often associated with conventional IC current sensors. | 07-03-2014 |
| 20140191233 | MICROPHONE COMPONENT - A 2-chip MEMS microphone component includes: at least one first MEMS microphone structural component having at least one first microphone structure formed in the front side of the structural component; an ASIC structural component having evaluation electronics for the microphone signal of the MEMS microphone structural component; and a housing having a sound opening. The MEMS microphone structural component is mounted within the housing and above the sound opening in such a way that the rear side of the microphone structure is acted on by the sound pressure. The ASIC structural component also includes a second MEMS microphone structure whose microphone signal is fed to the evaluation electronics. | 07-10-2014 |
| 20140191234 | Three Dimensional Stacked Structure for Chips - A 3-D chip stacked structure is disclosed. Each chip layer is provided with plural single-layered conductive members where among the same chip layer the two adjacent conductive members are structurally formed in minor symmetric way with each other along a chip longitudinal direction and the arrangements of the single-layered conductive members of the two adjacent chip layers are shifted by a test pad distance. The single-layered conductive members of the two adjacent chip layers are communicated through a vertical TSV (through silicon via). Therefore, a selection signal or an enabling signal might be transferred through this specific metal layer and related TSV to reach targeting chip layer and targeting circuit. | 07-10-2014 |
| 20140191235 | MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS - A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure. | 07-10-2014 |
| 20140197409 | MULTI-CHIP PACKAGE AND INTERPOSER WITH SIGNAL LINE COMPRESSION - A multi-chip package with signal line compression for testing of the multi-chip package. The multi-chip package includes an interposer and two or more integrated circuits attached to the interposer. The interposer includes multiple data signal lines for data communications between the two integrated circuits. The data signal lines are also coupled to one or more test contacts through an interface circuit. The number of test contacts is smaller than the number of signal lines, which allows a large number of signal lines to be tested with a smaller number of test contacts. | 07-17-2014 |
| 20140203278 | Chip Package Having Terminal Pads of Different Form Factors - A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip. The first and second groups of terminal pads are arranged on a common terminal surface of the chip package. A pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads. | 07-24-2014 |
| 20140203279 | TEST STRUCTURE AND METHOD TO FACILTIATE DEVELOPMENT/OPTIMIZATION OF PROCESS PARAMETERS - A test structure and method are provided to facilitate developing or optimizing a fabrication process by determining values of one or more lithography process parameters for use in semiconductor device fabrication. The test structure is configured to facilitate determining values of the one or more fabrication process parameters, and includes a plurality of test structure components arranged on a substrate according to a test pattern. The test pattern may be based on: varying distances between the test structure components according to a first rule; varying distances between centers of the test structure components according to a second rule; and/or varying at least one dimension of the test structure components according to a third rule. The method may further include determining dimensions of one or more components of the test structure using, for example, scatterometry, and using the dimensions of the components to ascertain one or more fabrication process parameters. | 07-24-2014 |
| 20140203280 | ELECTRICAL TEST STRUCTURE FOR DEVICES EMPLOYING HIGH-K DIELECTRICS OR METAL GATES - A test structure includes an active region formed in a semiconducting substrate, a first line formed above and extending over an upper surface of the active region, and a first isolation region formed in the semiconducting substrate, wherein the active region surrounds the first isolation region. The test structure further includes a first extension formed above the active region and on and in contact with an upper surface of the first isolation region, wherein the first extension extends laterally over the upper surface of the active region from a first side of the first line. Additionally, the first line and the first extension are comprised of at least one of a high-k layer of insulating material and a metal layer. | 07-24-2014 |
| 20140203281 | DISPLAY DEVICE HAVING REPAIR AND DETECT STRUCTURE - A display device having repair and detect structure includes a substrate, a pixel array, a first shorting bar and a first repair line. The pixel array disposed on the substrate includes a plurality of data lines and a plurality of gate lines. The first shorting bar disposed on the substrate is connected to the gate lines for testing the gate lines, and the first shorting bar includes a first shorting segment. The first repair line is disposed on the substrate for repairing at least one of the data lines. The first shorting segment of the first shorting bar is electrically connected to the first repair line. Furthermore, another repair and detect structure of a display device is disclosed, wherein the first shorting bar includes a first shorting segment, the first repair line includes a first repair segment, and the first shorting segment overlaps with the first repair segment. | 07-24-2014 |
| 20140203282 | Semiconductor Test Structures - A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes. | 07-24-2014 |
| 20140209904 | INTEGRATED TEST CIRCUIT AND METHOD FOR MANUFACTURING AN INTEGRATED TEST CIRCUIT - An integrated test circuit, including a plurality of test structure elements, wherein each test structure element includes at least a supply line and a test line; a plurality of select transistors, wherein each select transistor is assigned to one corresponding test structure element, and wherein each select transistor includes a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; and a plurality of contact pads, connected to respective first controlled regions and control regions of the plurality of select transistors, such that each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads. | 07-31-2014 |
| 20140209905 | Integrated Circuit, Semiconductor Device and Method of Manufacturing a Semiconductor Device - An integrated circuit including a semiconductor device has a power component including a plurality of trenches in a cell array, the plurality of trenches running in a first direction, and a sensor component integrated into the cell array of the power component and including a sensor cell having an area which is smaller than an area of the cell array of the power component. The integrated circuit further includes isolation trenches disposed between the sensor component and the power component, an insulating material being disposed in the isolation trenches. The isolation trenches run in a second direction that is different from the first direction. | 07-31-2014 |
| 20140209906 | Method of Fabricating GOI Silicon Wafer, GOI Silicon Wafer and GOI Detection Method - The invention discloses a method of fabricating a GOI silicon wafer, a GOI silicon wafer, and a method of GOI detection on the fabricated GOI silicon wafer, where the method of fabricating a GOI silicon wafer includes: in a process of fabricating a trench-type VDMOS, after a trench is formed and a gate oxide layer is grown, a poly-silicon layer is grown; and after the poly-silicon layer is grown, a mask of a metal layer is aligned with a silicon substrate with the poly-silicon layer grown, where the mask of the metal layer is a mask used in formation of the metal layer in the process of fabricating the VDMOS; and at least one pattern for GOI detection is formed on the silicon substrate with the poly-silicon layer grown, through the aligned mask of the metal layer in a photo-lithography to form a GOI silicon wafer. With the technical solution here according to an embodiment of the invention, an error between the GOI silicon wafer and the VDMOS device can be lowered, good accuracy can be achieved, and a resource can be saved effectively, and furthermore the accuracy in a result of GOI detection can be well improved. | 07-31-2014 |
| 20140209907 | SEMICONDUCTOR APPARATUS AND STACKED SEMICONDUCTOR APPARATUS FOR CHECKING FORMATION AND CONNECTION OF THROUGH SILICON VIA - A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal. | 07-31-2014 |
| 20140209908 | FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING - Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly. | 07-31-2014 |
| 20140209909 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed allowing detection of a connection state of a Through Silicon Via (TSV) at a wafer level. The semiconductor device includes a first line formed over a Through Silicon Via (TSV), a second line formed over the first line, and a first power line and a second power line formed over the same layer as the second line. Therefore, the semiconductor device can screen not only a chip-to-chip connection state after packaging completion, but also a connection state between the TSV and the chip at a wafer level, so that unnecessary costs and time encountered in packaging of a defective chip are reduced. | 07-31-2014 |
| 20140217406 | Apparatus and Method for Non-Intrusive Random Memory Failure Emulation Within an Integrated Circuit - The system and methods allow for emulation of random hardware failure of an internal embedded memory array of an integrated circuit (IC) device. Emulation of potential defects is performed in order to evaluate the behavior of the rest of the design. This non-intrusive emulation is performed in a pseudo-functional mode in order to evaluate the behavior of one or more memory cores in their standard functional mode. The solution enables the creation of failures and tracking both the detection of the failures and the time required time for detection. Specifically, the emulation of an internal memory array with respect of random failures and the associated diagnostic mechanism ensures that detection and correction mechanisms work as expected. A typical non-limiting use case is to ensure that safety control logic of an IC behaves as expected in cases of data corruption within an embedded memory core. | 08-07-2014 |
| 20140217407 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A donor layer that is formed by performing a heat treatment for a crystal defect formed by proton radiation is provided in an n-type drift layer of an n | 08-07-2014 |
| 20140239300 | SEMICONDUCTOR TEST DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor test devices and methods for fabricating the same may be provided. The semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, and a test substrate formed under the first thermal test flip chip cell. The first thermal test flip chip cell may include a plurality of first bumps arranged on a bottom surface of the first thermal test flip chip cell and be configured to be electrically connected to the first heater and the first sensor. The test substrate may include a first ball array arranged on a bottom surface of the test substrate in a first direction and be configured to be electrically connected to the plurality of first bumps, which are electrically connected to the first heater and the first sensor. | 08-28-2014 |
| 20140252356 | DEVICES AND METHODS FOR MEASUREMENT OF MAGNETIC CHARACTERISTICS OF MRAM WAFERS USING MAGNETORESISTIVE TEST STRIPS - Methods for testing magnetoresistance of test devices with layer stacks, such as MTJs, fabricated on a wafer are described. The test devices can be fabricated along with arrays of similarly structured memory cells on a production wafer to allow in-process testing. The test devices with contact pads at opposite ends of the bottom electrode allow resistance across the bottom electrode to be measured as a surrogate for measuring resistance between the top and bottom electrodes. An MTJ test device according to the invention has a measurable magnetoresistance (MR) between the two contact pads that is a function of the magnetic orientation of the free layer and varies with the length and width of the MTJ strip in each test device. The set of test MTJs can include a selected range of lengths to allow the tunnel magnetoresistance (TMR) and resistance area product (RA) to be estimated or predicted. | 09-11-2014 |
| 20140252357 | SEMICONDUCTOR DEVICE - Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip. | 09-11-2014 |
| 20140264331 | DAISY CHAIN CONNECTION FOR TESTING CONTINUITY IN A SEMICONDUCTOR DIE - An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch. | 09-18-2014 |
| 20140264332 | SEMICONDUCTOR CHIP WITH POWER GATING THROUGH SILICON VIAS - A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground. | 09-18-2014 |
| 20140264333 | METHOD AND APPARATUS FOR MONITORING SEMICONDUCTOR FABRICATION - A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated with a stack with at least one horizontal interconnect, the stack and the diode connected in series to form a diode stack combination, wherein the horizontal interconnect has a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode. | 09-18-2014 |
| 20140264334 | LAYOUT FOR RETICLE AND WAFER SCANNING ELECTRON MICROSCOPE REGISTRATION OR OVERLAY MEASUREMENTS - A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively. | 09-18-2014 |
| 20140264335 | PACKAGE SUBSTRATE AND METHOD FOR TESTING THE SAME - A package substrate is provided, including a board body having a wiring region and a testing region defined thereon, conductive pads embedded in the wiring region, and a plurality of testing pads disposed in the testing region and electrically connected to the conductive pads, wherein the top surface area of each of the testing pads is greater than the top surface area of each of the conductive pads in order to facilitate a precise alignment of a probe with a corresponding one of the testing pads and prevent the probe from being blocked by the board body when in electrically testing an embedded circuit. | 09-18-2014 |
| 20140264336 | PATTERN FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICE MANUFACTURING AND PROCESS MONITORING - A pattern for use in the manufacture of semiconductor devices is provided which, according to an example embodiment, may comprise at least one second field region comprising a main array of dies, each having a height of Y | 09-18-2014 |
| 20140264337 | PACKAGING MECHANISMS FOR DIES WITH DIFFERENT SIZES OF CONNECTORS - Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost. | 09-18-2014 |
| 20140264338 | LINE STRUCTURE FOR REPAIR AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME - A line structure for repair may include a first line in a first direction, a second line parallel with the first line, the second line having side portions extending along a second direction from respective end portions and coupled to the first line, and a third line intersecting the first and second lines, wherein at least one portion of the second line is made of undoped poly-silicon. | 09-18-2014 |
| 20140264339 | HEAT SLUG HAVING THERMOELECTRIC ELEMENTS AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - In a heat slug and a semiconductor package including the same, the heat slug includes a thermal conductive body having an active face and a dissipating face opposite to the active face, a dielectric layer covering the active face of the body, at least one thermoelectric element arranged on the dielectric layer and a conductive pattern arranged on the dielectric layer and electrically connected to the thermoelectric element. The electrical characteristics of the thermoelectric element are interacted with heat generated from a heat source. | 09-18-2014 |
| 20140264340 | REVERSIBLE HYBRIDIZATION OF LARGE SURFACE AREA ARRAY ELECTRONICS - Various technologies pertaining to characterizing a component of a large surface area array electronic device, such as a focal plane array (FPA), are described. A first semiconductor chip is reversibly hybridized with a second semiconductor chip through use of a conductive layer. Responsive to being reversibly hybridized, at least one of the first semiconductor chip or the second semiconductor chip is characterized as being defective or suitable for deployment. Thereafter, the conductive layer is removed, and the first semiconductor chip is separated from the second semiconductor chip without damaging either of the first semiconductor chip or the second semiconductor chip. | 09-18-2014 |
| 20140291677 | INTEGRATED MULTI-SENSOR MODULE - A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed. Such a miniature integrated multi-sensor module that features low power consumption can be used in medical monitoring and mobile computing, including smart phone applications. | 10-02-2014 |
| 20140291678 | SEMICONDUCTOR SENSOR RELIABILITY OPERATION - Embodiments of the present invention provide a semiconductor sensor reliability system and method. Specifically, the present invention provides in-situ positioning of a reliability sensor (hereinafter sensors) within each functional block, as well as at critical locations, of a semiconductor system. The quantity and location of the sensors are optimized to have maximum sensitivity to known process variations. In general, the sensor models a behavior (e.g., aging process) of the location (e.g., functional block) in which it is positioned and comprises a plurality of stages connected as a network and a self-digitizer. Each sensor has a mode selection input for selecting a mode thereof and an operational trigger input for enabling the sensor to model the behavior. The model selection input and operation trigger enable the sensor to have an operational mode in which the plurality of sensors are subject to an aging process, as well as a measurement mode in which an age of the plurality of sensors is outputted. Based on the output, one or more functional blocks are modified by a control sensor component to reduce semiconductor system degredation in real-time. | 10-02-2014 |
| 20140291679 | SEMICONDUCTOR DEVICE - A semiconductor device disclosed in the present specification comprises: a semiconductor chip, a package that incorporates the semiconductor chip, and a plurality of lower-surface pads disposed on a lower surface of the package, a plurality of upper-surface pads disposed on an upper surface of the package, wherein the plurality of upper-surface pads include a plurality of monitor pads each of which is connected to each of all the lower-surface pads. | 10-02-2014 |
| 20140299878 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate, and a stack of semiconductor chips over the package substrate, each of the semiconductor chips including first and second surfaces, each of the semiconductor chips including a first through electrode that extends through each of the semiconductor chips, a first surface electrode positioned on the first surface of each of the semiconductor chips, the first surface electrode being coupled to a first end of the first through electrode, a second surface electrode positioned on the second surface of each of the semiconductor chips, the second surface electrode being coupled to a second end of the first through electrode, a second through electrode that extends through each of the semiconductor chips, the second through electrode having third and fourth ends, and a third surface electrode positioned on the second surface of the first semiconductor chip. | 10-09-2014 |
| 20140319522 | FAR BACK END OF THE LINE METALLIZATION METHOD AND STRUCTURES - Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s). | 10-30-2014 |
| 20140319523 | CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE HAVING THE SAME - A chip-on-film package includes a base film, a test line, and an integrated circuit chip. The base film includes a bent area in which a bending occurs. The test line is disposed on the base film, and at least a portion of the test line is overlapped with the bent area. The integrated circuit chip is disposed on the base film and includes a first terminal and a second terminal. The first terminal is connected to one end of the test line to output a first signal and the second terminal is connected to the other end of the test line to receive a second signal. The integrated circuit chip detects whether a crack occurs in the bent area based on a difference value in signal characteristics. | 10-30-2014 |
| 20140327003 | Removable indicator structure in electronic chips of a common substrate for process adjustment - A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure. | 11-06-2014 |
| 20140327004 | Lead Frame Strips with Support Members - A lead frame strip includes a plurality of connected unit lead frames. Each unit lead frame has a die paddle for attaching to a semiconductor die, a tie bar connecting the die paddle to a periphery of the unit lead frame, and a plurality of leads projecting from the periphery toward the die paddle. The lead frame strip further includes a support member patterned into or connected to the periphery of each unit lead frame at a proximal end and bent into a different plane than the leads so that a distal end of each support member is disposed above or below the leads and projects toward the die paddles. The distal end of the support members can be anchored in a mold compound encapsulating electronic components attached to the die paddles, to maintain structural integrity during lead frame strip testing prior to unit lead frame separation. | 11-06-2014 |
| 20140327005 | Apparatus and Methods for De-Embedding Through Substrate Vias - An apparatus for de-embedding through substrate vias is provided. The apparatus may include pads on a first side of a substrate are coupled to through vias extending through a substrate, wherein pairs of the through vias are interconnected by transmission lines of varying lengths along a second side of the substrate. The apparatus may further include pairs of pads coupled together by transmission lines of the same varying lengths. Apparatuses may include through vias surrounding a through via device under test. The surrounding through vias are connected to the through via device under test by a backside metal layer. The apparatus may further include a dummy structure having an area equal to an area of the backside metal layer. | 11-06-2014 |
| 20140332810 | TEMPORARY LIQUID THERMAL INTERFACE MATERIAL FOR SURFACE TENSION ADHESION AND THERMAL CONTROL - An assembly including a liquid thermal interface material for surface tension adhesion and thermal control used during electrical/thermal test of a 3D wafer and methods of use. The method includes temporarily attaching a thinned wafer to a carrier wafer by applying a non-adhesive material therebetween and pressing the thinned wafer and the blank silicon-based carrier wafer together. | 11-13-2014 |
| 20140332811 | SEMICONDUCTOR DEVICE WITH BOND AND PROBE PADS - A semiconductor die has an active face with an arrangement of I/O pads around its edges. The I/O pads include bond pads and probe pads. Two types of I/O pads are provided and the two types of pads are arranged in a staggered arrangement around the edges of the die. The first type of I/O pad has bond pads that are spaced from the probe pads and connected with an interconnecting member. The second type of I/O pads has bond pads that are adjacent to and abutting probe pads. Providing two types of I/O pads and the staggered arrangement of the I/O pads reduces the area of the I/O pads and underlying I/O regions, which saves core area of the die. | 11-13-2014 |
| 20140332812 | WAFER AND SYSTEM AND METHOD FOR TESTING THE WAFER - A wafer is provided. The wafer includes at least one field. The field includes at least one chip, and at least one test chip that generates power using a wireless signal, that provides power to the chip, that tests performance of the chip, and that corrects performance of the chip according to a test result. | 11-13-2014 |
| 20140332813 | SEMICONDUCTOR DEVICE - A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge. | 11-13-2014 |
| 20140339558 | ALTERNATING OPEN-ENDED VIA CHAINS FOR TESTING VIA FORMATION AND DIELECTRIC INTEGRITY - Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area. | 11-20-2014 |
| 20140339559 | SEMICONDUCTOR DEVICE HAVING TEST STRUCTURE - A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures. | 11-20-2014 |
| 20140346509 | Semiconductor Component with Integrated Crack Sensor and Method for Detecting a Crack in a Semiconductor Component - A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body. | 11-27-2014 |
| 20140346510 | DEVICE STRUCTURE SUITABLE FOR PARALLEL TEST - A device structure suitable for parallel test is disclosed, which includes a main body and an anti-crosstalk structure. The main body includes a first well formed in a substrate, the first well defining a boundary of the main body in the substrate. The anti-crosstalk structure is a second well formed in the substrate and surrounding the first well of the main body. The second well has a conductivity type opposite to a conductivity type of the first well and has a depth greater than a depth of the first well. The present invention is capable of preventing the interference between leakage currents generated in bases of the same conductivity type of different such device structures during a parallel test, thereby allowing the leakage currents to be correctly measured and improving the reliability of measurement result and the test efficiency. | 11-27-2014 |
| 20140346511 | ARRAY SUBSTRATE, MANUFACTURING METHOD, AND DISPLAY DEVICE THEREOF - An array substrate, a manufacturing method, and a display device thereof are disclosed. The array substrate comprises a plurality of pixel units, each of the pixel units comprises a first transparent conductive layer and a second transparent conductive layer ( | 11-27-2014 |
| 20140346512 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device, a target chip, a test chip, and an electronic device are incorporated in a package. A signal terminal of the target chip is a target terminal and to be subjected to a test. The test chip has a test mechanism for allowing the test to be performed through an external terminal exposed outside the package. In a product operation mode where the semiconductor integrated circuit device operates as a product, the electronic device is connected to the target terminal. The test chip includes a common wire connected to the test terminal, a first terminal connected to the target terminal, a first switch for opening and closing a connection between the common wire and the first terminal, a second terminal connected to the electronic device, and a second switch for opening and closing a connection between the first terminal and the second terminal. | 11-27-2014 |
| 20140346513 | Mixed-Sized Pillars That Are Probeable and Routable - An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and multiple macro-pillars also attached to the surface of the integrated circuit. The micro-pillars provide an electrical interface to the integrated circuit during regular operation. The macro-pillars provide an electrical interface to the integrated circuit both during regular operation and during testing of the integrated circuit. | 11-27-2014 |
| 20140346514 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a semiconductor element including an electrode; a leading line electrically connected to the electrode, passing above the electrode, and led to a side thereof; and a current sensor sensing current flowing through the leading line. The current sensor includes a magneto-resistance element placed above the electrode and below the leading line. A resistance value of the magneto-resistance element varies linearly according to magnetic field generated by the current. | 11-27-2014 |
| 20140346515 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Detection accuracy of a semiconductor device for detecting various kinds of substances including biological matter such as DNA is to be increased. This semiconductor device includes: a channel region CH placed on a first surface of a silicon oxide film | 11-27-2014 |
| 20140346516 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR PACKAGES - A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption. | 11-27-2014 |
| 20140353664 | SEMICONDUCTOR CHIP, SEMICONDUCTOR APPARATUS HAVING THE SAME AND METHOD OF ARRANGING THE SAME - Provided is a semiconductor apparatus in which a plurality of semiconductor chips stacked in a vertical direction. Each of the semiconductor chips comprises: a bank area comprising a plurality of banks configured to store data; and a peripheral area including a pad area in which a plurality of pads configured to receive signals for controlling the bank area and a plurality of TSV for electrically connecting the plurality of pads, respectively. | 12-04-2014 |
| 20140353665 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; a first insulating film on a surface of the semiconductor substrate; a temperature sensing diode on the first insulating film; a trench extending inward from the surface of the semiconductor substrate; and a trench electrode embedded in the trench via a second insulating film and connected to the temperature sensing diode. | 12-04-2014 |
| 20140361298 | LITHOGRAPHY PROCESS MONITORING OF LOCAL INTERCONNECT CONTINUITY - Disclosed is a novel system and method to form local interconnects in a continuity test structure. The method begins with a first set of transistor gate lines and a second set of transistor gate lines are formed. Next, a first group of two or more local interconnect lines landing on transistor gates and formed substantially perpendicular to the first set of transistor gate lines and electrically coupled therewith is formed using a first lithography pass. A second group of two or more local interconnect lines landing and formed substantially perpendicular to the second set of transistor gate lines and electrically coupled therewith is formed during second lithography pass. For some technologies, a third set of transistor gate lines is formed along with a third group using a third lithography pass. | 12-11-2014 |
| 20140361299 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. | 12-11-2014 |
| 20140367684 | METHODS FOR TESTING INTEGRATED CIRCUITS OF WAFER AND TESTING STRUCTURES FOR INTEGRATED CIRCUITS - Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material over a first conductor material of the integrated circuit, and contacting a test probe to the deposited sacrificial material. The methods can also include testing the integrated circuit using the test probe contacting the sacrificial material. Finally, the methods can include removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit. | 12-18-2014 |
| 20140367685 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR CHIP - A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n | 12-18-2014 |
| 20140374757 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF MANUFACTURING THE SAME - A circuit board includes a first metal pattern which includes a marking and a first solder resist, a semiconductor memory element mounted on a circuit board, a connection terminal, and a mold resin covering the semiconductor memory element. The semiconductor memory device displays information through the marking which is formed by laser processing on the first metal pattern in areas where the test terminal and the electrode terminal are not provided and the semiconductor memory element is sealed with a mold resin. | 12-25-2014 |
| 20140374758 | System for Wafer-Level Phosphor Deposition - System for wafer-level phosphor deposition. A method for phosphor deposition on a semiconductor wafer that has a plurality of LED dies includes the operations of covering the semiconductor wafer with a selected thickness of photo resist material, removing portions of the photo resist material to expose portions of the semiconductor wafer so that electrical contacts associated with the plurality of LED dies remain unexposed, and depositing phosphor on the exposed portions of the semiconductor wafer. | 12-25-2014 |
| 20150008431 | METHOD AND LAYOUT FOR DETECTING DIE CRACKS - A method of detecting a crack in a semiconductor die is provided. The method includes the following steps. A semiconductor die having an outer edge is provided, wherein a conductive feature is formed on semiconductor die along the outer edge. The conductive feature is biased, and a leakage current of the semiconductor die is measured, such that the crack propagating in the semiconductor the is detected. A semiconductor the with a layout for detecting a die crack and the method of manufacturing it are also provided. The semiconductor the includes a semiconductor the having an cuter edge, and a conductive feature on the semiconductor die along the outer edge. The conductive feature is configured to be biased by an external pin. | 01-08-2015 |
| 20150008432 | MOTHER SUBSTRATE FOR ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A mother substrate for an organic light-emitting display apparatus. The mother substrate has a panel area and a peripheral area surrounding the panel area, pixels disposed in a display area of the panel area, pads that are disposed in a non-display area of the panel area and are coupled to the pixels, test wirings disposed in the peripheral area, a local buffer electrically connected to the test wirings, a bridge wiring connecting the local buffer to one of the pads, and a dummy resistance layer having one end in contact with the bridge wiring and another end in contact with one of the test wirings. | 01-08-2015 |
| 20150014686 | FAST TESTING SWITCH DEVICE AND THE CORRESPONDING TFT-LCD ARRAY SUBSTRATE - A fast testing switch device arranged on a TFT-LCD array substrate is disclosed. The fast testing switch device switches the testing signals for testing a display area of the TFT-LCD array substrate. The fast testing switch device includes at least a first switch TFT. The gate of the first switch TFT connects to one control chip and a testing block for receiving the switch control signals from the testing block or the turn-off control signals from the control chip. The source of the first switch TFT connects to one data testing line or one gate testing line, and the drain of the first switch TFT connects to the corresponding data line or gate line of the display area. In addition, a corresponding TFT-LCD array substrate is also disclosed. The above configuration not only can achieve the narrow-bezel design but also can enhance the yield rate of the TFT-LCD array substrate. | 01-15-2015 |
| 20150014687 | SEMICONDUCTOR DEVICE - A semiconductor device includes an N-type semiconductor region, a back electrode, first and second P-type base regions, first and second N | 01-15-2015 |
| 20150014688 | Thin Wafer Handling and Known Good Die Test Method - A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. | 01-15-2015 |
| 20150021604 | CMOS IMAGE SENSOR HAVING OPTICAL BLOCK AREA - A CMOS image sensor includes an active pixel structure suitable for sensing light incident from outside and converting a sensed light into an electrical signal, and an optical block structure suitable for blocking a visible light and passing a UV light to check and evaluate an electrical characteristic of the active pixel area. The UV pass filter includes first and second insulation layers comprising an insulator, and a metal layer formed between the first and second insulation layers. | 01-22-2015 |
| 20150021605 | MAPPING DENSITY AND TEMPERATURE OF A CHIP, IN SITU - A method and system to map density and temperature of a chip, in situ, is disclosed. The method includes measuring a propagation time that a mechanical propagation wave travels along at least one predefined path in a substrate. The method further includes calculating an average substrate density and temperature along the at least one predefined path as a function of the propagation time and distance. The method further includes determining a defect or unauthorized modification in the substrate based on the average substrate density being different than a baseline substrate density. | 01-22-2015 |
| 20150028337 | Monitoring and Controlling Temperatures in a Semiconductor Structure - An electronic device includes a semiconductor structure. A first temperature sensor is located at a hot spot of the semiconductor structure and a second temperature sensor is located at a cold spot of the semiconductor structure. A control block is configured to control current flow through the semiconductor structure. For example, the control block is configured to cut off the current flow through the semiconductor structure when a temperature at the hot spot exceeds a first predefined threshold or when a temperature difference between the temperature at the hot spot and a temperature at the cold spot exceeds a second predefined threshold. | 01-29-2015 |
| 20150034952 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of cells in a main region, a plurality of cells in a sensing region, a transistor, and a gate shut-off time for the sensing region. The transistor is configured to drive each of the plurality of cells in the main region and each of the plurality of cells in the sensing region. The gate shut-off time for the sensing region is set according to D=(Cgs/Cgm)*(Rgs/Rgm) to be earlier than a gate shut-off time for the main region. D indicates a CR delay ratio, Rgm indicates a gate resistance value for the main region and Rgs indicates a gate resistance value for the sensing region in the transistor, and Cgm indicates a parasitic capacitance for the main region and Cgs indicates a parasitic capacitance for the sensing region in the transistor. | 02-05-2015 |
| 20150041809 | VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION - A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure. | 02-12-2015 |
| 20150048373 | METHOD AND LAYOUT FOR DETECTING DIE CRACKS - A method of detecting a crack in a semiconductor die is provided. The method includes the following steps. A semiconductor die having an outer edge is provided, wherein a conductive feature is formed on semiconductor die along the outer edge. The conductive feature is biased, and a leakage current of the semiconductor die is measured, such that the crack propagating in the semiconductor the is detected. A semiconductor the with a layout for detecting a die crack and the method of manufacturing it are also provided. The semiconductor the includes a semiconductor the having an outer edge, and a conductive feature on the semiconductor die along the outer edge. The conductive feature is configured to be biased by an external pin. | 02-19-2015 |
| 20150053980 | PHOTODETECTOR USING SURFACE PLASMON RESONANCE AND IMAGE SENSOR HAVING THE SAME - Disclosed is a photodetector including an electrically conductive substrate, a first electrode formed on the substrate, a second electrode disposed to be spaced apart from the first electrode, a plasmonic nanostructure positioned between the first electrode and the second electrode and having surface plasmon resonance, and a resistance measuring device or an electrical conductivity measuring device connected to the first electrode and the second electrode. | 02-26-2015 |
| 20150060854 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a main region suitable for performing a first test operation and a second test operation respectively based on a first test signal and a second test signal in a test mode, a first test region electrically connected to the main region and suitable for generating and transferring the first test signal to the main region in the test mode, and a second test region electrically connected to the main region or the first test region with a scribe lane disposed therebetween and suitable for generating and transferring the second test signal to the main region in the test mode. | 03-05-2015 |
| 20150060855 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first pads, a plurality of data input and output units suitable for transmitting a data between a plurality of global lines and the plurality of first pads, respectively, a connection control unit suitable for coupling the plurality of first pads to each other in a test operation period, and a test operation unit suitable for controlling the plurality of data input and output units to transmit a test data in a set order through the plurality of first pads coupled to each other in the test operation period. | 03-05-2015 |
| 20150069394 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line. | 03-12-2015 |
| 20150069395 | Smart Measurement Techniques to Enhance Inline Process Control Stability - An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred. | 03-12-2015 |
| 20150076498 | TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS - A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact. | 03-19-2015 |
| 20150076499 | System and Method for Test Key Characterizing Wafer Processing State - Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group. | 03-19-2015 |
| 20150084051 | Electronic Device, Test Board, and Semiconductor Device Manufacturing Method - Electrical characteristics of a mounting board over which a semiconductor device is mounted is improved. A mounting board (wiring board) includes a plurality of first through holes and second through holes extending from its upper surface bearing a semiconductor device (semiconductor package) to its lower surface and through-hole wirings formed in the respective through holes. The mounting board has a capacitor arranged on its lower surface and electrically connected with the semiconductor device via second electrodes. Among a plurality of first electrodes formed on the upper surface of the mounting board, the several first electrodes to be connected with the capacitor are connected with one wiring formed in a first through hole with a larger diameter than a signal transmission path. | 03-26-2015 |
| 20150084052 | TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor liquid crystal display (TFT-LCD) array substrate comprises a display area comprising a gate line, a data line and a common electrode line, a pixel electrode and a first thin film transistor (TFT) formed in each sub-pixel area defined by the gate line and data line which are crossed with each other; and a test area located at the peripheral of the display area and comprising a first test line, a second test line, a testing electrode and a second TFT, and the common electrode line extending to the test area from the display area, wherein a part of the second test line constitutes a gate electrode of the second TFT; the source electrode of the second TFT is electrically connected with the first test line; a drain of the second TFT is electrically connected with the common electrode line; and the common electrode line is connected with the testing electrode. | 03-26-2015 |
| 20150097184 | Semiconductor Device and a Method for Forming a Semiconductor Device - A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface. | 04-09-2015 |
| 20150097185 | SEMICONDUCTOR DEVICE HAVING TEST UNIT, ELECTRONIC APPARATUS HAVING THE SAME, AND METHOD FOR TESTING THE SEMICONDUCTOR DEVICE - A semiconductor device can detect a defective or faulty part caused by copper (Cu) ions migrated from a through silicon via (TSV), resulting in improvement of device characteristics and reliability. The semiconductor device includes: a semiconductor substrate including an active region defined by a device isolation region; a through silicon via (TSV) formed to pass through the semiconductor substrate; and a test unit formed in the vicinity of the TSV so as to determine the presence or absence of metal pollution caused by the TSV. | 04-09-2015 |
| 20150097186 | DIE TESTING USING TOP SURFACE TEST PADS - Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size. | 04-09-2015 |
| 20150115266 | DIE CRACK DETECTOR WITH INTEGRATED ONE-TIME PROGRAMMABLE ELEMENT - The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. With the fuse intact the package lead can thus be used to determine a measurement of the conductivity of the conductive trace, with the measurement of conductivity indicative of the presence of a crack on the die. After such testing the fuse can be electrically opened, and the package lead used for normal operation of the device on the packaged die without the conductive trace interfering with this operation. | 04-30-2015 |
| 20150115267 | PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area. | 04-30-2015 |
| 20150115268 | SEMICONDUCTOR APPARATUS AND TESTING METHOD THEREOF - A semiconductor apparatus having a through via to be electrically coupled with a chip includes a latch memory cell configured to be electrically coupled with the through via and receive a signal transmitted through the through via, and output a stored signal to the through via. | 04-30-2015 |
| 20150115269 | Semiconductor Device and Method for Manufacturing Semiconductor Device - This invention provides a semiconductor device with improved reliability. A semiconductor chip (semiconductor device) includes a plurality of electrode pads arranged in a plurality of lines extending along a side (chip side) of a perimeter of the semiconductor chip in plan view. Among the electrode pads, the areas of respective electrode pads arranged in a first line along the chip side are smaller than the areas of respective electrode pads arranged in a line located further than the first line from the chip side. | 04-30-2015 |
| 20150123129 | WAFER LEVEL PACKAGING TECHNIQUES - In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer. | 05-07-2015 |
| 20150123130 | TEST KEY STRUCTURE - A test key structure is provided. The test key structure comprises at least one semiconductor element. Each of the at least one semiconductor element including a well, a source region, a drain region and a gate. The source region is disposed in the well. The drain region is disposed in the well and separated from the source region. The gate is disposed above the well. The source region, the drain region and the well have the same type of doping. | 05-07-2015 |
| 20150123131 | Semiconductor Devices and Methods of Formation Thereof - In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node. | 05-07-2015 |
| 20150123132 | SEMICONDUCTOR SYSTEM - A semiconductor system may include a first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad. | 05-07-2015 |
| 20150123133 | INTEGRATED CIRCUIT FOR DETECTING DEFECTS OF THROUGH CHIP VIA - An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode. | 05-07-2015 |
| 20150129874 | EMI SHIELDING IN SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate, a chip disposed over a top surface of the substrate, an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip, a ground pad disposed in the substrate to contact a bottom surface of the substrate, and a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad. A method of testing the semiconductor package is performed using a loop circuit to which a current is applied, the loop circuit being formed by electrically coupling the ground pad, the EMI shielding layer, and the test pad. | 05-14-2015 |
| 20150129875 | DISPLAY DEVICE - In a liquid crystal display device it is desirable to test in the state of TFT substrates, without reducing the number of TFT substrates to be obtained from one mother TFT substrate, and without increasing the overall size of the TFT substrates. Test terminals are formed on the outside of terminals for driving the liquid crystal display device. The test terminals of the specific TFT substrate are formed in another TFT substrate just below the specific TFT substrate. The area in which the test lines are formed is a space in which a sealing material is formed, between the display area and an end of the lower TFT substrate. Thus, the size of the TFT substrates is not actually increased. A test line area is not separately formed and not discarded, so that the number of TFT substrates to be obtained from one mother TFT substrate is not reduced. | 05-14-2015 |
| 20150137125 | SEMICONDUCTOR DEVICE - A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad. | 05-21-2015 |
| 20150144948 | SEMICONDUCTOR DEVICE - A semiconductor device in which the area of a circuit that is unnecessary during normal operation is small. The semiconductor device includes a first circuit and a second circuit. The first circuit includes a third circuit storing at least one pair of first data including a history of a branch instruction and a first address corresponding to the branch instruction; a fourth circuit comparing a second address of an instruction and the first address; and a fifth circuit selecting the first data of one pair among the at least one pair in accordance with a comparison result. The second circuit includes a plurality of sixth circuits having a function of generating a signal for testing operation of the first circuit in accordance with second data, and a function of storing the at least one pair together with the second circuit after the operation is tested. | 05-28-2015 |
| 20150294918 | STAGGERED ELECTRICAL FRAME STRUCTURES FOR FRAME AREA REDUCTION - A method of forming a group of probe pads or sets of probe pads and DUTs in a staggered pattern within a portion of a pad row and the resulting device are disclosed. Embodiments include forming a first group of probe pads or sets of probe pads and DUTs in a pad row on a wafer; and forming a second group of probe pads and DUTs in the pad row on the wafer, wherein the probe pads or sets of probe pads of the first group are staggered along the pad row, and each DUT of the first group is aligned with a probe pad perpendicular to the pad row. | 10-15-2015 |
| 20150294964 | IP PROTECTION - Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners. | 10-15-2015 |
| 20150311130 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display device are provided. The array substrate comprises a display region and a peripheral circuit region (B), wherein a first gate line ( | 10-29-2015 |
| 20150318225 | WAFER HAVING PAD STRUCTURE - A wafer including a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated circuits. The wafer further includes a plurality of dielectric layers formed in the at least one scribe line having a process control monitor (PCM) pad structure formed therein, the PCM pad structure having: a plurality of metal pads interconnected by a plurality of conductive vias. The PCM pad further includes a plurality of contact bars in contact with a bottom-most metal pad, the contact bars extending substantially vertically from the bottom-most metal pad into the substrate. Additionally, the PCM pad includes an isolation structure substantially surrounding the plurality of contact bars to isolate the PCM pad structure. | 11-05-2015 |
| 20150325489 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The light-emitting device has a plurality of light-emitting elements that is mounted on one or more wiring patterns on a substrate. A new light-emitting element that replaces a defective element is mounted on the same wiring pattern on which the defective element is mounted. The defective element or a trace that remains alter removal of the defective element is sealed by a same sealing member by which the new light-emitting element is sealed. | 11-12-2015 |
| 20150338710 | ARRAY STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND ARRAY SUBSTRATE - An array structure and a method for manufacturing the same, an array substrate and a display device are provided, the array structure comprises signal input pads ( | 11-26-2015 |
| 20150340296 | PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area. | 11-26-2015 |
| 20150340594 | Anisotropic Magnetoresistive Device and Method for Fabricating the Same - The present invention relates to an anisotropic magnetoresistive (AMR) device which comprises a substrate, an interconnect structure and a magnetoresistive material layer. The interconnect structure is disposed above the substrate and comprises a plurality of metal interconnect layers. The magnetoresistive material layer is disposed above the interconnect structure. The topmost metal interconnect layer of the plurality of metal interconnect layers comprises a conductive current-shunting structure. The conductive current-shunting structure is physically connected to the magnetoresistive layer without a conductive via plug. | 11-26-2015 |
| 20150348913 | PLANAR METROLOGY PAD ADJACENT A SET OF FINS IN A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers. | 12-03-2015 |
| 20150348978 | SEMICONDUCTOR DEVICE INCLUDING A RESERVOIR CAPACITOR - A semiconductor device includes: a Through Silicon Via (TSV) region extending in a first direction and crossing a center portion of a semiconductor device; a plurality of cell regions disposed at both sides of the TSV region in a second direction crossing the first direction; a plurality of peripheral circuit regions each disposed between the TSV region and a corresponding cell region or between two neighboring cell regions in the first direction; a plurality of test pad regions each disposed at an edge portion of the semiconductor device and having a plurality of test pads, wherein the plurality of test pad regions encloses the cell regions, the peripheral circuit regions, and the TSV region; and a reservoir capacitor disposed below corresponding test pads in a test pad regions. | 12-03-2015 |
| 20150364386 | Stacked Semiconductor Devices and Methods of Forming Same - Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces. | 12-17-2015 |
| 20150364402 | Monitor Structures and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening. | 12-17-2015 |
| 20150371907 | SUBSTRATE FEATURES FOR INDUCTIVE MONITORING OF CONDUCTIVE TRENCH DEPTH - A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines. | 12-24-2015 |
| 20150372008 | SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a semiconductor integrated circuit including: a plurality of first input/output cells arranged on a semiconductor integrated circuit substrate; a plurality of second input/output cells arranged on the semiconductor integrated circuit substrate along the plurality of first input/output cells; and a potential supply portion formed on a semiconductor package substrate, a portion of the potential supply portion protruding in a surface of the semiconductor package substrate, and configured to supply a predetermined potential to a target cell which is one of the plurality of first input/output cells and a cell neighboring the target cell among the plurality of second input/output cells through a region including the protruding portion. | 12-24-2015 |
| 20150380324 | Interposer Test Structures and Methods - An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads. | 12-31-2015 |
| 20150380325 | PHYSICAL LAYOUT FEATURES OF INTEGRATED CIRCUIT DEVICE TO ENHANCE OPTICAL FAILURE ANALYSIS - An integrated circuit device includes an active silicon layer, and at least one passive metal layer placed in an input region and an output region of the device. The at least one passive metal layer has a surface area and thickness for at least one of the input region or the output region to provide a phase shift of an optical laser, the phase shift corresponding to an optimized visibility of the optical laser during an optic failure analysis of the device. | 12-31-2015 |
| 20150380327 | WAFER BONDING STRUCTURES AND WAFER PROCESSING METHODS - A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer. | 12-31-2015 |
| 20150380329 | Contact Test Structure and Method - A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together. | 12-31-2015 |
| 20150380619 | STRUCTURES AND METHODS FOR TESTING PRINTABLE INTEGRATED CIRCUITS - A substrate includes an anchor area physically secured to a surface of the substrate and at least one printable electronic component. The at least one printable electronic component includes an active layer having one or more active elements thereon, and is suspended over the surface of the substrate by electrically conductive breakable tethers. The electrically conductive breakable tethers include an insulating layer and a conductive layer thereon that physically secure and electrically connect the at least one printable electronic component to the anchor area, and are configured to be preferentially fractured responsive to pressure applied thereto. Related methods of fabrication and testing are also discussed. | 12-31-2015 |
| 20160013176 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE | 01-14-2016 |
| 20160013377 | LIGHT EMITTING DEVICE PACKAGE | 01-14-2016 |
| 20160020158 | Systems and Methods for Self Test Circuit Security - The present inventions are related to systems and methods for circuit implementation, and more particularly to systems and methods for securing data in a circuit. | 01-21-2016 |
| 20160020159 | SEMICONDUCTOR DEVICE HAVING TEST STRUCTURE - A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures. | 01-21-2016 |
| 20160020425 | ELECTRICAL DEVICE, IN PARTICULAR ORGANIC LIGHT EMITTING DEVICE - The invention relates to an electrical device comprising an electrical unit ( | 01-21-2016 |
| 20160026053 | DISPLAY DEVICE - A display surface where a plurality of source lines are arrayed thereon and each receives a video signal; and an inspection wiring portion that transmits an inspection signal to the source lines. The inspection wiring portion includes a first conductive layer connected to a part of the source lines, a second conductive layer connected to another part of the source lines, and an insulating portion that insulates the first conductive layer and the second conductive layer, and the second conductive layer is laminated on the first conductive layer. | 01-28-2016 |
| 20160027800 | MOTHERBOARD, ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - An array substrate and a fabrication method thereof, a display device including the array substrate and a motherboard including the array substrate are provided. The array substrate includes a pixel region and a peripheral wiring region. The peripheral wiring region includes a transparent conductive contact electrode disposed on a base substrate. The transparent conductive contact electrode is electrically connected with a metal electrode line disposed below the transparent conductive contact electrode through via holes disposed in different insulating layers, and the via holes disposed in different insulating layers do not overlap with each other in a projection direction. | 01-28-2016 |
| 20160033558 | CURRENT SENSING USING A METAL-ON-PASSIVATION LAYER ON AN INTEGRATED CIRCUIT DIE - A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a flip-chip semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are electrically connected to a first leadframe portion and a second leadframe portion of the semiconductor package where the first leadframe portion and the second leadframe portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor. | 02-04-2016 |
| 20160041433 | ELECTRODE STRUCTURE AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - An electrode structure comprises an introduction electrode and a body electrode, and a first isolating layer and a second isolating layer arranged between the introduction electrode and the body electrode. A first via hole is formed in the first isolating layer, a second via hole is formed in the second isolating layer. The hole axes of the first via hole and the second via hole are on the same straight line passing through the body electrode, so that a part of the body electrode is exposed via the first and the second via holes. The introduction electrode is electrically connected with the body electrode through the part of the body electrode. The diameter of the first via hole is smaller than that of the second via hole, and the first isolating layer extends to completely cover the hole wall of the second via hole. | 02-11-2016 |
| 20160043009 | Power Semiconductor Module - A power semiconductor module, including a housing and a substrate having at least one conductive path is located, at least one power semiconductor device arranged on said conductive path at least one contact, a self-sustaining system for detecting a physical parameter or a chemical substance, a device for wireless transmitting data provided by the sensor, and an energy source. The sensor detects at least one of current, voltage magnetic fields, mechanical stress, and humidity. The power semiconductor module may be part of an electronic device. | 02-11-2016 |
| 20160043010 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a display area, a test pad, a plurality of first test transistors, and at least one outline. The display area includes pixels coupled to data lines and scan lines. The test pad receives a test signal. The first test transistors are coupled between the data lines of the display area and the test pad. The at least one outline is coupled between one of the first test transistors and the test pad. The at least one outline is located in a non-display area outside the display area. | 02-11-2016 |
| 20160043011 | APPARATUS AND METHOD TO MONITOR DIE EDGE DEFECTS - Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a semiconductor die, the wire extending substantially along a perimeter of the semiconductor die; and one or more diodes, coupled at various sections of the wire, and positioned along the perimeter of the semiconductor die and surrounding the semiconductor die. | 02-11-2016 |
| 20160043026 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate including connection pads, a first semiconductor, and conductive wires. The first semiconductor chip is stacked on the substrate and includes bonding pads, non-bonding pads, and a routing area that is provided adjacent a center of an edge of the first semiconductor chip. The conductive wires are connected to the bonding pads and the connection pads. The bonding pads are disposed to form at least one column in a direction extending along the edge of the first semiconductor chip and are not disposed in the routing area. The non-bonding pads are disposed to form a column different from the at least one column formed by the bonding pads. | 02-11-2016 |
| 20160043059 | MULTI-CHIP SEMICONDUCTOR APPARATUS - A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip. | 02-11-2016 |
| 20160049340 | STRESS SENSOR FOR A SEMICONDUCTOR DEVICE - In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data. | 02-18-2016 |
| 20160049341 | INTEGRATED CIRCUIT CHIP WITH CORRECTED TEMPERATURE DRIFT - An integrated circuit chip includes trenches at least partially surrounding a critical portion of a circuit that is sensitive to temperature variations. The trenches are locally interrupted in order to permit circuit connections to pass between the critical portion and an outer portion containing a remainder of the circuit. The critical portion includes heating resistors and a temperature sensor. | 02-18-2016 |
| 20160056138 | VERTICAL SENSE DEVICES IN VERTICAL TRENCH MOSFET - Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand. | 02-25-2016 |
| 20160064295 | TEST KEY ARRAY - The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern. | 03-03-2016 |
| 20160064296 | MARKER PATTERN FOR ENHANCED FAILURE ANALYSIS RESOLUTION - A marker pattern for enhancing resolution of a defect location along an axis in semiconductor defect analysis, and in particular, a marker pattern providing greater resolution in locating bit line defects using thermal laser stimulation methods such as OBIRCH. In an example, the marker pattern may consist of large markers, each having a set of associated small markers. Each of the small markers may be offset along an axis from each other. By identifying the small marker and its associated large marker which align with the defect, the bit line containing the defect may be more easily identified. | 03-03-2016 |
| 20160071962 | SYMMETRICAL LATERAL BIPOLAR JUNCTION TRANSISTOR AND USE OF SAME IN CHARACTERIZING AND PROTECTING TRANSISTORS - A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric. | 03-10-2016 |
| 20160079132 | DIE TESTING USING TOP SURFACE TEST PADS - Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size. | 03-17-2016 |
| 20160079139 | SEMICONDUCTOR DEVICE - A semiconductor device includes an AC coupling element, and a temperature monitoring unit that outputs a temperature monitor signal, the temperature monitoring unit has a first temperature monitoring element that outputs the temperature monitor signal, and the first temperature monitoring element is arranged in a region immediately below or a region adjacent to the AC coupling element. | 03-17-2016 |
| 20160085904 | SEMICONDUCTOR HAVING CROSS COUPLED STRUCTURE AND LAYOUT VERIFICATION METHOD THEREOF - A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters. | 03-24-2016 |
| 20160087094 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a main cell region and a sense cell region. A separation trench separating a main second semiconductor region from a sense second semiconductor region is provided in an upper surface of the semiconductor substrate. The semiconductor substrate includes a separation fourth semiconductor region being of a second conductivity type and separated from the main second semiconductor region and the sense second semiconductor substrate by a third semiconductor region. | 03-24-2016 |
| 20160093714 | ION IMPLANTATION METHODS AND STRUCTURES THEREOF - A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. By way of example, a first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. In various examples, an interstitial cluster is formed within the group of fins and within the test structure. In some embodiments, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure. | 03-31-2016 |
| 20160099188 | Semiconductor Device with Sensor Potential in the Active Region - A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region. The semiconductor device further includes: a first load contact structure included in the surface region and arranged for feeding a load current into the semiconductor body region; a first trench extending into the semiconductor body region and having a sensor electrode and a first dielectric, the first dielectric electrically insulating the sensor electrode from the second semiconductor region; an electrically conductive path electrically connecting the sensor electrode to the first semiconductor region; a first semiconductor path, wherein the first semiconductor region is electrically coupled to the first load contact structure by at least the first semiconductor path; a sensor contact structure included in the surface region and arranged for receiving an electrical potential of the sensor electrode. | 04-07-2016 |
| 20160111381 | SEMICONDUCTOR STRUCTURE INCLUDING A DIE SEAL LEAKAGE DETECTION MATERIAL, METHOD FOR THE FORMATION THEREOF AND METHOD INCLUDING A TEST OF A SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture. | 04-21-2016 |
| 20160124039 | Edge Damage Inspection - A power semiconductor device includes a semiconductor body. The semiconductor body includes an active semiconductor region and a perimeter semiconductor region surrounding the active semiconductor region. The active semiconductor region has an active surface area, and the perimeter semiconductor region has a perimeter surface area. The power semiconductor device further includes a test structure for contactless testing of the perimeter semiconductor region. The test structure includes an electrically conductive path mounted on the perimeter surface area. The test structure is configured to extract energy from a remotely generated electromagnetic radio frequency test field. | 05-05-2016 |
| 20160126151 | METHOD FOR PRODUCING A PLURALITY OF MEASUREMENT REGIONS ON A CHIP, AND CHIP WITH MEASUREMENT REGIONS - A a chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in which, in order to reliably separate the individual measurement regions from one another, a monolayer of a fluorosilane is formed on the chip surface which has strongly hydrophobic properties. Therefore, during spotting with a liquid, the drops of liquid applied by spotting can be reliably prevented from coalescing, and thus, causing mixing of the substances in the drops of liquid which are supposed to be immobilized in the measurement regions. | 05-05-2016 |
| 20160126152 | TEST STRUCTURE FOR DETERMINING OVERLAY ACCURACY IN SEMICONDUCTOR DEVICES USING RESISTANCE MEASUREMENT - Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns. | 05-05-2016 |
| 20160133531 | TEST STRUCTURE FOR MONITORING LINER OXIDATION - Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device. | 05-12-2016 |
| 20160133582 | DEVICE FOR DETECTING A LASER ATTACK IN AN INTEGRATED CIRCUIT CHIP - A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate. | 05-12-2016 |
| 20160133607 | SEMICONDUCTOR SYSTEM - A semiconductor system may include first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad. | 05-12-2016 |
| 20160141251 | WAFER WITH DIE MAP - Embodiments of the invention provide a semiconductor wafer with information for detecting a die attach pick error on the semiconductor wafer. The semiconductor wafer has a plurality of electrical chips. The semiconductor wafer also has a die map with a plurality of locations of a set of pre-selected check good electrical chips (CGEC) die from the plurality of electrical chips on the semiconductor wafer and flat edge orientation marker. A reference feature located in a predetermined area of the semiconductor wafer. A reference die is located in a known spatial relationship to the reference feature. The die map is defined relative to the location of the reference die on the semiconductor wafer. | 05-19-2016 |
| 20160146878 | Electronic Assembly for Prognostics of Solder Joint - The problem to be solved by the present invention is to provide a substrate for providing early warning of degradation in a semiconductor device. | 05-26-2016 |
| 20160148884 | MEMORY APPARATUS HAVING POWER PAD - A memory apparatus includes a pad, an internal circuit that is connected with the pad, a power connection unit connected with power meshes, and a first switching unit suitable for selectively connecting the pad with the power connection unit based on a package control signal. | 05-26-2016 |
| 20160148905 | SEMICONDUCTOR CHIP FOR SENSING TEMPERATURE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information. | 05-26-2016 |
| 20160149088 | COMPACT EMITTER FOR WARM DIMMING AND COLOR TUNABLE LAMP - A substrate for an LED emitter includes a body with a recess region formed therein. Bonding pads are disposed within the recess region, including LED bonding pads for LEDs and supporting chip bonding pads for one or more semiconductor chips that provide supporting circuitry (e.g., driver and/or controller circuitry) to support operation of the LEDs. External electrical contacts can be disposed outside the recess region. Electrical paths, disposed at least partially within the body of the substrate, connect the external electrical contacts to a first subset of the supporting chip bonding pads and connect a second subset of the supporting chip bonding pads to the plurality of LED bonding pads such that one or more supporting chips connected to the controller pads can be operated to deliver different operating currents to different ones of the LEDs. | 05-26-2016 |
| 20160152466 | MICROMECHANICAL SENSOR DEVICE AND CORRESPONDING MANUFACTURING METHOD | 06-02-2016 |
| 20160155677 | Semiconductor device and method of manufacturing a semiconductor device | 06-02-2016 |
| 20160155712 | SEMICONDUCTOR CHIP | 06-02-2016 |
| 20160155724 | SEMICONDUCTOR DEVICES HAVING STACKED STRUCTURES AND METHODS FOR FABRICATING THE SAME | 06-02-2016 |
| 20160163608 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad; and a chip bump including a first bump provided between the package substrate and the connection pad and a second bump provided between the package substrate and the measurement pad. An interconnection disposed within the package substrate is not connected to the second bump to be electrically isolated from the second bump. | 06-09-2016 |
| 20160163656 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having an element; a front surface electrode connected to the element; a rear surface electrode connected to the element; a protective film disposed on the front surface of the semiconductor substrate in a separation region; and a temperature sensor disposed on a front surface side of the semiconductor substrate. The front surface electrode is divided into multiple pieces along at least two directions with the protective film. The separation region includes an opposing region located between opposing sides of divided pieces of the front surface electrode adjacent to each other, and an intersection region, at which the opposing region intersects. The temperature sensor is disposed in only the opposing region. | 06-09-2016 |
| 20160172333 | Integrated Circuit Package and Methods of Forming Same | 06-16-2016 |
| 20160172335 | SEMICONDUCTOR DEVICE | 06-16-2016 |
| 20160187732 | ARRAY SUBSTRATE, MANUFACTURE METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY DEVICE - An array substrate, a manufacture method thereof, and a liquid crystal display device (LCD) are provided. The array substrate includes a substrate; and a plurality of sub-pixel units disposed on the substrate. The sub-pixel unit comprises a thin film transistor (TFT), a pixel electrode, a common electrode and a passivation layer. The thin film transistor comprises an active layer, a gate electrode, a source electrode and a drain electrode, The drain electrode is electrically connected with the pixel electrode. The passivation layer covers the source electrode, the drain electrode and the pixel electrode. The sub-pixel unit further includes a test electrode which is electrically connected with the pixel electrode and is exposed at an external surface of the sub-pixel unit. With the test electrode, electrical characteristics of the TFT can be tested conveniently, and the quality level of the LCD device can also be improved. | 06-30-2016 |
| 20160190084 | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT PACKAGE AND APPARATUS PRODUCED THEREBY - A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via. | 06-30-2016 |
| 20160194199 | Method and Apparatus for a Seal Ring Structure | 07-07-2016 |
| 20160197020 | FILM FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE USING FILM AND DISPLAY DEVICE INCLUDING THE SAME | 07-07-2016 |
| 20160197021 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 07-07-2016 |
| 20160197047 | INTEGRATED CIRCUIT WITH SENSOR AND METHOD OF MANUFACTURING SUCH AN INTEGRATED CIRCUIT | 07-07-2016 |
| 20160197050 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | 07-07-2016 |
| 20160197056 | Die and Manufacturing Method for a Die | 07-07-2016 |
| 20160203938 | INTEGRATED DEVICES WITH PHOTOEMISSIVE STRUCTURES | 07-14-2016 |
| 20160204045 | 3D TAP & SCAN PORT ARCHITECTURES | 07-14-2016 |
| 20160204098 | GATE DIELECTRIC PROTECTION FOR TRANSISTORS | 07-14-2016 |
| 20160254201 | SEMICONDUCTOR TEST PAD WITH STACKED THIN METAL SHEETS AND METHOD FOR MANUFACTURING THE SAME | 09-01-2016 |
| 20160254202 | Array Formed From A Multiplicity Of Electric Integrated Circuits, and Method For Production Thereof | 09-01-2016 |
| 20160379906 | DISPLAY DEVICE AND METHOD OF TESTING THE SAME - A display device includes a display panel with signal wire pads connected to data lines; an integrated circuit (IC) that feeds a data voltage to the data lines; a multiplexer disposed on a substrate of the display panel, between the data lines and the integrated circuit; a flexible circuit board bonded onto the substrate of the display panel and connected to the signal wire pads; and a test circuit on the substrate of the display panel. | 12-29-2016 |
| 20160379907 | DISPLAY DEVICE - A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device. | 12-29-2016 |
| 20160379966 | POWER PACKAGE WITH INTEGRATED MAGNETIC FIELD SENSOR - A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a magnetic field sensor integrated in the same power semiconductor package as the power semiconductor die and positioned in close proximity to a current pathway of the power semiconductor die. The magnetic field sensor is operable to generate a signal in response to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to the amount of current flowing in the current pathway. | 12-29-2016 |
| 20170236908 | SEMICONDUCTOR DEVICE | 08-17-2017 |
| 20180024159 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME | 01-25-2018 |
| 20180025954 | TOP CONTACT RESISTANCE MEASUREMENT IN VERTICAL FETS | 01-25-2018 |
| 20180026013 | MEMORY DEVICE INCLUDING INTERPOSER AND SYSTEM-IN-PACKAGE INCLUDING THE SAME | 01-25-2018 |
| 20190148247 | NITRIDE SEMICONDUCTOR LAMINATE, METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAMINATE, METHOD FOR MANUFACTURING SEMICONDUCTOR LAMINATE, AND METHOD FOR INSPECTING SEMICONDUCTOR LAMINATE | 05-16-2019 |
| 20190148249 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, AND TEST METHOD FOR SEMICONDUCTOR CHIP | 05-16-2019 |
| 20190148343 | Structure and Formation Method for Chip Package | 05-16-2019 |
| 20190148347 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 05-16-2019 |
| 20220139790 | SEMICONDUCTOR DEVICE WITH TESTING STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first testing area, a word line structure positioned in the first testing area and arranged parallel to a first axis, a first column of capacitor contact structures positioned in the first testing area and arranged parallel to a second axis perpendicular to the first axis, a second column of capacitor contact structures positioned adjacent to the first column of capacitor contact structures and arranged parallel to the first column of capacitor contact structures, and a first testing structure including a first drain portion extended along the second axis and a first source portion extended along the second axis. The first drain portion is positioned on the first column of capacitor contact structures and the first source portion is positioned on the second column of capacitor contact structures. | 05-05-2022 |
| 20220140020 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a driving backplane, a plurality of detection pads, a light emitting function layer, and a flexible circuit board. The driving backplane has a pixel driving region and a peripheral region, and the peripheral region has bonding pads; an edge of the driving backplane is surrounded by a first section and a second section, and the bonding pads are located between the first section and the pixel driving region; a plurality of detection pads are disposed in and distributed along the second section; a light emitting function layer is disposed on the driving backplane and located in the pixel driving region; a flexible circuit board extends between the first section and the pixel driving region, and is bonded to the bonding pads; a first packaging layer is disposed on the light emitting function layer. | 05-05-2022 |
