Class / Patent application number | Description | Number of patent applications / Date published |
257026000 | Ballistic transport device | 76 |
20100320445 | Separation method of nitride semiconductor layer, semiconductor device, manufacturing method thereof, semiconductor wafer, and manufacturing method thereof - In a separation method of a nitride semiconductor layer, a graphene layer in the form of a single layer or two or more layers is formed on a surface of a first substrate. A nitride semiconductor layer is formed on the graphene layer so that the nitride semiconductor layer is bonded to the graphene layer with a bonding force due to regularity of potential at atomic level at an interface therebetween without utilizing covalent bonding. The nitride semiconductor layer is separated from the first substrate with a force which is greater than the bonding force between the nitride semiconductor layer and the graphene layer, or greater than a bonding force between respective layers of the graphene layer. | 12-23-2010 |
20110108805 | ELECTRONIC DEVICE, LIGHT-RECEIVING AND LIGHT-EMITTING DEVICE, ELECTRONIC INTEGRATED CIRCUIT AND OPTICAL INTEGRATED CIRCUIT USING THE DEVICES - Provided are an electronic device and a light-receiving and light-emitting device which can control the electron configuration of a graphene sheet and the band gap thereof, and an electronic integrated circuit and an optical integrated circuit which use the devices. By shaping the graphene sheet into a curve, the electron configuration thereof is controlled. The graphene sheet can be shaped into a curve by forming the sheet on a base film having a convex structure or a concave structure. The local electron states in the curved part can be formed by bending the graphene sheet. Thus, the same electron states as the cylinder or cap part of a nanotube can be realized, and the band gaps at the K points in the reciprocal lattice space can be formed. | 05-12-2011 |
20110309335 | UNIPOLAR HETEROJUNCTION DEPLETION-LAYER TRANSISTOR - A depletion-layer transistor comprising a base, an emitter and a collector, in which the emitter contains a tunnel diode which permits a tunnel current of charge carriers from the emitter in the direction of the collector when an emitter-base voltage above a first threshold voltage is applied in the direction of current flow, and in which the base contains a graphene layer. | 12-22-2011 |
20120193610 | METHODS OF MAKING HETEROJUNCTION DEVICES - The present invention provides a graphene/oxide semiconductor Schottky junction device, a graphene/oxide semiconductor p-n heterojunction device, and fabrication methods thereof. The Schottky junction device comprises graphene vapor-deposited directly on thin films, nanowires, nanotubes, nanobelts or nanoparticles. The p-n heterojunction device is manufactured by doping the graphene of the Schottky junction device so as to convert the graphene into a semiconductor. | 08-02-2012 |
20120305891 | GRAPHENE CHANNEL TRANSISTORS AND METHOD FOR PRODUCING SAME - Embodiments of graphene channel transistors and methods for producing same are provided herein. In some embodiments, a graphene channel transistor may include a substrate a having a source region, a drain region, and a dielectric material disposed between the source and drain regions; a channel region comprising a graphene layer disposed atop the dielectric material and partially atop the source and drain regions; and a composite gate electrode comprising an insulator layer disposed atop the graphene layer and a conductive layer disposed atop the insulator layer. | 12-06-2012 |
20130037780 | Apparatus and Associated Methods - An apparatus including a first layer configured to enable a flow of charge carriers from a source electrode to a drain electrode, a second layer configured to control the density of charge carriers in the first layer using an electric field formed between the first and second layers, and a third layer positioned between the first and second layers to shield the first layer from the electric field, wherein the third layer includes a layer of electrically conducting nanoparticles and is configured such that when stress is applied to the third layer, the strength of the electric field experienced by the first layer is varied resulting in a change in the charge carrier density and a corresponding change in the conductance of the first layer. | 02-14-2013 |
20130248822 | Broadband Polymer Photodetectors Using Zinc Oxide Nanowire as an Electron-Transporting Layer - A polymer photodetector has an inverted device structure that includes an indium-tin-oxide (ITO) cathode that is separated from an anode by an active layer. The active layer is formed as a composite of conjugated polymers, such as PDDTT and PCBM. IN addition, a cathode buffer layer formed as an matrix of ZnO nanowires is disposed upon the ITO cathode, while a MoO | 09-26-2013 |
20130285016 | EPITAXIAL STRUCTURE - An epitaxial structure is provided. The epitaxial structure includes a substrate, an epitaxial layer and a graphene layer. The epitaxial layer is located on the substrate. The graphene layer is located between the substrate and the epitaxial layer. The graphene layer can be a graphene film or graphene powder. The epitaxial structure can be made by: providing a substrate having an epitaxial growth surface, placing a graphene layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. | 10-31-2013 |
20130334497 | NANOWIRE EPITAXY ON A GRAPHITIC SUBSTRATE - A composition of matter comprising at least one nanowire on a graphitic substrate, said at least one nanowire having been grown epitaxially on said substrate, wherein said nanowire comprises at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group (IV) element. | 12-19-2013 |
20140070168 | ELECTRONIC COMPONENT, METHODS FOR MANUFACTURING THE SAME AND USE OF GRAPHENE IN AN ELECTRONIC COMPONENT - The electronic component comprises at least two superposed conducting or semiconducting layers. According to one aspect of the invention, it comprises at least graphene layer interposed between the conducting or semiconducting layers, the conducting or semiconducting layers being electronically coupled through the thickness of said or each graphene layer. Application notably to tunnel junctions either magnetic or not, to spin valves, to memristors. | 03-13-2014 |
20140158986 | Highly Conductive Nano-structures incorporated in Semiconductor Nanocomposites - The presently claimed invention provides a highly conductive composite used for electric charge transport, and a method for fabricating said composite. The composite comprises a plurality of one-dimensional semiconductor nanocomposites and highly conductive nanostructures, and the highly conductive nanostructures are incorporated into each of the one-dimensional semiconductor nanocomposite. The composite is able to provide fast electric charge transport, and reduce the rate of electron-hole recombination, ultimately increasing the power conversion efficiency for use in solar cell; provide fast electrons transport, storage of electrons and large surface area for adsorption and reaction sites of active molecular species taking part in photocatalytic reaction; enhance the sensitivity of a surface for biological and chemical sensing purposes for use in biological and chemical sensors; and lower the impedance and increase the charge storage capacity of a lithium-ion battery. | 06-12-2014 |
20140246650 | NANOSTRUCTURED DEVICE - A nanostructured device according to the invention comprises a first group of nanowires protruding from a substrate where each nanowire of the first group of nanowires comprises at least one pn- or p-i-n-junction. A first contact, at least partially encloses and is electrically connected to a first side of the pn- or p-i-n- junction of each nanowire in the first group of nanowires. A second contacting means comprises a second group of nanowires that protrudes from the substrate, and is arranged to provide an electrical connection to a second side of the pn- or p-i-n-junction. | 09-04-2014 |
20140284552 | GRAPHENE BASE TRANSISTOR WITH REDUCED COLLECTOR AREA - A graphene base transistor with reduced collector area comprising an electron injection region, an electron collection region, and a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith. | 09-25-2014 |
20150028288 | Synthesis of CdSe/ZnS Core/Shell Semiconductor Nanowires - The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, CdSe/ZnS core/shell nanowires, as well as a method of preparation thereof. The disclosure also provides a new continuous flow method of preparing core/shell nanowires, including CdSe/CdS core/shell nanowire and CdSe/ZnS core/shell nanowires. | 01-29-2015 |
20150034907 | GATE-TUNABLE P-N HETEROJUNCTION DIODE, AND FABRICATION METHOD AND APPLICATION OF SAME - One aspect of the invention relates to a gate-tunable p-n heterojunction diode including a vertical stacked heterojunction of two ultrathin semiconductors. In one embodiment, single-layer molybdenum disulphide of an n-type semiconductor are stacked below semiconducting single-walled carbon nanotubes of a p-type semiconductor with each of them connected to a gold electrodes to form a p-n heterojunction. The electrical properties of the p-n heterojunction can be modulated by a gate voltage applied to a gate electrode and range from an insulator to a linear-response resistor to a highly rectifying diode. The gate tunability of the p-n heterojunction also allows spectral control over the photoresponse. | 02-05-2015 |
20150102287 | NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN - A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region. | 04-16-2015 |
20150144881 | DIRECT AND SEQUENTIAL FORMATION OF MONOLAYERS OF BORON NITRIDE AND GRAPHENE ON SUBSTRATES - The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer. | 05-28-2015 |
20150332920 | ELECTRONIC DEVICE HAVING GRAPHENE-SEMICONDUCTOR MULTI-JUNCTION AND METHOD OF MANUFACTURING THE ELECTRONIC DEVICE - Example embodiments relate to an electronic device having a graphene-semiconductor multi-junction and a method of manufacturing the electronic device. The electronic device includes a graphene layer having at least one graphene protrusion and a semiconductor layer that covers the graphene layer. A side surface of each of the at least one graphene protrusion may be uneven, may have a multi-edge, and may be a stepped side surface. The graphene layer includes a plurality of nanocrystal graphenes. The graphene layer includes a lower graphene layer having a plurality of nanocrystal graphenes and the at least one graphene protrusion that is formed on the lower graphene layer. The semiconductor layer may include a transition metal dichalcogenide (TMDC) layer. Each of the at least one graphene protrusion may include a plurality of nanocrystal graphenes. | 11-19-2015 |
20150349184 | PHOTOSENSING DEVICE WITH GRAPHENE - A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light. | 12-03-2015 |
20150349185 | PHOTOSENSING DEVICE WITH GRAPHENE - A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light. | 12-03-2015 |
20150364614 | Detector - A detector is described comprising a first graphene element ( | 12-17-2015 |
20160064474 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate doped with a first conductive type;
| 03-03-2016 |
20160064489 | GROWTH OF SEMICONDUCTORS ON HETERO-SUBSTRATES USING GRAPHENE AS AN INTERFACIAL LAYER - Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth. | 03-03-2016 |
20160087087 | METHOD OF MAKING A GRAPHENE BASE TRANSISTOR WITH REDUCED COLLECTOR AREA - A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region. | 03-24-2016 |
257027000 | Field effect transistor | 52 |
20090134382 | MULTILEVEL LOGIC BALLISTIC DEFLECTION TRANSISTOR - A multilevel logic transistor including a ballistic channel, the ballistic channel formed in a substrate layer and configured to receive a flow of electrons generated by an emitter, a deflection barrier, the deflection barrier comprising at least two deflection surfaces and a deflection channel, and a deflection controller, the deflection controller configured to generate an electrical biasing field for directing the flowed of electrons, wherein the deflection barrier is positioned in the ballistic channel such that the deflection barrier is in the path of the received electrons. The multilevel logic transistor can further include an electron spin controller configured to generate a particular spin on each electron in the flow of electrons. | 05-28-2009 |
20110042649 | Thin-Film Transistor, Carbon-Based Layer and Method of Producing Thereof - The present invention relates to a thin-film transistor which comprises a conductive and predominantly continuous carbon-based layer ( | 02-24-2011 |
20110101308 | Utilization of Organic Buffer Layer to Fabricate High Performance Carbon Nanoelectronic Devices - A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide. | 05-05-2011 |
20110253983 | SIDEWALL GRAPHENE DEVICES FOR 3-D ELECTRONICS - A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device. | 10-20-2011 |
20120097923 | GRAPHENE DEVICE AND METHOD FOR MANUFACTURING THE SAME - The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices. | 04-26-2012 |
20120235118 | NITRIDE GATE DIELECTRIC FOR GRAPHENE MOSFET - A semiconductor structure which includes a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode; and a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode. | 09-20-2012 |
20120235119 | Method to Improve Nucleation of Materials on Graphene and Carbon Nanotubes - Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material. | 09-20-2012 |
20120256167 | GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer. | 10-11-2012 |
20120256168 | Semiconductor Devices And Methods Of Manufacturing The Same - According to example embodiments, a semiconductor device includes a first electrode, a second electrode apart from the first electrode, and an active layer between the first and second electrodes. The active layer includes first and second layers, the first layer contacts the first and second electrodes, and the second layer is separated from at least one of the first and second electrodes. | 10-11-2012 |
20120261643 | GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES - Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed. | 10-18-2012 |
20120298959 | LINE-TUNNELING TUNNEL FIELD-EFFECT TRANSISTOR (TFET) AND MANUFACTURING METHOD - A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gat electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions. | 11-29-2012 |
20120298960 | Hetero-Junction Tunneling Transistor - A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers. | 11-29-2012 |
20120298961 | CONTROL OF TUNNELING JUNCTION IN A HETERO TUNNEL FIELD EFFECT TRANSISTOR - A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current. | 11-29-2012 |
20120298962 | Utilization of Organic Buffer Layer to Fabricate High Performance Carbon Nanoelectronic Devices - A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide. | 11-29-2012 |
20120298963 | STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET - A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region. | 11-29-2012 |
20130032784 | THIN FILM TRANSISTOR INCLUDING A NANOCONDUCTOR LAYER - A thin film transistor having a channel region including a nanoconductor layer. The nanoconductor layer can be a dispersed monolayer of nanotubes or nanowires formed of carbon. The thin film transistor generally includes a gate terminal insulated by a dielectric layer. The nanoconductor layer is placed on the dielectric layer and a layer of semiconductor material is developed over the nanoconductor layer to form the channel region of the thin film transistor. A drain terminal and a source terminal are then formed on the semiconductor layer. At low field effect levels, the operation of the thin film transistor is dominated by the semiconductor layer, which provides good leakage current performance. At high field effect levels, the charge transfer characteristics of the channel region are enhanced by the nanoconductor layer such that the effective mobility of the thin film transistor is enhanced. | 02-07-2013 |
20130048948 | INVERTER LOGIC DEVICES INCLUDING GRAPHENE FIELD EFFECT TRANSISTOR HAVING TUNABLE BARRIER - Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer. | 02-28-2013 |
20130075700 | Electrode Structure Including Graphene And Field Effect Transistor Having The Same - According to example embodiments, an electrode structure includes a graphene layer on a semiconductor layer and an electrode containing metal on the graphene layer. A field effect transistor (FET) may include the electrode structure. | 03-28-2013 |
20130105764 | TUNNELING FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD FOR FORMING THE SAME | 05-02-2013 |
20130146846 | GRAPHENE FIELD EFFECT TRANSISTOR - Manufacturing a semiconductor structure including: forming a seed material on a sidewall of a mandrel; forming a graphene field effect transistor (FET) on the seed material; and removing the seed material. | 06-13-2013 |
20130285017 | STRAINED CHANNEL REGION TRANSISTORS EMPLOYING SOURCE AND DRAIN STRESSORS AND SYSTEMS INCLUDING THE SAME - Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons. | 10-31-2013 |
20140001440 | DIELECTRIC FOR CARBON-BASED NANO-DEVICES | 01-02-2014 |
20140021445 | GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer. | 01-23-2014 |
20140034908 | Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width - Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls. | 02-06-2014 |
20140048773 | Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices - A nanowire FET device includes a SOI wafer having a SOI layer over a BOX, and a plurality of nanowires and pads patterned in the SOI layer, wherein the nanowires are suspended over the BOX; an interfacial oxide surrounding each of the nanowires; and at least one gate stack surrounding each of the nanowires, the gate stack having (i) a conformal gate dielectric present on the interfacial oxide (ii) a conformal first gate material on the conformal gate dielectric (iii) a work function setting material on the conformal first gate material, and (iv) a second gate material on the work function setting material. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires. | 02-20-2014 |
20140054549 | GATED CIRCUIT STRUCTURE WITH ULTRA-THIN, EPITAXIALLY-GROWN TUNNEL AND CHANNEL LAYER - A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer. | 02-27-2014 |
20140091279 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING GERMANIUM-BASED ACTIVE REGION WITH RELEASE ETCH-PASSIVATION SURFACE - Non-planar semiconductor devices having germanium-based active regions with release etch-passivation surfaces are described. For example, a semiconductor device includes a vertical arrangement of a plurality of germanium-rich nanowires disposed above a substrate. Each nanowire includes a channel region having a sulfur-passivated outer surface. A gate stack is disposed on and completely surrounds the channel region of each of the germanium-rich nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the sulfur-passivated outer surface and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the germanium-rich nanowires. | 04-03-2014 |
20140097403 | TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING GRAPHENE CHANNEL - According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate. | 04-10-2014 |
20140131661 | GRAPHENE FIELD EFFECT TRANSISTOR - Manufacturing a semiconductor structure including: forming a seed material on a sidewall of a mandrel; forming a graphene field effect transistor (FET) on the seed material; and removing the seed material. | 05-15-2014 |
20140151638 | HYBRID NANOMESH STRUCTURES - An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The second semiconductor material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the first semiconductor material, and the first semiconductor material is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the second semiconductor material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires. | 06-05-2014 |
20140151639 | NANOMESH COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS - An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The germanium-free silicon material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the silicon-germanium alloy, and the silicon-germanium alloy is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the germanium-free silicon material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires. | 06-05-2014 |
20140264279 | FACETED SEMICONDUCTOR NANOWIRE - Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics. | 09-18-2014 |
20140291616 | COMPOUND TUNNELING FIELD EFFECT TRANSISTOR INTEGRATED ON SILICON SUBSTRATE AND METHOD FOR FABRICATING THE SAME - Compound tunneling field effect transistors integrated on a silicon substrate are provided with increased tunneling efficiency and an abrupt band slope by forming a source region with a material having a bandgap at least 0.4 electron volts (eV) narrower than that of silicon to increase a driving current (ON current) by forming a channel region with a material having almost no difference in lattice constant from a source region and having a high electron mobility at least 5 times higher than silicon. ON/OFF current ratio simultaneously is increased by forming a drain region with a material having a bandgap at least as wide as a channel region material to restrain OFF current. Tunneling field effect transistors having various threshold voltages according to circuit designs are formed easily by adding a specific material with an electron affinity less than a source region material when forming a channel region. | 10-02-2014 |
20140299838 | TRANSISTORS, METHODS OF FORMING TRANSISTORS AND DISPLAY DEVICES HAVING TRANSISTORS - A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern. | 10-09-2014 |
20140319467 | FIELD-EFFECT TRANSISTOR WITH TWO-DIMENSIONAL CHANNEL REALIZED WITH LATERAL HETEROSTRUCTURES BASED ON HYBRIDIZED GRAPHENE - The invention is a field-effect transistor with a channel consisting of a thin sheet of one or more atomic layers of lateral heterostructures based on hybridized graphene. The role of lateral heterostructures is to modify the energy gap in the channel so as to enable the effective operation of the transistor in all bias regions. This solution solves the problem of the missing bandgap in single-layer and multi-layer graphene, which does not allow the fabrication of transistors that can be efficiently switched off. The possibility of fabricating lateral heterostructures, with patterns of domains with different energy dispersion relations, enables the realization of field-effect transistors with additional functionalities with respect to common transistors. | 10-30-2014 |
20140361250 | Graphene Transistor - A transistor includes a silicon carbide crystal ( | 12-11-2014 |
20150034908 | SEMICONDUCTOR GRAPHENE STRUCTURES, METHODS OF FORMING SUCH STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES - A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material, wherein the graphene-lattice matching material has a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. The semiconducting graphene structure may have an energy band gap of at least about 0.5 eV. A method of modifying an energy band gap of a graphene material may include forming a graphene-lattice matching material over at least a portion of a graphene material, the graphene-lattice matching material having a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. | 02-05-2015 |
20150053926 | GRAPHITE AND/OR GRAPHENE SEMICONDUCTOR DEVICES - Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier. | 02-26-2015 |
20150090958 | SEMICONDUCTOR DEVICE INCLUDING NANOWIRE TRANSISTOR - A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film. | 04-02-2015 |
20150137074 | GRAPHENE DEVICE INCLUDING SEPARATED JUNCTION CONTACTS AND METHOD OF MANUFACTURING THE SAME - A graphene device including separated junction contacts and a method of manufacturing the same are disclosed. The graphene device is a field effect transistor (FET) in which graphene is used as a channel. A source electrode and a drain electrode do not directly contact the graphene channel, and junction contacts formed by doping semiconductor are separately disposed between the graphene channel and the source electrode and between the graphene channel and the drain electrode. Therefore, in an off state where a voltage is not applied to a gate electrode, due to a barrier between the graphene channel and the junction contacts, carriers may not move. As a result, the graphene device may have low current in the off state. | 05-21-2015 |
20150144882 | CONTROLLED EPITAXIAL BORON NITRIDE GROWTH FOR GRAPHENE BASED TRANSISTORS - We have demonstrated controlled growth of epitaxial h-BN on a metal substrate using atomic layer deposition. This permits the fabrication of devices such as vertical graphene transistors, where the electron tunneling barrier, and resulting characteristics such as ON-OFF rate may be altered by varying the number of epitaxial layers of h-BN. Few layer graphene is grown on the h-BN opposite the metal substrate, with leads to provide a vertical graphene transistor that is intergratable with Si CMOS technology of today, and can be prepared in a scalable, low temperature process of high repeatability and reliability. | 05-28-2015 |
20150340617 | Carbon Nanotube-Graphene Hybrid Transparent Conductor and Field Effect Transistor - A nanotube-graphene hybrid nano-component and method for forming a cleaned nanotube-graphene hybrid nano-component. The nanotube-graphene hybrid nano-component includes a gate; a gate dielectric formed on the gate; a channel comprising a carbon nanotube-graphene hybrid nano-component formed on the gate dielectric; a source formed over a first region of the carbon nanotube-graphene hybrid nano-component; and a drain formed over a second region of the carbon nanotube-graphene hybrid nano-component to form a field effect transistor. | 11-26-2015 |
20150357504 | GRAPHENE TRANSISTOR OPTICAL DETECTOR BASED ON METAMATERIAL STRUCTURE AND APPLICATION THEREOF - A graphene transistor optical detector based on a metamaterial structure and an application thereof. The optical detector includes a substrate, a gate metal layer, a gate medium layer, a graphene layer, a source and drain metal layer successively arranged from bottom to top, wherein a local region of at least the source and drain metal layer has a periodic micro/nanostructure, the periodic micro/nanostructure being matched with the gate metal layer and the gate medium layer to form a metamaterial structure having a complete absorption characteristic. By changing the refractive index, thickness or the like of material for the periodic micro/nanostructure and the gate medium layer, a light absorption frequency band of the metamaterial structure can be regulated. The optical detector provided by the present invention has higher flexibility and narrow-band response, and can work under visible light to infrared even longer wavebands by selecting different metamaterial structures. | 12-10-2015 |
20160020280 | GRAPHENE DEVICE, METHODS OF MANUFACTURING AND OPERATING THE SAME, AND ELECTRONIC APPARATUS INCLUDING THE GRAPHENE DEVICE - Example embodiments relate to a graphene device, methods of manufacturing and operating the same, and an electronic apparatus including the graphene device. The graphene device is a multifunctional device. The graphene device may include a graphene layer and a functional material layer. The graphene device may have a function of at least one of a memory device, a piezoelectric device, and an optoelectronic device within the structure of a switching device/electronic device. The functional material layer may include at least one of a resistance change material, a phase change material, a ferroelectric material, a multiferroic material, multistable molecules, a piezoelectric material, a light emission material, and a photoactive material. | 01-21-2016 |
20160035849 | Strained Channel of Gate-All-Around Transistor - The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8. | 02-04-2016 |
20160043152 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND ORGANIC LIGHT EMITTING DISPLAY PANEL - A thin film transistor, a method for manufacturing the thin film transistor, an array substrate comprising the thin film transistor and an organic light emitting display panel comprising the thin film transistor are provided. The thin film transistor at least comprising an active layer made of carbon nanotube material with semiconductor properties or graphene with semiconductor properties; further comprising a first conductive layer and a second conductive layer respectively located on upper and lower sides of the active layer and in contact with the active layer, the first conductive layer and the second conductive layer formed a secondary electron emitting layer with electron multiplication function. The thin film transistor is advantageous in its simple structure and simple manufacturing process. | 02-11-2016 |
20160093806 | Heterostructure Comprising A Carbon Nanomembrane - A heterostructure comprising at least one carbon nanomembrane on top of at least one carbon layer, a method of manufacture of the heterostructure, and an electronic device, a sensor and a diagnostic device comprising the heterostructure. The heterostructure comprises at least one carbon nanomembrane on top of at least one carbon layer, wherein the at least one carbon nanomembrane has a thickness of 0.5 to 5 nm and the heterostructure has a thickness of 1 to 10 nm. | 03-31-2016 |
20160104852 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device includes: a nanocarbon material; a pair of electrodes that is electrically connected to the nanocarbon material; a lower layer that is formed under the nanocarbon material and is made of at least one kind of a molecular material having a doping function; and an upper layer that is formed on the nanocarbon material and is made of at least two kinds of molecular materials having doping functions whose polarities are reverse to each other, in which the nanocarbon material constitutes one type selected from among an NPN structure, a PNP structure, an N | 04-14-2016 |
20160141373 | SEMICONDUCTOR DEVICES INCLUDING FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME - A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity. | 05-19-2016 |
20160172507 | THIN FILM DEVICE WITH PROTECTIVE LAYER | 06-16-2016 |
20160190344 | SEMICONDUCTOR DEVICES WITH GRAPHENE NANORIBBONS - Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material. | 06-30-2016 |
20190148493 | SEMICONDUCTOR DEVICE INCLUDING METAL-2 DIMENSIONAL MATERIAL-SEMICONDUCTOR CONTACT | 05-16-2019 |