| Entries |
| Document | Title | Date |
|---|
| 20080237576 | Voltage Controlled Computing Element for Quantum Computer - A computing element for use in a quantum computer has at least three coupled quantum dots, and at least one gate for applying an electric field to manipulate the state of said qubit. | 10-02-2008 |
| 20080237577 | Forming a non-planar transistor having a quantum well channel - In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed. | 10-02-2008 |
| 20080237578 | ULTRAHIGH DENSITY PATTERNING OF CONDUCTING MEDIA - A nanoscale device and a method for creating and erasing of nanoscale conducting regions at the interface between two insulating oxides SrTiO | 10-02-2008 |
| 20080246020 | Nanowire, method for fabricating the same, and device having nanowires - A nanowire according to the present invention includes: a nanowire body made of a crystalline semiconductor as a first material; and a plurality of fine particles, which are made of a second material, including a constituent element of the semiconductor, and which are located on at least portions of the surface of the nanowire body. The surface of the nanowire body is smooth. | 10-09-2008 |
| 20080246021 | Single electron transistor and method of manufacturing the same - A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot. | 10-09-2008 |
| 20080272366 | Field effect transistor having germanium nanorod and method of manufacturing the same - A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode. | 11-06-2008 |
| 20080283824 | METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES - A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device. | 11-20-2008 |
| 20080296557 | Semiconductor Power Switch and Method for Producing a Semiconductor Power Switch - A semiconductor power switch and method is disclosed. In one embodiment the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the semiconductor structure between the source contact and the drain contact. The semiconductor structure has a plurality of nanowires which are connected in parallel and are arranged in such a manner that each nanowire forms an electrical connection between the source contact and the drain contact. | 12-04-2008 |
| 20080296558 | Method of Synthesizing Y-Junction Single-Walled Carbon Nanotubes and Products Formed Thereby - A method has been developed of synthesizing Y-SWNTs with controlled density, position, and growth direction. The process includes patterning a substrate with a solvent solution of catalyst metal ions, dopant metal ions and metal oxide ions, having in a molar ratio of catalyst to dopant in the range of 0.1 to 0.5 moles of catalyst metal per mole of dopant metal, prior to heating to 600-1200° C. with a flow of hydrocarbon gas. A Y-SWNT can be used as a building component of nanoscale two- and three-terminal electronic devices, such as interconnects, diodes, and transistors. This development has a profound impact on nanoscale semiconductor industry, since it is certain that the market share of nanoscale devices using Y-SWNTs will be increased to a great extent. | 12-04-2008 |
| 20080296559 | Method for Fabricating a Nanoelement Field Effect Transistor with Surrounded Gate Structure - A nanoelement field effect transistor includes a nanotube disposed on the substrate. A first source/drain region is coupled to a first end portion of the nanoelement and a second source/drain region is coupled to a second end portion of the nanoelement. A recess in a surface region of the substrate is arranged in such a manner that a region of the nanoelement arranged between the first and second end portions is taken out over the entire periphery of the nanoelement. A gate-insulating structure covers the periphery of the nanoelement and a gate structure covers the periphery of the gate-insulating structure. | 12-04-2008 |
| 20080315183 | SEMICONDUCTOR DEVICE WITH CARBON NANOTUBE CHANNEL AND MANUFACTURING METHOD THEREOF - A high-performance semiconductor device having a channel region structured from a carbon nanotube (CNT) for reducing or minimizing a drain leakage current is provided. This semiconductor device includes, in addition to the CNT-formed channel region, a gate electrode formed to overlie the channel region with a gate insulation film sandwiched therebetween, and a pair of source and drain regions interposing the channel region therebetween. The source and drain regions have portions in contact with the channel region, which portions are made of a specific semiconductor material that is wider in energy band gap than the channel region. | 12-25-2008 |
| 20090001352 | Non-Volatile Memory Device, Method of Manufacturing the Same, and Semiconductor Package - Provided is a non-volatile memory device that can be highly integrated and may have a high reliability. Some embodiments of the non-volatile memory device include a first doping layer having a first conductivity on a substrate, a semiconductor pillar extending from the first doping layer on the substrate in an upward direction and having second conductivity opposite to the first conductivity, and a control gate electrode surrounding a sidewall of the semiconductor pillar. Embodiments of the non-volatile memory device may include a charge storage layer interposed between the semiconductor pillar and the control gate electrode and a second doping layer of the first conductivity that is disposed on the semiconductor pillar and is electrically connected to the semiconductor pillar. | 01-01-2009 |
| 20090008629 | N-TYPE TRANSISTOR, PRODUCTION METHODS FOR N-TYPE TRANSISTOR AND N-TYPE TRANSISTOR-USE CHANNEL, AND PRODUCTION METHOD OF NANOTUBE STRUCTURE EXHIBITING N-TYPE SEMICONDUCTOR-LIKE CHARACTERISTICS - An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound | 01-08-2009 |
| 20090032803 | METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR - A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least one trench in the gate dielectric (e.g., a back gate dielectric) and back gate adjacent to the local gate electrode. Another aspect of the invention is a nanotube field-effect transistor fabricated using such a method. | 02-05-2009 |
| 20090032804 | Self-Aligned T-Gate Carbon Nanotube Field Effect Transistor Devices and Method for Forming the Same - A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature, an improved design of the gate to possess a “T”-shape, referred to as the “T-Gate,” thereby enabling a reduction in gate resistance and further providing an increased power gain. The self-aligned T-gate CNT FET is formed using simple fabrication steps to ensure a low cost, high yield process. | 02-05-2009 |
| 20090050876 | Transparent Nanowire Transistors and Methods for Fabricating Same - Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors disclosed herein also can be mechanically flexible. | 02-26-2009 |
| 20090057650 | Nanoscale wires and related devices - The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like. | 03-05-2009 |
| 20090057651 | Gated Quantum Resonant Tunneling Diode Using CMOS Transistor with Modified Pocket and LDD Implants - A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode. | 03-05-2009 |
| 20090065765 | CARBON NANOTUBE GROWN ON CATALYST AND MANUFACTURE METHOD - A method for manufacturing carbon nanotubes includes the steps of: (a) depositing catalytic fine particles containing Al—Fe, Zr—Co or Hf—Co on a base body; and (b) growing carbon nanotubes on the catalytic fine particles deposited on the base body. | 03-12-2009 |
| 20090072222 | METHOD FOR FORMING CATALYST NANOPARTICLES FOR GROWING ELONGATED NANOSTRUCTURES - Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle. According to preferred embodiments a method is also provided for forming at least one elongated nanostructure, such as e.g. a nanowire or carbon nanotube, using the catalyst nanoparticles formed by the method according to preferred embodiments as a catalyst. The methods according to preferred embodiments may be used in, for example, semiconductor processing. The methods according to preferred embodiments are scalable and fully compatible with existing semiconductor processing technology. | 03-19-2009 |
| 20090072223 | FIELD EFFECT TRANSISTOR USING CARBON NANOTUBE, METHOD OF FABRICATING SAME, AND SENSOR - A field effect transistor according to the present invention includes a carbon nanotube of two or more walls having an inner wall and an outer wall, source and drain electrodes formed on both sides of the carbon nanotube, and a gate electrode formed in a gate formation region of the carbon nanotube, wherein the outer wall of the carbon nanotube is removed in the gate formation region to expose the inner wall, an insulation film is formed on the exposed inner wall, the gate electrode is formed on the exposed inner wall via the insulation film or via a Schottky junction, the source and drain electrodes are formed in contact with the outer wall and inner wall, and the carbon nanotube between the source and drain electrodes and the insulation film is covered by the outer wall. | 03-19-2009 |
| 20090085027 | THREE DIMENSIONAL STRAINED QUANTUM WELLS AND THREE DIMENSIONAL STRAINED SURFACE CHANNELS BY GE CONFINEMENT METHOD - The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 04-02-2009 |
| 20090101889 | OPTICALLY INTERFACE ELECTRICALLY CONTROLLED DEVICES - The present invention presents devices and methods for localized control and transport of excitons as well as separate processing of holes and electrons in a device with an optical input and an optical output. In an embodiment of the invention, an optoelectronic device includes a coupled or wide quantum well structure. A localized gate is arranged over a region of the coupled or wide quantum well structure and a semiconductor barrier layer. A optical input and optical output are arranged over other regions of the coupled or wide quantum well structure that are separated by the gate electrode region. The coupled or wide quantum well structure is dimensioned and formed from materials that create a nonzero distance d between the separated electron and hole of an exciton formed in response to the input. The flow of excitons or separated electrons and holes between the optical input and optical output can be controlled by a voltage potentials applied to the localized gate electrode, optical input, and output gates. | 04-23-2009 |
| 20090114903 | Integrated Nanotube and CMOS Devices For System-On-Chip (SoC) Applications and Method for Forming The Same - An integrated, multilayer nanotube and complementary metal oxide semiconductor (CMOS) device is provided along with a method of forming the same. The device includes at least one CMOS device formed on at least one layer of the device, a first metal wiring layer that is electrically connected to the least one CMOS device, and at least one nanotube device formed over the first metal wiring layer in parasitic isolation from the at least one CMOS device. In one or more embodiments, the at least one CMOS device and the at least one nanotube device are located on different layers of a same semiconductor wafer chip to allow the wafer to be is used for system-on-chip (SoC) applications having RF/analog circuitry based on the least one nanotube device and digital circuitry based on the at least one CMOS device. | 05-07-2009 |
| 20090114904 | SEMICONDUCTOR DEVICES HAVING NANO-LINE CHANNELS - A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described. | 05-07-2009 |
| 20090127542 | NEGATIVE RESISTANCE FIELD EFFECT ELEMENT AND HIGH-FREQUENCY OSCILLATION ELEMENT - There is provided a 3-terminal negative differential resistance field effect element having a high output and high frequency characteristic, requiring low power consumption, and preferably having a high PVCR. The field effect element uses a compound hetero structure and forms a dual channel layer by connecting a high-transfer degree quantum well layer ( | 05-21-2009 |
| 20090146133 | HYBRID SEMICONDUCTOR STRUCTURE - A method for the fabrication of a semiconductor structure that includes areas that have different crystalline orientation and semiconductor structure formed thereby. The disclosed method allows fabrication of a semiconductor structure that has areas of different semiconducting materials. The method employs templated crystal growth using a Vapor-Liquid-Solid (VLS) growth process. A silicon semiconductor substrate having a first crystal orientation direction is etched to have an array of holes into its surface. A separation layer is formed on the inner surface of the hole for appropriate applications. A growth catalyst is placed at the bottom of the hole and a VLS crystal growth process is initiated to form a nanowire. The resultant nanowire crystal has a second different crystal orientation which is templated by the geometry of the hole. | 06-11-2009 |
| 20090152530 | Image sensor including photoelectric charge-trap structure - A pixel of an image sensor includes a first insulating structure, a photoelectric charge-trap structure, a second insulating structure, and a gate electrode. The first insulating structure is formed on a substrate, and the photoelectric charge-trap structure is formed on the first insulating structure. The second insulating structure is formed on the photoelectric charge-trap structure. The gate electrode is formed on the second insulating structure. The photoelectric charge-trap structure converts a significant amount of light reaching the pixel into charge carriers. | 06-18-2009 |
| 20090173935 | PREPARATION OF THIN FILM TRANSISTORS (TFT's) OR RADIO FREQUENCY IDENTIFICATION (RFID) TAGS OR OTHER PRINTABLE ELECTRONICS USING INK-JET PRINTER AND CARBON NANOTUBE INKS - The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of exiting printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques can not used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks. | 07-09-2009 |
| 20090179193 | CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT - Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array. | 07-16-2009 |
| 20090189146 | Multifinger Carbon Nanotube Field-Effect Transistor - A multifinger carbon nanotube field-effect transistor (CNT FET) is provided in which a plurality of nonotube top gated FETs are combined in a finger geometry along the length of a single carbon nanotube, an aligned array of nanotubes, or a random array of nanotubes. Each of the individual FETs are arranged such that there is no geometrical overlap between the gate and drain finger electrodes over the single carbon nanotube so as to minimize the Miller capacitance (Cgd) between the gate and drain finger electrodes. A low-K dielectric may be used to separate the source and gate electrodes in the multifinger CNT FET so as t further minimize the Miller capacitance between the source and gate electrodes. | 07-30-2009 |
| 20090200541 | MAKING A STRUCTURE - A structure includes a surface and a non-equilibrium two-dimensional semiconductor micro structure on the surface. | 08-13-2009 |
| 20090218563 | NOVEL FABRICATION OF SEMICONDUCTOR QUANTUM WELL HETEROSTRUCTURE DEVICES - A device employing a quantum well structure having a pattern that is defined by a photolithographically patterned top gate electrode. By defining the active area of the quantum well structure by the patterning of the top gate electrode there is no need to pattern the quantum well structure itself, such as by etching or other processes. This advantageously allows the active are of the quantum well structure to be patterned to a very small size, without the damaging edge effects associated with the patterning of the quantum well structure itself. | 09-03-2009 |
| 20090236588 | NANOWIRE-BASED DEVICE HAVING ISOLATED ELECTRODE PAIR - A nanowire-based device includes the pair of isolated electrodes and a nanowire bridging between respective surfaces of the isolated electrodes of the pair. Specifically, the nanowire-based device having isolated electrodes comprises: a substrate electrode having a crystal orientation; a ledge electrode that is an epitaxial semiconductor having the crystal orientation of the substrate electrode; and a nanowire bridging between respective surfaces of the substrate electrode and the ledge electrode. | 09-24-2009 |
| 20090242873 | SEMICONDUCTOR HETEROSTRUCTURES TO REDUCE SHORT CHANNEL EFFECTS - Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap. | 10-01-2009 |
| 20090250687 | SEMICONDUCTOR DEVICE AND METHOD TO CONTROL THE STATE OF A SEMICONDUCTOR DEVICE AND TO MANUFACTURE THE SAME - A semiconductor device includes a conduct structure to which are arranged contacts for a source and a drain, a resonance region including at least two barrier regions, at least one resonator between the barrier regions and a control electrode and which resonance region is arranged between the contacts. The conduct structure between the contacts is homogeneous and the barrier regions are formed of narrows arranged to the conduct structure. In addition, disclosed are methods to control the state of a semiconductor device and manufacture the same. | 10-08-2009 |
| 20090267053 | CARBON-NANOTUBE BASED OPTO-ELECTRIC DEVICE - A carbon nano-tube based photoelectric device includes a substrate and a carbon nanotube (CNT) over the substrate. The CNT comprises a first end and a second end, wherein the CNT has a CNT work function. A high work-function electrode over the substrate is in electric contact with the first end of the CNT. The high work-function electrode has a first work function higher than the CNT work function. A low work-function electrode over the substrate is in electric contact with the second end of the CNT. The low work-function electrode has a second work function lower than the CNT work function. The CNT can form a conductive channel between the high work-function electrode and the low work-function electrode. The carbon nano-tube based photoelectric device also includes a dielectric material is in contact with a side surface of the CNT and a conductive material in contact with the dielectric material. | 10-29-2009 |
| 20090272965 | Selective High-K dielectric film deposition for semiconductor device - Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer. | 11-05-2009 |
| 20090278114 | CONTROL OF CARBON NANOTUBE DIAMETER USING CVD OR PECVD GROWTH - The diameter of carbon nanotubes grown by chemical vapor deposition is controlled independent of the catalyst size by controlling the residence time of reactive gases in the reactor. | 11-12-2009 |
| 20090283751 | NANOTUBES AND DEVICES FABRICATED THEREFROM - Nanofluidic devices incorporating inorganic nanotubes fluidly coupled to channels or nanopores for supplying a fluid containing chemical or biochemical species are described. In one aspect, two channels are fluidly interconnected with a nanotube. Electrodes on opposing sides of the nanotube establish electrical contact with the fluid therein. A bias current is passed between the electrodes through the fluid, and current changes are detected to ascertain the passage of select molecules, such as DNA, through the nanotube. In another aspect, a gate electrode is located proximal the nanotube between the two electrodes thus forming a nanofluidic transistor. The voltage applied to the gate controls the passage of ionic species through the nanotube selected as either or both ionic polarities. In either of these aspects the nanotube can be modified, or functionalized, to control the selectivity of detection or passage. | 11-19-2009 |
| 20090283752 | Thin film transistor - A thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a channel and a gate electrode. The drain electrode is spaced from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The channel includes a plurality of carbon nanotube wires, one end of each carbon nanotube wire is connected to the source electrode, and opposite end of each the carbon nanotube wire is connected to the drain electrode. | 11-19-2009 |
| 20090283753 | Thin film transistor - A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is electrically connected to the source electrode and the drain electrode. The semiconductor layer comprises a plurality of carbon nanotubes. A semiconductor layer comprising a plurality of carbon nanotubes electrically connected to the source electrode and the drain electrode, the plurality of carbon nanotubes having almost the same length are substantially parallel to each other and are joined side by side via van der Waals attractive force therebetween. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. | 11-19-2009 |
| 20090283754 | Thin film transistor - A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The semiconducting layer includes at least two stacked carbon nanotube films. Each carbon nanotube film includes an amount of carbon nanotubes. At least a part of the carbon nanotubes of each carbon nanotube film are aligned along a direction from the source electrode to the drain electrode. | 11-19-2009 |
| 20090283755 | Thin film transistor - A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The semiconducting layer includes a carbon nanotube film, a plurality of carbon nanotubes in the carbon nanotube film oriented along a direction from the source electrode to the drain electrode. | 11-19-2009 |
| 20090283756 | SCALABLE QUANTUM WELL DEVICE AND METHOD FOR MANUFACTURING THE SAME - A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap. | 11-19-2009 |
| 20090289245 | FACETED CATALYTIC DOTS FOR DIRECTED NANOTUBE GROWTH - Faceted catalytic dots are used for directing the growth of carbon nanotubes. In one example, a faceted dot is formed on a substrate for a microelectronic device. A growth promoting dopant is applied to a facet of the dot using an angled implant, and a carbon nanotube is grown on the doped facet of the dot. | 11-26-2009 |
| 20090309091 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having good switching characteristics even metallic CNTs are included and a manufacturing method thereof are provided. The semiconductor device includes a source electrode; a drain electrode; and a channel layer formed between the source electrode and the drain electrode and including a carbon nanotube group. The carbon nanotube group includes conductive carbon nanotubes having a characteristic of a conductive material and semiconductive carbon nanotubes having a characteristic of a semiconductive material. The density of the carbon nanotube group is the density where the source electrode and the drain electrode are connected to each other through all of the carbon nanotube group and not connected to each other only through the conductive carbon nanotubes. | 12-17-2009 |
| 20090309092 | SELF-ALIGNED NANOTUBE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME - A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film. | 12-17-2009 |
| 20090315017 | Electronic devices - An electronic device includes a substrate supporting mobile charge carriers, insulative features formed on the substrate surface to define first and second substrate areas on either side of the insulative features, the first and second substrate areas being connected by an elongate channel defined by the insulative features, the channel providing a charge carrier flow path in the substrate from the first area to the second area, the conductivity between the first and second substrate areas being dependent upon the potential difference between the areas. The mobile charge carriers can be within at least two modes in each of the three dimensions within the substrate. The substrate can be an organic material. The mobile charge carriers can have a mobility within the range 0.01 cm | 12-24-2009 |
| 20090315018 | Methods of forming buffer layer architecture on silicon and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an In | 12-24-2009 |
| 20090321716 | Semiconductor Nanowire Transistor - A nanowire wrap-gate transistor is realised in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits. | 12-31-2009 |
| 20090321717 | COMPOSITIONALLY-GRADED QUANTUM-WELL CHANNELS FOR SEMICONDUCTOR DEVICES - A compositionally-graded quantum well channel for a semiconductor device is described. A semiconductor device includes a semiconductor hetero-structure disposed above a substrate and having a compositionally-graded quantum-well channel region. A gate electrode is disposed in the semiconductor hetero-structure, above the compositionally-graded quantum-well channel region. A pair of source and drain regions is disposed on either side of the gate electrode. | 12-31-2009 |
| 20090321718 | Thin film transistor - A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer includes a carbon nanotube structure comprised of carbon nanotubes. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The carbon nanotube structure is connected to both the source electrode and the drain electrode, and an angle exist between each carbon nanotube of the carbon nanotube structure and a surface of the semiconductor layer, and the angle ranges from about 0 degrees to about 15 degrees. | 12-31-2009 |
| 20100001259 | FIELD EFFECT TRANSISTOR - A source electrode | 01-07-2010 |
| 20100001260 | SELF-ALIGNED NANOTUBE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME - A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film. | 01-07-2010 |
| 20100006823 | Semiconducting Device Having Graphene Channel - The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure. | 01-14-2010 |
| 20100006824 | ORGANIC NANOFIBER STRUCTURE BASED ON SELF-ASSEMBLED ORGANOGEL, ORGANIC NANOFIBER TRANSISTOR USING THE SAME, AND METHOD OF MANUFACTURING THE ORGANIC NANOFIBER TRANSISTOR - An organic nanofiber including a gelled organic semiconductor compound. Also disclosed is an organic semiconductor transistor and a method of manufacturing an organic semiconductor transistor. | 01-14-2010 |
| 20100012923 | DOPANT MATERIAL, DOPANT MATERIAL MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE USING THE SAME - It is to provide a thermodynamically and chemically stable dopant material which can achieve controls of the pn conduction types, carrier density, and threshold value of gate voltage, and a manufacturing method thereof. Further, it is to provide an actually operable semiconductor device such as a transistor with an excellent high-speed operability and high-integration characteristic. Provided is a dopant material obtained by depositing, on a carbon nanotube, a donor with a smaller ionization potential than an intrinsic work function of the carbon nanotube or an acceptor with a larger electron affinity than the intrinsic work function of the carbon nanotube. The ionization potential of the donor in vacuum is desired to be 6.4 eV or less, and the electron affinity of the acceptor in vacuum to be 2.3 eV or more. | 01-21-2010 |
| 20100012924 | HETERO JUNCTION FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided. | 01-21-2010 |
| 20100012925 | HYBRID CARBON NANOTUBE FET (CNFET)-FET STATIC RAM (SRAM) AND METHOD OF MAKING SAME - Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET. | 01-21-2010 |
| 20100019226 | SEMICONDUCTOR SENSOR DEVICE, DIAGNOSTIC INSTRUMENT COMPRISING SUCH A DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE - The invention relates to a semiconductor sensor device ( | 01-28-2010 |
| 20100019227 | VARIABLE CAPACITOR SINGLE-ELECTRON DEVICE CROSS-REFERENCE TO RELATED APPLICATIONS - The present invention provides a single-electron transistor device | 01-28-2010 |
| 20100025658 | Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process - The disclosure pertains to a method for making a nanoscale filed effect transistor structure on a semiconductor substrate. The method comprises disposing a mask on a semiconductor upper layer of a multi-layer substrate, and removing areas of the upper layer not covered by the mask in a nanowire lithography process. The mask includes two conductive terminals separated by a distance, and a nanowire in contact with the conductive terminals across the distance. The nanowire lithography may be carried out using a deep-reactive-ion-etching, which results in an integration of the nanowire mask and the underlying semiconductor layer to form a nanoscale semiconductor channel for the field effect transistor. | 02-04-2010 |
| 20100025659 | NON-VOLATILE ELECTROMECHANICAL FIELD EFFECT DEVICES AND CIRCUITS USING SAME AND METHODS OF FORMING SAME - Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect, a field effect device includes a gate having a corresponding gate terminal; a source having a corresponding source terminal; a drain having a corresponding drain terminal; a control terminal; and a nanotube switching element positioned between one of the gate, source, and drain and its corresponding terminal and switchable, in response to electrical stimuli at the control terminal and at least one of the gate, source, and drain terminals, between a first non-volatile state that enables current flow between the source and the drain and a second non-volatile state that disables current flow between the source and the drain. | 02-04-2010 |
| 20100025660 | SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer; a gate layer comprising carbon nanotubes and/or graphene. Disclosed herein too is a method comprising disposing a source region, a drain region and a gate layer on a semiconductor host; the gate layer being disposed between the source region and the drain region; the gate layer comprising carbon nanotubes and/or graphene. | 02-04-2010 |
| 20100032653 | Carbon Nanotube Electric Field Effect Transistor and Process for Producing the Same - This invention provides a process for producing a carbon nanotube electric field effect transistor that can improve yield in channel preparation. Carbon nanotubes dispersed in a mixed acid composed of sulfuric acid and nitric acid are subjected to radical treatment with aqueous hydrogen peroxide to cut the carbon nanotubes and thus to provide carboxyl-introduced carbon nanotube fragments. The carbon nanotube fragments are attached, through a covalent bond and/or an electrostatic bond, to a site, where a source electrode is to be formed, and a site where a drain electrode is to be formed, in a substrate with a functional group, to be attached to a carboxyl group, introduced thereinto. The carbon nanotube fragments attached to the substrate are attached to carbon nanotubes as channels through n-n interaction to fix the carbon nanotubes as channels to the substrate. | 02-11-2010 |
| 20100038627 | METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR SOI SUBSTRATE - A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed. | 02-18-2010 |
| 20100038628 | CHEMICAL DOPING OF NANO-COMPONENTS - A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided for forming a field effect transistor comprising a nano-component that has been doped using such a dopant. | 02-18-2010 |
| 20100044678 | METHOD OF PLACING A SEMICONDUCTING NANOSTRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTING NANOSTRUCTURE - A method of placing a functionalized semiconducting nanostructure, includes functionalizing a semiconducting nanostructure including one of a nanowire and a nanocrystal, with an organic functionality including a functional group for bonding to a bonding surface, dispersing the functionalized semiconducting nanostructure in a solvent to form a dispersion, and depositing the dispersion onto the bonding surface. | 02-25-2010 |
| 20100044679 | Method For Producing Carbon Nanotube Transistor And Carbon Nanotube Transistor Thereby - The present invention relates to a method of manufacturing a carbon nanotube transistor in which a carbon nanotube channel is formed between a source electrode and a drain electrode and a gate electrode is formed at one side of the carbon nanotube channel, the method comprising the steps of: (a) forming the carbon nanotube channel on a substrate; (b) electrically connecting the source electrode and the drain electrode to both ends of the carbon nanotube channel, respectively; and (c) applying a stress voltage across the source electrode and the drain electrode to remove metallicity of the carbon nanotube channel. | 02-25-2010 |
| 20100065820 | Nanotube Device Having Nanotubes with Multiple Characteristics - A carbon nanotube of a nanotube device has at least two segments with different characteristics. The segments meet at a junction and a diameter of the carbon nanotube on either side of the junction is about the same. One segment may be doped differently from another segment. One segment may be p doped and another segment n doped. One segment may be doped with a different carrier concentration from another segment. The nanotube device may be used in power semiconductor devices including power diodes and power transistors. These power devices will be very power efficient, wasting significantly less energy than similar manufactured using silicon technology. | 03-18-2010 |
| 20100065821 | Molecular quantum interference device - A molecular quantum interference device is provided. A method for the design of such devices is also provided, the method including modelling of device performance. | 03-18-2010 |
| 20100065822 | LIPID NANOTUBE OR NANOWIRE SENSOR - A sensor apparatus comprising a nanotube or nanowire, a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer. Also a biosensor apparatus comprising a gate electrode; a source electrode; a drain electrode; a nanotube or nanowire operatively connected to the gate electrode, the source electrode, and the drain electrode; a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer. | 03-18-2010 |
| 20100065823 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 03-18-2010 |
| 20100065824 | METHOD FOR REDUCING FERMI-LEVEL-PINNING IN A NON-SILICON CHANNEL MOS DEVICE - A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created. | 03-18-2010 |
| 20100072458 | Methods For Sorting Nanotubes By Wall Number - The present teachings provide methods for sorting nanotubes according to their wall number, and optionally further in terms of their diameter, electronic type, and/or chirality. Also provided are highly enriched nanotube populations provided thereby and articles of manufacture including such populations. | 03-25-2010 |
| 20100072459 | NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME - Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate. | 03-25-2010 |
| 20100072460 | NANOELECTRONIC DEVICE - An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device. | 03-25-2010 |
| 20100084632 | NANOSTRUCTURE INSULATED JUNCTION FIELD EFFECT TRANSISTOR - A novel nanostructure device operating in Junction Field Effect Transistor (JFET) mode is provided that avoids the majority of the carriers that interact with the interface (e.g. surface roughness, high-k scattering). | 04-08-2010 |
| 20100084633 | SPIN TRANSISTOR USING DOUBLE CARRIER SUPPLY LAYER STRUCTURE - A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer. | 04-08-2010 |
| 20100090198 | Nanowire Field Effect Junction Diode - A nanowire field effect junction diode constructed on an insulating transparent substrate that allows form(s) of radiation such as visual light, ultraviolet radiation; or infrared radiation to pass. A nanowire is disposed on the insulating transparent substrate. An anode is connected to a first end of the nanowire and a cathode is connected to the second end of the nanowire. An oxide layer covers the nanowire. A first conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the anode. A second conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the cathode and adjacent with a non-zero separation the first conducting gate. A controllable PN junction may be dynamically formed along the nanowire channel by applying opposite gate voltages. Radiation striking the nanowire through the substrate creates a current the anode and cathode. | 04-15-2010 |
| 20100108988 | Nanotube-Based Structure and Method of Forming the Structure - Nanotube-based structure and method of forming the same are disclosed. A structure having two tips is provided for defining a location for forming a nanotube connection. The nanotube connection, which can be coated with an electrically conductive polymer for enhanced conductivity, can be used in forming nanotube-based devices for various applications. | 05-06-2010 |
| 20100117062 | Quantum well field-effect transistors with composite spacer structures, apparatus made therewith, and methods of using same - A quantum well (QW) layer is provided in a semiconductive device. The QW layer is covered with a composite spacer above QW layer. The composite spacer includes an InP spacer first layer and an InAlAs spacer second layer above and on the InP spacer first layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate. | 05-13-2010 |
| 20100127242 | TRANSPARENT ELECTRONICS BASED ON TRANSFER PRINTED CARBON NANOTUBES ON RIGID AND FLEXIBLE SUBSTRATES - Methods and devices for transparent electronics are disclosed. According to an embodiment, transparent electronics are provided based on transfer printed carbon nanotubes that can be disposed on both rigid and flexible substrates. Methods are provided to enable highly aligned single-walled carbon nanotubes (SWNTs) to be used in transparent electronics for achieving high carrier mobility while using low-temperature processing. According to one method, highly aligned nanotubes can be grown on a first substrate. Then, the aligned nanotubes can be transferred to a rigid or flexible substrate having pre-patterned gate electrodes. Source and drain electrodes can be formed on the transferred nanotubes. The subject devices can be integrated to provide logic gates and analog circuitry for a variety of applications. | 05-27-2010 |
| 20100133509 | SEMICONDUCTOR NANOWIRE AND ITS MANUFACTURING METHOD - A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth. | 06-03-2010 |
| 20100133510 | BIO-SENSOR CHIP - Provided is a bio-sensor chip. The bio-sensor chip includes a sensing part, a board circuit part, a channel part, and a cover. In the sensing part, a target material and a detection material interact with each other to detect the target material. The board circuit part is electrically connected to the sensing part. The channel part provides a solution material containing the target material into the sensing part. The cover is coupled to the board circuit part to cover the channel part and the sensing part. | 06-03-2010 |
| 20100133511 | Integrated Circuits Based on Aligned Nanotubes - Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes. | 06-03-2010 |
| 20100133512 | METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR SOI SUBSTRATE - A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed. | 06-03-2010 |
| 20100140588 | CATALYST SUPPORT SUBSTRATE, METHOD FOR GROWING CARBON NANOTUBES USING THE SAME, AND TRANSISTOR USING CARBON NANOTUBES - A catalyst supporting substrate includes a first region ( | 06-10-2010 |
| 20100140589 | FERROELECTRIC TUNNEL FET SWITCH AND MEMORY - A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV/decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, wherein the combined effect of BTB tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions in the present proposed Ferroelectric tunnel FET than for any reported tunnel FET or any reported ferroelectric FET. | 06-10-2010 |
| 20100140590 | TRANSISTOR COMPRISING CARBON NANOTUBES FUNCTIONALIZED WITH A NON-FLUORO CONTAINING ELECTRON DEFICIENT OLEFIN OR ALKYNE - The present invention is a transistor and a process for making the transistor in which the semiconductor component comprises at least one carbon nanotube functionalized by cycloaddition with a fluorinated olefin. Functionalization with the fluorinated olefin renders the carbon nanotube semiconducting. | 06-10-2010 |
| 20100148153 | Group III-V devices with delta-doped layer under channel region - A group III-V material device has a delta-doped region below a channel region. This may improve the performance of the device by reducing the distance between the gate and the channel region. | 06-17-2010 |
| 20100155701 | Self-aligned replacement metal gate process for QWFET devices - A self-aligned replacement metal gate QWFET device comprises a III-V quantum well layer formed on a substrate, a III-V barrier layer formed on the quantum well layer, a III-V etch stop layer formed on the III-V barrier layer, a III-V source extension region formed on the III-V etch stop layer and having a first sidewall, a source region formed on the III-V source extension region and having a second sidewall, a III-V drain extension region formed on the III-V etch stop layer and having a third sidewall, a drain region formed on the III-V drain extension region and having a fourth sidewall, a conformal high-k gate dielectric layer formed on the first, second, third, and fourth sidewalls and on a top surface of the etch stop layer, and a metal layer formed on the high-k gate dielectric layer. | 06-24-2010 |
| 20100155702 | NANOWIRE CIRCUIT ARCHITECTURE - A nanowire circuit architecture is presented. The technology comprises of nanowire transistors ( | 06-24-2010 |
| 20100155703 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot. | 06-24-2010 |
| 20100163843 | ROOM TEMPERATURE-OPERATING SINGLE-ELECTRON DEVICE AND THE FABRICATION METHOD THEREOF - The present invention relates to a room temperature-operating single-electron device and a fabrication method thereof, and more particularly, to a room temperature-operating single-electron device in which a plurality of metal silicide dots formed serially is used as multiple quantum dots, and a fabrication method thereof. | 07-01-2010 |
| 20100163844 | Fabrication method of electronic devices based on aligned high aspect ratio nanoparticle networks - A layer of high aspect ratio nanoparticles is disposed on a surface of a substrate under the influence of an electrical field applied on the substrate. To create the electrical field, a voltage is applied between a pair of electrodes arranged near the substrate or on the substrate, and the high aspect ratio nanoparticles disposed on the substrate are at least partially aligned along direction(s) of the applied electrical field. The high aspect ratio nanoparticles are grown from catalyst nanoparticles in an aerosol, and the aerosol is directly used for forming the nanoparticle layer on the substrate at room temperature. The nanoparticles may be carbon nanotubes, in particular single wall carbon nanotubes. The substrate with the layer of aligned high aspect ratio nanoparticles disposed thereon can be used for fabricating nanoelectronic devices. | 07-01-2010 |
| 20100163845 | Tunnel field effect transistor and method of manufacturing same - A TFET includes a source region ( | 07-01-2010 |
| 20100163846 | Nano-tube mosfet technology and devices - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches. | 07-01-2010 |
| 20100163847 | QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS - Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well. | 07-01-2010 |
| 20100163848 | BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION - Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers. | 07-01-2010 |
| 20100163849 | DOUBLE PASS FORMATION OF A DEEP QUANTUM WELL IN ENHANCEMENT MODE III-V DEVICES - A quantum well is formed for a deep well III-V semiconductor device using double pass patterning. In one example, the well is formed by forming a first photolithography pattern over terminals on a material stack, etching a well between the terminals using the first photolithography patterning, removing the first photolithography pattern, forming a second photolithography pattern over the terminals and at least a portion of the well, deepening the well between the terminals by etching using the second photolithography pattern, removing the second photolithography pattern, and finishing the terminals and the well to form a device on the material stack. | 07-01-2010 |
| 20100163850 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both side portions, the source electrode and the drain electrode electrically connected to the silicon nanowire, respectively. | 07-01-2010 |
| 20100187502 | ENCLOSED NANOTUBE STRUCTURE AND METHOD FOR FORMING - A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap. | 07-29-2010 |
| 20100187503 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge nano wire are (111) planes, and the other surface that define the triangular cross section of the Ge nano wire is a (100) plane; and an Si layer or an Si | 07-29-2010 |
| 20100193770 | Maskless Process for Suspending and Thinning Nanowires - Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET. | 08-05-2010 |
| 20100193771 | QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS - Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well. | 08-05-2010 |
| 20100200838 | SWITCHING ELEMENT - In a switching element using, for the active layer, a carbon nanotube (CNT) dispersed film which can be manufactured at low temperatures, the interaction between the CNT and the surface of the gate insulating film is insufficient. For this reason, a problem of such a switching element is that the amount of CNT fixed in the channel region is insufficient, resulting in insufficient uniformity. In the switching element of the exemplary embodiment, a gate insulating film is formed of a nonconjugated polymer material containing, in the main chain, an aromatic group and a substituted or unsubstituted alkylene or alkyleneoxy group having 2 or more carbon atoms as repeating units. As a result, the interaction between the CNT and the surface of the gate insulating film is enhanced while maintaining the flexibility of the gate insulating film, and the amount of CNT fixed in the channel region can be increased. Thereby, a switching element having good and stable transistor characteristics can be obtained by a low-temperature, simple, and inexpensive process. | 08-12-2010 |
| 20100207101 | INCORPORATING GATE CONTROL OVER A RESONANT TUNNELING STRUCTURE IN CMOS TO REDUCE OFF-STATE CURRENT LEAKAGE, SUPPLY VOLTAGE AND POWER CONSUMPTION - A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode. | 08-19-2010 |
| 20100207102 | Static random access memories having carbon nanotube thin films - A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter. | 08-19-2010 |
| 20100207103 | Method of Forming Nanotube Vertical Field Effect Transistor - A nanotube field effect transistor and a method of fabrication are disclosed. The method includes electrophoretic deposition of a nanotube to contact a region of a conductive layer defined by an aperture. | 08-19-2010 |
| 20100213441 | Modulation-doped halos in quantum well field-effect transistors, apparatus made therewith, and methods of using same - A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate. | 08-26-2010 |
| 20100224862 | CARBON NANOTUBE STRUCTURE AND THIN FILM TRANSISTOR - When an electronic element using a carbon nanotube (CNT) is fabricated, particularly when a carbon nanotube thin film is formed on a previously formed electrode, a CNT film is manufactured on the previously formed electrode, and the CNT film on the electrode is used as an electronic element, as it is. In this case, a problem is that unless the carbon nanotubes and the electrode are in sufficient contact with each other, the contact resistance increases, and sufficient element properties are not obtained. When a carbon nanotube thin film is formed on a previously formed electrode, a conductive organic polymer thin film is formed, before or after the carbon nanotube thin film is manufactured, to decrease the contact resistance. | 09-09-2010 |
| 20100237324 | Semiconductor Switching Circuit Employing Quantum Dot Structures - A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided. | 09-23-2010 |
| 20100243990 | NANOSENSORS - Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described. | 09-30-2010 |
| 20100252812 | Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region. | 10-07-2010 |
| 20100252813 | Core-Shell-Shell Nanowire Transistor And Fabrication Method - A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure. The source/drain (S/D) regions in end sections of the CS nanostructure flanking are doped. | 10-07-2010 |
| 20100252814 | SEMICONDUCTOR NANOWIRES HAVING MOBILITY-OPTIMIZED ORIENTATIONS - Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning. | 10-07-2010 |
| 20100252815 | STRUCTURALLY STABILIZED SEMICONDUCTOR NANOWIRE - In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During the thinning process that forms a semiconductor nanowire, the taper at the end portions of the semiconductor nanowire provides enhanced mechanical strength to prevent structural buckling or bending. In another embodiment, a semiconductor nanowire having bulge portions are formed by preventing the thinning of a semiconductor link portion at pre-selected positions. The bulge portions having a greater width than a middle portion of the semiconductor nanowire provides enhanced mechanical strength during thinning of the semiconductor link portion so that structural damage to the semiconductor nanowire is avoided during thinning. | 10-07-2010 |
| 20100252816 | High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio - A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region. | 10-07-2010 |
| 20100264403 | NANOROD THIN-FILM TRANSITORS - A method for forming an electronic switching device on a substrate, wherein the method comprises depositing the active semiconducting layer of the electronic switching device onto the substrate from a liquid dispersion of ligand-modified colloidal nanorods, and subsequently immersing the substrate into a growth solution to increase the diameter and/or length of the nanorods on the substrate, and wherein the as-deposited nanorods are aligned such that their long-axis is aligned preferentially in the plane of current flow in the electronic switching device. | 10-21-2010 |
| 20100270536 | Concentric Gate Nanotube Transistor Devices - Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications. | 10-28-2010 |
| 20100276667 | NONVOLATILE MEMORY ELECTRONIC DEVICE INCLUDING NANOWIRE CHANNEL AND NANOPARTICLE-FLOATING GATE NODES AND A METHOD FOR FABRICATING THE SAME - A nonvolatile memory electronic device including nanowire channel and nanoparticle-floating gate nodes, in which the nonvolatile memory electronic device, which comprises a semiconductor nanowire used as a charge transport channel and nanoparticles used as a charge trapping layer, is configured by allowing the nanoparticles to be adsorbed on a tunneling layer deposited on a surface of the semiconductor nanowire, whereby charge carriers moving through the nanowire are tunneled to the nanoparticles by a voltage applied to a gate, and then, the charge carriers are tunneled from the nanoparticles to the nanowire by the change of the voltage that has been applied to the gate, whereby the nonvolatile memory electronic device can be operated at a low voltage and increase the operation speed thereof. | 11-04-2010 |
| 20100276668 | Reducing Source/Drain Resistance of III-V Based Transistors - An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode. | 11-04-2010 |
| 20100276669 | ELECTRIC NANODEVICE AND METHOD OF MANUFACTURING SAME - A nanodevice is disclosed. The nanodevice comprises: a drain region, a source region opposite to the drain region and being separated therefrom at least with a trench, and a gate region, isolated from the drain and the source regions and from the trench. The trench has a height which is between 1 nm and 30 nm. | 11-04-2010 |
| 20100295020 | Method For Forming A Robust Top-Down Silicon Nanowire Structure Using A Conformal Nitride And Such Structure - A nanowire product and process for fabricating it has a wafer with a buried oxide (BOX) upper layer in which a well is formed and the ends of a nanowire are on the BOX layer forming a beam that spans the well. A mask coating is formed on the upper surface of the BOX layer leaving an uncoated window over a center part of the beam and also forming a mask coating around the beam intermediate ends between each end of the beam center part and a side wall of the well. Applying oxygen through the window thins the beam center part while leaving the wire intermediate ends over the well thicker and having a generally arched shape. A thermal oxide coating can be placed on the wire and also the mask on the BOX layer before oxidation. | 11-25-2010 |
| 20100295021 | Single Gate Inverter Nanowire Mesh - Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided. | 11-25-2010 |
| 20100295022 | Nanowire Mesh FET with Multiple Threshold Voltages - Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels. | 11-25-2010 |
| 20100295023 | FIELD EFFECT TRANSISTOR FABRICATION FROM CARBON NANOTUBES - Methods and apparatus for an electronic device such as a field effect transistor. One embodiment includes fabrication of an FET utilizing single walled carbon nanotubes as the semiconducting material. In one embodiment, the FETs are vertical arrangements of SWCNTs, and in some embodiments prepared within porous anodic alumina (PAA). Various embodiments pertain to different methods for fabricating the drains, sources, and gates. | 11-25-2010 |
| 20100295024 | SEMICONDUCTOR STRUCTURE AND METHOD FOR PRODUCING A SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a support and at least one block provided on the support. The block includes a stack including alternating layers based on a first semiconductor material and layers based on a second semiconductor material different from the first material, the layers presenting greater dimensions than layers such that the stack has a lateral tooth profile and a plurality of spacers filling the spaces formed by the tooth profile, the spacers being made of a third material different from the first material such that each of the lateral faces of the block presents alternating lateral bands based on the first material and alternating lateral bands based on the third material. At least one of the lateral faces of the block is partially coated with a material promoting the growth of nanotubes or nanowires, the catalyst material exclusively coating the lateral bands based on the first material or exclusively coating the lateral bands based on the third material. | 11-25-2010 |
| 20100295025 | CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT - Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array. | 11-25-2010 |
| 20100314609 | NANOWIRE MEMORY - Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories. | 12-16-2010 |
| 20100314610 | HEMT WITH IMPROVED QUANTUM CONFINEMENT OF ELECTRONS - A HEMT with improved electron confinement is formed by removing semiconductor cap material between the channel and the source and drain regions. The source and drain regions can be isolated from the gate region by an insulating layer. Significant noise reduction can be achieved as a result of these techniques. Also, removing the semiconductor cap material can provide an increased breakdown voltage for the transistor. | 12-16-2010 |
| 20100327259 | Ultra-Sensitive Detection Techniques - Techniques for ultra-sensitive detection are provided. In one aspect, a detection device is provided. The detection device comprises a source; a drain; a nanowire comprising a semiconductor material having a first end clamped to the source and a second end clamped to the drain and suspended freely therebetween; and a gate in close proximity to the nanowire. | 12-30-2010 |
| 20100327260 | Single Electron Transistor Operating at Room Temperature and Manufacturing Method for Same - The present invention relates to a single electron transistor operating at room temperature and a manufacturing method for same. More particularly, the present invention relates to a single electron transistor operating at room temperature, in which a quantum dot or a silicide quantum dot using a nanostructure is formed and a gate is positioned on the quantum dot so as to minimize influence on a tunneling barrier and achieve improved effectiveness in electric potential control for the quantum dot and operating efficiency of the transistor, and a manufacturing method for same. | 12-30-2010 |
| 20100327261 | HIGH HOLE MOBILITY P-CHANNEL GE TRANSISTOR STRUCTURE ON SI SUBSTRATE - The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 12-30-2010 |
| 20110006286 | Transverse Force, Pressure and Vibration Sensors using Piezoelectric Nanostructures - An electrical device includes an insulating substrate; an elongated piezoelectric semiconductor structure, a first electrode and a second electrode. A first portion of the elongated piezoelectric semiconductor structure is affixed to the substrate and a second portion of the elongated piezoelectric semiconductor structure extends outwardly from the substrate. The first electrode is electrically coupled to a first end of the first portion of the elongated piezoelectric semiconductor structure. The second electrode is electrically coupled to a second end of the first portion of the elongated piezoelectric semiconductor structure. | 01-13-2011 |
| 20110012090 | SILICON-GERMANIUM NANOWIRE STRUCTURE AND A METHOD OF FORMING THE SAME - A silicon-germanium nanowire structure arranged on a support substrate is disclosed, The silicon-germanium nanowire structure includes at least one germanium-containing supporting portion arranged on the support substrate, at least one germanium-containing nanowire disposed above the support substrate and arranged adjacent the at least one germanium-containing supporting portion, wherein germanium concentration of the at least one germanium-containing nanowire is higher than the at least one germanium-containing supporting portion. A transistor comprising the silicon-germanium nanowire structure arranged on a support substrate is also provided. A method of forming a silicon-germanium nanowire structure arranged on a support substrate and a method of forming a transistor comprising forming the silicon-germanium nanowire structure arranged on a support substrate are also disclosed. | 01-20-2011 |
| 20110031473 | Nanomesh SRAM Cell - Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels. | 02-10-2011 |
| 20110042648 | RECONFIGURABLE LOGIC DEVICE USING SPIN ACCUMULATION AND DIFFUSION - A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns. | 02-24-2011 |
| 20110049473 | Film Wrapped NFET Nanowire - A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire. | 03-03-2011 |
| 20110049474 | TUNNEL FIELD EFFECT DEVICES - An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state. | 03-03-2011 |
| 20110049475 | Solid state charge qubit device - This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them. | 03-03-2011 |
| 20110049476 | IMPACT IONIZATION FIELD-EFFECT TRANSISTOR - An Impact Ionization Field-Effect Transistor (I-MOS) device in which device degradation caused by hot carrier injection into a gate oxide is prevented. The device includes source, drain, and gate contacts, and a channel between the source and the drain. The channel has a dimension normal to the direction of a charge carrier transport in the channel such that the energy separation of the first two sub-bands equals or exceeds the effective energy band gap of the channel material. | 03-03-2011 |
| 20110057168 | 3-TERMINAL ELECTRONIC DEVICE AND 2-TERMINAL ELECTRONIC DEVICE - A 3-terminal electronic device includes: a control electrode; a first electrode and a second electrode; and an active layer that is provided between the first electrode and the second electrode and is provided to be opposed to the control electrode via an insulating layer. The active layer includes a collection of nanosheets. When it is assumed that the nanosheets have an average size L | 03-10-2011 |
| 20110062417 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion on a channel region between the source/drain regions. Third semiconductor layers are on the first portions of the second semiconductor layer. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. Contact plugs are in the first semiconductor layers, the first portions of the second semiconductor layers and the third semiconductor layers in the source/drain regions. A diameter of the contact plug in the second semiconductor layer is smaller than a diameter of the contact plug in the first and third semiconductor layers. | 03-17-2011 |
| 20110062418 | MOLECULAR TRANSISTOR DRIVING OF NANOSCALE ACTUATORS FROM DIFFERENTIAL AMPLIFIER CIRCUITS COMPATIBLE WITH CARBON NANOTUBE SENSORS AND TRANSDUCERS - A carbon nanotube electronic circuit utilizing a differential amplifier is implemented on a single carbon nanotube. Field effect transistors are formed from a first group of electrical conductors in contact with the carbon nanotube and a second group of electrical conductors insulated from, but exerting electric fields on, the carbon nanotube form the gates of the field effect transistors. A signal input circuit has a first input portion and a second input portion. A first field effect transistor electrically responsive to a first incoming signal is formed on the first input portion. A carbon nanotube actuator having electrical terminals and responsive to electrical conditions is an electrical load. A current source, connected to the signal input circuit, is formed on the carbon nanotube from one or more second field effect transistors. The electrical load is connected to the signal input circuit, and the signal input circuit and current source together form a differential amplifier to operate the actuator responsive to the incoming signal. | 03-17-2011 |
| 20110062419 | FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Provided is a carbon nanotube field effect transistor manufacturing method wherein carbon nanotube field effect transistors having excellent stable electric conduction property are manufactured with excellent reproducibility. After arranging carbon nanotubes to be a channel on a substrate, the carbon nanotubes are covered with an insulating protection film. Then, a source electrode and a drain electrode are formed on the insulating protection film. At this time, a contact hole is formed on the protection film, and the carbon nanotubes are connected with the source electrode and the drain electrode. Then, a wiring protection film, a conductive film and a plasma CVD film are sequentially formed on the insulating protection film, the source electrode and the drain electrode. In the field effect transistor thus manufactured, since the carbon nanotubes to be the channel are not contaminated and not damaged, excellent stable electric conductive property is exhibited. | 03-17-2011 |
| 20110068323 | Local Bottom Gates for Graphene and Carbon Nanotube Devices - Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided. | 03-24-2011 |
| 20110068324 | N-TYPE TRANSISTOR, PRODUCTION METHODS FOR N-TYPE TRANSISTOR AND N-TYPE TRANSISTOR-USE CHANNEL, AND PRODUCTION METHOD OF NANOTUBE STRUCTURE EXHIBITING N-TYPE SEMICONDUCTOR-LIKE CHARACTERISTICS - An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound | 03-24-2011 |
| 20110073840 | RADIAL CONTACT FOR NANOWIRES - An embodiment is a method and apparatus of radial contact using nanowires. An inner contact has a center. An outer contact surrounds the inner contact around the center and is spaced from the inner contact by a channel length. A nanowire connects the center of the inner contact and the outer contact in a rotationally invariant geometry. | 03-31-2011 |
| 20110073841 | NANO LINE STRUCTURES IN MICROELECTRONIC DEVICES - A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed. | 03-31-2011 |
| 20110073842 | NANO-WIRE FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE TRANSISTOR, AND INTEGRATED CIRCUIT INCLUDING THE TRANSISTOR - Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor. | 03-31-2011 |
| 20110079769 | Nanometric MOS Transistor With Maximized Ration Between On-State Current and Off-State Current - A MOS transistor having a gate length shorter than twice the de Broglie wavelength of the charge carriers in the channel material, wherein the cross-sectional area of the channel region is decreased in the vicinity of the drain region along at least one dimension to a value smaller than half said wavelength. | 04-07-2011 |
| 20110079770 | Preparation of Thin Film Transistors (TFTs) or Radio Frequency Identification (RFID) Tags or Other Printable Electronics Using Ink-Jet Printer and Carbon Nanotube Inks - The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of exiting printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques can not used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks. | 04-07-2011 |
| 20110079771 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching using a hot phosphoric acid solution, and a gate electrode is formed so that the lower portion thereof fill the first and second openings while placing a gate insulating film in between, and so that the head portion thereof projects above the cap structure. | 04-07-2011 |
| 20110095267 | Nanowire Stress Sensors and Stress Sensor Integrated Circuits, Design Structures for a Stress Sensor Integrated Circuit, and Related Methods - Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress. | 04-28-2011 |
| 20110108802 | Metal-Free Integrated Circuits Comprising Graphene and Carbon Nanotubes - An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene. | 05-12-2011 |
| 20110108803 | VERTICAL NANOWIRE FET DEVICES - A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode. | 05-12-2011 |
| 20110108804 | Maskless Process for Suspending and Thinning Nanowires - Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET. | 05-12-2011 |
| 20110114918 | FABRICATION OF GRAPHENE NANOELECTRONIC DEVICES ON SOI STRUCTURES - A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer. | 05-19-2011 |
| 20110121266 | QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS - Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well. | 05-26-2011 |
| 20110127492 | Field Effect Transistor Having Nanostructure Channel - A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure. | 06-02-2011 |
| 20110127493 | SELF ALIGNED CARBIDE SOURCE/DRAIN FET - A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure. | 06-02-2011 |
| 20110133161 | Omega Shaped Nanowire Tunnel Field Effect Transistors - A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region. | 06-09-2011 |
| 20110133162 | Gate-All-Around Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region. | 06-09-2011 |
| 20110133163 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire. | 06-09-2011 |
| 20110133164 | Omega Shaped Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region. | 06-09-2011 |
| 20110133165 | SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions. | 06-09-2011 |
| 20110133166 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire. | 06-09-2011 |
| 20110133167 | PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS - A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region. | 06-09-2011 |
| 20110133168 | QUANTUM-WELL-BASED SEMICONDUCTOR DEVICES - Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer. | 06-09-2011 |
| 20110140085 | METHODS FOR FABRICATING SELF-ALIGNING ARRANGEMENTS ON SEMICONDUCTORS - Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described. | 06-16-2011 |
| 20110140086 | NANOSTRUCTURED MEMORY DEVICE - The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire ( | 06-16-2011 |
| 20110140087 | SCALABLE QUANTUM WELL DEVICE AND METHOD FOR MANUFACTURING THE SAME - A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap. | 06-16-2011 |
| 20110147708 | INCREASING CARRIER INJECTION VELOCITY FOR INTEGRATED CIRCUIT DEVICES - Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed. | 06-23-2011 |
| 20110147709 | SIGNAL CONTROL ELEMENTS IN FERROMAGNETIC LOGIC - A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations. | 06-23-2011 |
| 20110147710 | DUAL LAYER GATE DIELECTRICS FOR NON-SILICON SEMICONDUCTOR DEVICES - Non-silicon metal-insulator-semiconductor (MIS) devices and methods of forming the same. The non-silicon MIS device includes a gate dielectric stack which comprises at least two layers of non-native oxide or nitride material. The first material layer of the gate dielectric forms an interface with the non-silicon semiconductor surface and has a lower dielectric constant than a second material layer of the gate dielectric. In an embodiment, a dual layer including a first metal silicate layer and a second oxide layer provides both a good quality oxide-semiconductor interface and a high effective gate dielectric constant. | 06-23-2011 |
| 20110147711 | NON-PLANAR GERMANIUM QUANTUM WELL DEVICES - Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 06-23-2011 |
| 20110147712 | QUANTUM WELL TRANSISTORS WITH REMOTE COUNTER DOPING - A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel. | 06-23-2011 |
| 20110147713 | TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS - Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material. | 06-23-2011 |
| 20110147714 | FIELD-EFFECT TRANSISTOR AND SENSOR BASED ON THE SAME - A field-effect transistor has at least one electrode disposed independently of source and drain electrodes and in direct contact with the surface of a semiconductor channel to form a schottky barrier, so that it is possible to easily control the schottky barrier. | 06-23-2011 |
| 20110147715 | Medium Scale Carbon Nanotube Thin Film Integrated Circuits on Flexible Plastic Substrates - The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems. | 06-23-2011 |
| 20110156004 | Multi-gate III-V quantum well structures - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material. | 06-30-2011 |
| 20110156005 | Germanium-based quantum well devices - A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric. | 06-30-2011 |
| 20110156006 | Forming A Non-Planar Transistor Having A Quantum Well Channel - In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed. | 06-30-2011 |
| 20110163296 | CNT-BASED SENSORS: DEVICES, PROCESSES AND USES THEREOF - Disclosed herein are methods of preparing and using doped MWNT electrodes, sensors and field-effect transistors. Devices incorporating doped MWNT electrodes, sensors and field-effect transistors are also disclosed. | 07-07-2011 |
| 20110163297 | Core-Shell-Shell Nanowire Transistor - A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure. The source/drain (S/D) regions in end sections of the CS nanostructure flanking are doped. | 07-07-2011 |
| 20110168980 | Nanofiber composite, method of manufacturing the same, and field effect transistor including the same - A nanofiber composite including a nanofiber formed of a hydrophobic polymer, a nanowire formed of a conductive or semiconductive organic material that is oriented in the nanofiber in the longitudinal direction of the nanofiber, and an ionic active material. | 07-14-2011 |
| 20110204331 | CHARGE STORAGE NANOSTRUCTURE - The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established. | 08-25-2011 |
| 20110204332 | Semiconductor device and method of manufacturing the same - A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semiconductor device may be a memory device or a diode. | 08-25-2011 |
| 20110215298 | ULTRAFAST AND ULTRASENSITIVE NOVEL PHOTODETECTORS - A photodetector is provided that includes a FET structure with a channel structure having one or more nanowire structures. Noble metal nanoparticles are positioned on the channel structure so as to produce a functionalized channel structure. The functionalized channel structure exhibits pronounced surface plasmon resonance (SPR) absorption near the SPR frequency of the noble metal nanoparticles. | 09-08-2011 |
| 20110220875 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises: growing a carbon nano tube on a semiconductor substrate; forming an insulating film in the inside and the outside of the carbon nano tube; and forming a graphene on the surface of the insulating film, thereby securing a channel region corresponding to a region extended by the carbon nano tube to prevent a short channel effect. As a result, channel resistance is reduced to facilitate the manufacturing of the device that can be operated at a high speed. The carbon nano tube is applied to a semiconductor device of less than 30 nm so that a micro-sized semiconductor device can be manufactured regardless of limitation of exposure light sources. | 09-15-2011 |
| 20110227043 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 09-22-2011 |
| 20110233521 | SEMICONDUCTOR WITH CONTOURED STRUCTURE - The present disclosure relates to a semiconductor device that has a first semiconductor structure that is grown to form a non-planar growth surface. The non-planar growth surface is formed from multiple facets and provides a defined contour. The defined contour may include, but is not limited to a corrugated contour or a pyramidal contour. A second semiconductor structure is grown over the non-planar growth surface of the first semiconductor structure, and as such, the second semiconductor structure is non-planar and follows the defined contour of the non-planar growth surface of the first semiconductor structure. The first and second semiconductor structures may form the foundation for various types of electrical and optoelectrical semiconductor devices, such as diodes, transistors, thyristors, and the like. | 09-29-2011 |
| 20110233522 | p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors - Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET. | 09-29-2011 |
| 20110233523 | SINGLE ELECTRON TRANSISTOR - A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot. | 09-29-2011 |
| 20110253980 | Source/Drain Technology for the Carbon Nano-tube/Graphene CMOS with a Single Self-Aligned Metal Silicide Process - Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided. | 10-20-2011 |
| 20110253981 | METHOD OF MANUFACTURING A VERTICAL TFET - The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs. | 10-20-2011 |
| 20110253982 | VERTICAL GROUP III-V NANOWIRES ON SI, HETEROSTRUCTURES, FLEXIBLE ARRAYS AND FABRICATION - Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures. An array of Group III-V nanowire structures is embedded in polymer. A fabrication method forms the vertical nanowires on a substrate, e.g., a silicon substrate. Preferably, the nanowires are formed by the preferred methods for fabrication of Group III-V nanowires on silicon. Devices can be formed with core/shell and core/multi-shell nanowires and the devices are released from the substrate upon which the nanowires were formed to create a flexible structure that includes an array of vertical nanowires embedded in polymer. | 10-20-2011 |
| 20110272673 | DIRECTIONALLY ETCHED NANOWIRE FIELD EFFECT TRANSISTORS - A method for forming a nanowire field effect transistor (FET) device includes depositing a first semiconductor layer on a substrate wherein a surface of the semiconductor layer is parallel to {110} crystalline planes of the semiconductor layer, epitaxailly depositing a second semiconductor layer on the first semiconductor layer, etching the first semiconductor layer and the second semiconductor layer to define a nanowire channel portion that connects a source region pad to a drain region pad, the nanowire channel portion having sidewalls that are parallel to {100} crystalline planes, and the source region pad and the drain region pad having sidewalls that are parallel to {110} crystalline planes, and performing an anisotropic etch that removes primarily material from {100} crystalline planes of the first semiconductor layer such that the nanowire channel portion is suspended by the source region pad and the drain region pad. | 11-10-2011 |
| 20110278542 | TFET with Nanowire Source - A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region. | 11-17-2011 |
| 20110278543 | GENERATION OF MUTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions. | 11-17-2011 |
| 20110278544 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses. | 11-17-2011 |
| 20110297916 | N-and P-Channel Field-Effect Transistors with Single Quantum Well for Complementary Circuits - A complementary metal oxide semiconductor (CMOS) device in which a single In | 12-08-2011 |
| 20110309332 | EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS - A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks. | 12-22-2011 |
| 20110309333 | SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE - A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions. | 12-22-2011 |
| 20110309334 | Graphene/Nanostructure FET with Self-Aligned Contact and Gate - A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material. | 12-22-2011 |
| 20110315960 | TUNNEL FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME - A TFET includes a source region ( | 12-29-2011 |
| 20120007051 | Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric - Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material. | 01-12-2012 |
| 20120007052 | Apparatus, System, and Method for Dual-Channel Nanowire FET Device - An apparatus, system, and method for dual-channel FET devices is presented. In some embodiments, the nanowire FET device may include a first transistor on a substrate, where the first transistor includes a first group of nanowires made of silicon. The nanowire FET device may also include a second transistor on the same substrate, where the second transistor includes a second group of nanowires made of silicon-germanium. | 01-12-2012 |
| 20120018704 | UNIAXIAL TENSILE STRAIN IN SEMICONDUCTOR DEVICES - A semiconductor device structure comprises an active layer and a buffer layer. The active layer is a quantum well structure. There is a lattice mismatch between the buffer layer and the active layer which places the active layer under biaxial compressive strain. Uniaxial tensile strain is applied to the active layer to reduce compressive strain on the active layer in a second direction but not in a first direction. This favours hole and electron mobility in the first direction, rendering the semiconductor device structure suitable for the formation of both p-channel and n-channel devices. | 01-26-2012 |
| 20120025169 | NANOSTRUCTURE ARRAY TRANSISTOR - Transistors and methods for forming transistors from groups of nanostructures are disclosed herein. The transistor may be formed from an array of nanostructures that are grown vertically on a substrate. The nanostructures may have lower, middle and upper segments that may be formed with different materials and/or doping to achieve desired effects. Collectively, the lower segments may form the source or drain, with the middle segments collectively forming the channel. Alternatively, the lower segments could collectively form the emitter or collector, with the middle segments collectively forming the base. Transistor electrodes may be planar metal structures that surround sidewalls of the nanostructures. The transistors may be Field Effect Transistors (FETs) or bipolar junction transistors (BJTs). Heterojunction bipolar junction transistors (HBTs) and high electron mobility transistors (HEMTs) are possible. | 02-02-2012 |
| 20120025170 | P-TYPE SEMICONDUCTOR DEVICES - A semiconductor device comprises an active layer above a first confinement layer. The active layer comprises a layer of α-Sn less than 20 nm thick. The first confinement layer is formed of material with a wider band gap than α-Sn, wherein the band gap offset between α-Sn and this material allows confinement of charge carriers in the active layer so that the active layer acts as a quantum well. A similar second confinement layer may be formed over the active layer. This semiconductor device may be a p-FET. A method of fabricating such a semiconductor device is described. | 02-02-2012 |
| 20120032149 | Vertical Stacking of Carbon Nanotube Arrays for Current Enhancement and Control - Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided. | 02-09-2012 |
| 20120056161 | GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE - A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode. | 03-08-2012 |
| 20120061649 | STRAIN-INDUCING SEMICONDUCTOR REGIONS - A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate. | 03-15-2012 |
| 20120068158 | INFRARED LIGHT DETECTOR - Provided is an infrared light detector | 03-22-2012 |
| 20120074386 | Non-planar quantum well device having interfacial layer and method of forming same - Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 03-29-2012 |
| 20120104361 | TRANSISTOR USING SOURCE ELECTRODE AND DRAIN ELECTRODE HAVING POINTED PORTIONS - A transistor includes a substrate, a source electrode, a drain electrode and a nanowire-layer. The source electrode, the drain electrode and the nanowires-layer are formed on the substrate. The source electrode includes a plurality of first pointed portions, and the drain electrode includes a plurality of second pointed portions each aligned with a corresponding first pointed portions. The nanowire-layer is interconnected between the first pointed portions and the second pointed portions. | 05-03-2012 |
| 20120132892 | Nano Device - Disclosed herein is a nano device, including: a carbon layer including one-layered graphene having a honeycombed planar structure in which carbon atoms are connected with each other and two or more-layered monocrystalline graphite; and one or more vertically-grown nanostructures formed on the carbon layer. This nano device can be used to manufacture an integrated circuit in which various devices including a graphene electronic device and a photonic device are connected with each other, and is a high-purity and high-quality nano device having a small amount of impurities because a metal catalyst is not used. | 05-31-2012 |
| 20120138899 | SEMICONDUCTOR APPARATUSES AND METHOD THEREFOR - In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications. | 06-07-2012 |
| 20120138900 | Omega Shaped Nanowire Tunnel Field Effect Transistors - A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region. | 06-07-2012 |
| 20120145997 | PRODUCTION OF VERTICAL ARRAYS OF SMALL DIAMETER SINGLE-WALLED CARBON NANOTUBES - A hot filament chemical vapor deposition method has been developed to grow at least one vertical single-walled carbon nanotube (SWNT). In general, various embodiments of the present invention disclose novel processes for growing and/or producing enhanced nanotube carpets with decreased diameters as compared to the prior art. | 06-14-2012 |
| 20120145998 | Local Bottom Gates for Graphene and Carbon Nanotube Devices - Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided. | 06-14-2012 |
| 20120153262 | Systems and process for forming carbon nanotube sensors - A process for forming a functionalized sensor for sensing a molecule of interest includes providing at least one single or multi-wall carbon nanotube having a first and a second electrode in contact therewith on a substrate; providing a third electrode including a decorating material on the substrate a predetermined distance from the at least one single or multi-wall carbon nanotube having a first and a second electrode in contact therewith, wherein the decorating material has a bonding affinity for a bioreceptors that react with the molecule of interest; and applying a voltage to the third electrode, causing the decorating material to form nanoparticles of the decorating material on the at least one single or multi-wall carbon nanotube. | 06-21-2012 |
| 20120153263 | TUNNEL FIELD EFFECT TRANSISTOR - The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor. | 06-21-2012 |
| 20120187375 | Deposition On A Nanowire Using Atomic Layer Deposition - In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire. | 07-26-2012 |
| 20120187376 | TUNNEL FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME - A tunnel field effect transistor is capable of operating at a low subthreshold and is able to be manufactured easily. The tunnel field effect transistor includes a group IV semiconductor substrate having a (111) surface and doped so as to have a first conductivity type, a group III-V compound semiconductor nanowire arranged on the (111) surface and containing a first region connected to the (111) surface and a second region doped so as to have a second conductivity type, a source electrode connected to the group IV semiconductor substrate; a drain electrode connected to the second region, and a gate electrode for applying an electric field to an interface between the (111) surface and the group III-V compound semiconductor nanowire, or an interface between the first region and the second region. | 07-26-2012 |
| 20120193609 | GERMANIUM-BASED QUANTUM WELL DEVICES - A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric. | 08-02-2012 |
| 20120199814 | SILICON-BASED TUNNELING FIELD EFFECT TRANSISTORS AND TRANSISTOR CIRCUITRY EMPLOYING SAME - A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (u) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (u) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature (500 degrees Centigrade) molecular beam epitaxy. | 08-09-2012 |
| 20120205626 | SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP - A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device. | 08-16-2012 |
| 20120205627 | SEMICONDUCTOR SWITCHING CIRCUIT EMPLOYING QUANTUM DOT STRUCTURES - A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided. | 08-16-2012 |
| 20120211726 | Forming A Non-Planar Transistor Having A Quantum Well Channel - In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed. | 08-23-2012 |
| 20120217479 | Nanowire Mesh FET with Multiple Threshold Voltages - Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels. | 08-30-2012 |
| 20120223292 | Multilayer-Interconnection First Integration Scheme for Graphene and Carbon Nanotube Transistor Based Integration - Integrated circuit multilayer integration techniques are provided. In one aspect, a method of fabricating an integrated circuit is provided. The method includes the following steps. A substrate is provided. A plurality of interconnect layers are formed on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack. At least one transistor is formed on a top-most layer of the stack. | 09-06-2012 |
| 20120273760 | Bipolar Transistor with Lateral Emitter and Collector and Method of Production - A bipolar transistor includes a substrate of semiconductor material, a high-mobility layer in the substrate, and a donor layer adjacent to the high-mobility layer. An emitter terminal forms an emitter contact on the donor layer, and a collector terminal forms a collector contact on the donor layer. A base terminal is electrically conductively connected with the high-mobility layer. The transistor can be produced in a HEMT technology or BiFET technology in GaAs. | 11-01-2012 |
| 20120273761 | Nanowire Tunnel Field Effect Transistors - A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate. | 11-01-2012 |
| 20120280210 | VERTICAL TUNNELING NEGATIVE DIFFERENTIAL RESISTANCE DEVICES - The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry. | 11-08-2012 |
| 20120280211 | A p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors - Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET. | 11-08-2012 |
| 20120298958 | QUANTUM-WELL-BASED SEMICONDUCTOR DEVICES - Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer. | 11-29-2012 |
| 20120326125 | Deposition On A Nanowire Using Atomic Layer Deposition - A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape. | 12-27-2012 |
| 20130001515 | DIRECT GROWTH OF GRAPHENE ON SUBSTRATES - Graphene layers can be formed on a dielectric substrate using a process that includes forming a copper thin film on a dielectric substrate; diffusing carbon atoms through the copper thin film; and forming a graphene layer at an interface between the copper thin film and the dielectric substrate. | 01-03-2013 |
| 20130015428 | Vertical Stacking of Carbon Nanotube Arrays for Current Enhancement and Control - Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided. | 01-17-2013 |
| 20130026449 | Hybrid CMOS Technology with Nanowire Devices and Double Gated Planar Devices - A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member. | 01-31-2013 |
| 20130026450 | NITRIDE-BASED HETEROJUCTION SEMICONDUCTOR DEVICE AND METHOD FOR THE SAME - Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for producing the same. The nitride-based heterojunction semiconductor device includes a nitride semiconductor buffer layer, a barrier layer disposed on the buffer layer, a cap layer discontinuously disposed on the barrier layer, a source electrode and a drain electrode that contact at least one of the barrier layer and the cap layer, and a gate electrode that Schottky-contacts at least one of the barrier layer and the cap layer and is disposed between the source electrode and the drain electrode. | 01-31-2013 |
| 20130026451 | Hybrid CMOS Technology With Nanowire Devices and Double Gated Planar Devices - A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member. | 01-31-2013 |
| 20130032783 | NON-PLANAR GERMANIUM QUANTUM WELL DEVICES - Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 02-07-2013 |
| 20130069040 | ORGANIC NANOFIBER STRUCTURE BASED ON SELF-ASSEMBLED ORGANOGEL, ORGANIC NANOFIBER TRANSISTOR USING THE SAME, AND METHOD OF MANUFACTURING THE ORGANIC NANOFIBER TRANSISTOR - An organic nanofiber including a gelled organic semiconductor compound. Also disclosed is an organic semiconductor transistor and a method of manufacturing an organic semiconductor transistor. | 03-21-2013 |
| 20130099204 | CARBON NANOTUBE TRANSISTOR EMPLOYING EMBEDDED ELECTRODES - Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance. | 04-25-2013 |
| 20130105763 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 05-02-2013 |
| 20130119347 | SEMICONDUCTOR DEVICE INCLUDING GROUP III-V BARRIER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well. | 05-16-2013 |
| 20130126830 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
| 20130146845 | TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS - Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material. | 06-13-2013 |
| 20130187129 | SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE - A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions. | 07-25-2013 |
| 20130207079 | Tapered Nanowire Structure With Reduced Off Current - Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents. | 08-15-2013 |
| 20130207080 | BILAYER GATE DIELECTRIC WITH LOW EQUIVALENT OXIDE THICKNESS FOR GRAPHENE DEVICES - A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer. | 08-15-2013 |
| 20130221328 | Pad-Less Gate-All Around Semiconductor Nanowire FETs On Bulk Semiconductor Wafers - A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region. | 08-29-2013 |
| 20130228750 | THIN FILM TRANSISTOR METHOD OF FABRICATING THE SAME - A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both side portions, the source electrode and the drain electrode electrically connected to the silicon nanowire, respectively. | 09-05-2013 |
| 20130228751 | NANOWIRE DEVICES - A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device. | 09-05-2013 |
| 20130234114 | Graphene Channel-Based Devices and Methods for Fabrication Thereof - Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel. | 09-12-2013 |
| 20130240838 | INCREASING CARRIER INJECTION VELOCITY FOR INTEGRATED CIRCUIT DEVICES - Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed. | 09-19-2013 |
| 20130264544 | NANOWIRE FIELD-EFFECT DEVICE WITH MULTIPLE GATES - The present invention relates to a semiconductor device ( | 10-10-2013 |
| 20130328016 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 12-12-2013 |
| 20130341595 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening. | 12-26-2013 |
| 20140008616 | TRANSISTOR DEVICE AND MATERIALS FOR MAKING - This application relates to graphene based heterostructures and transistor devices comprising graphene. The hetero-structures comprise i) a first graphene layer; ii) a spacer layer and iii) a third graphene. The transistors comprise (i) an electrode, the electrode comprising a graphene layer, and (ii) an insulating barrier layer. | 01-09-2014 |
| 20140014903 | VERTICAL TUNNELING NEGATIVE DIFFERENTIAL RESISTANCE DEVICES - The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry. | 01-16-2014 |
| 20140021443 | NANO RESONATOR AND MANUFACTURING METHOD THEREOF - A nano resonator includes a substrate, a first insulating layer disposed on the substrate, a first source disposed on the first insulating layer at a first position, a first drain disposed on the first insulating layer at a second position spaced apart from the first position so that the first drain faces the first source, a first nano-wire channel having a first end connected to the first source and a second end connected to the first drain, and having a doping type and a doping concentration that are identical to a doping type and a doping concentration of the first source and the first drain, and a second nano-wire channel disposed at a predetermined distance from the first nano-wire channel in a direction perpendicular to the substrate or a direction parallel to the substrate. | 01-23-2014 |
| 20140021444 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device includes a carbon layer including graphene or graphite and a thin film formed on the carbon layer. The electronic device may further include a drain electrode, a source electrode and/or a gate electrode formed on the thin film. A method of manufacturing an electronic device includes preparing a carbon layer including graphene or graphite, forming a nanostructure on the carbon layer, and forming a thin film to cover the nanostructure. | 01-23-2014 |
| 20140034905 | Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width - Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX. Nanowire cores and pads are etched in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial shells are formed surrounding each of the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores/epitaxial shells, wherein the portions of the nanowire cores/epitaxial shells surrounded by the gate stack serve as channels of the device, and wherein the pads and portions of the nanowire cores/epitaxial shells that extend out from the gate stack serve as source and drain regions of the device. | 02-06-2014 |
| 20140034906 | CARBON NANOTUBE SEMICONDUCTOR DEVICES AND DETERMINISTIC NANOFABRICATION METHODS - Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications. | 02-06-2014 |
| 20140034907 | NANOWIRE SENSOR HAVING NANOWIRE OF NETWORK STRUCTURE - A nanowire sensor having a nanowire in a network structure includes: source and drain electrodes formed over a substrate; a nanowire formed between the source and drain electrodes and having a network structure in which patterns of intersections are repeated; and a detection material fixed to the nanowire and selectively reacting with a target material introduced from outside. | 02-06-2014 |
| 20140042392 | DOUBLE CONTACTS FOR CARBON NANOTUBES THIN FILM DEVICES - A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled. | 02-13-2014 |
| 20140054546 | Dynamic Random Access Memory Unit And Method For Fabricating The Same - A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer. | 02-27-2014 |
| 20140054547 | DEVICE WITH STRAINED LAYER FOR QUANTUM WELL CONFINEMENT AND METHOD FOR MANUFACTURING THEREOF - The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer. | 02-27-2014 |
| 20140054548 | TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES - Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 02-27-2014 |
| 20140061589 | GERMANIUM-BASED QUANTUM WELL DEVICES - A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric. | 03-06-2014 |
| 20140084246 | SEMICONDUCTOR DEVICE HAVING GERMANIUM ACTIVE LAYER WITH UNDERLYING PARASITIC LEAKAGE BARRIER LAYER - Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack. | 03-27-2014 |
| 20140084247 | THRESHOLD ADJUSTMENT FOR QUANTUM DOT ARRAY DEVICES WITH METAL SOURCE AND DRAIN - Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase V | 03-27-2014 |
| 20140084248 | METHODS OF FORMING STRUCTURES HAVING NANOTUBES EXTENDING BETWEEN OPPOSING ELECTRODES AND STRUCTURES INCLUDING SAME - A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed. | 03-27-2014 |
| 20140110669 | NON-PLANAR QUANTUM WELL DEVICE HAVING INTERFACIAL LAYER AND METHOD OF FORMING SAME - Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 04-24-2014 |
| 20140124736 | CARBON NANOTUBE TRANSISTOR EMPLOYING EMBEDDED ELECTRODES - Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance. | 05-08-2014 |
| 20140131660 | UNIAXIALLY STRAINED NANOWIRE STRUCTURE - Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions. | 05-15-2014 |
| 20140151637 | TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region. | 06-05-2014 |
| 20140158985 | SEMICONDUCTOR HETEROSTRUCTURE FIELD EFFECT TRANSISTOR AND METHOD FOR MAKING THEREOF - A heterostructure field effect transistor is provided comprising a semiconductor wire comprising in its longitudinal direction a source and a drain region, a channel region in between the source and drain region and in its transversal direction for the source region, a source core region and a source shell region disposed around the source core region, the source shell region having in its transversal direction for the drain region, a drain core region and a drain shell region disposed around the drain core region, the drain shell region having in its transversal direction for the channel region, a channel core region and a channel shell region disposed around the channel core region; wherein the thickness of the channel shell region is smaller than the thickness of the source shell region and is smaller than the thickness of the drain shell region. | 06-12-2014 |
| 20140166981 | VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION - Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length. | 06-19-2014 |
| 20140183451 | FIELD EFFECT TRANSISTOR WITH CHANNEL CORE MODIFIED TO REDUCE LEAKAGE CURRENT AND METHOD OF FABRICATION - A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode. A source structure is connected to one end of the channel structure, and a drain structure is connected to the other end of the channel structure. The channel structure has a non-uniform composition, in a cross-sectional view, that provides a reduction of a leakage current of the semiconductor device relative to a leakage current that would result from a uniform composition | 07-03-2014 |
| 20140183452 | FIELD EFFECT TRANSISTOR WITH CHANNEL CORE MODIFIED FOR A BACKGATE BIAS AND METHOD OF FABRICATION - A semiconductor device includes a substrate and a source structure and a drain structure formed on the substrate. At least one nanowire structure interconnects the source structure and drain structure and serves as a channel therebetween. A gate structure is formed over said at least one nanowire structure to provide a control of a conductivity of carriers in the channel, and the nanowire structure includes a center core serving as a backbias electrode for the channel. | 07-03-2014 |
| 20140197376 | Semiconductor Device - The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application. | 07-17-2014 |
| 20140203243 | THREE-DIMENSIONAL QUANTUM WELL TRANSISTOR AND FABRICATION METHOD - Three dimensional quantum well transistors and fabrication methods are provided. A quantum well layer, a barrier layer, and a gate structure can be sequentially formed on an insulating surface of a fin part. The gate structure can be formed over the barrier layer and across the fin part. The QW layer and the barrier layer can form a hetero-junction of the transistor. A recess can be formed in the fin part on both sides of the gate structure to suspend a sidewall spacer. A source and a drain can be formed by growing an epitaxial material in the recess and the sidewall spacer formed on both sidewalls of the gate electrode can be positioned on surface of the source and the drain. | 07-24-2014 |
| 20140239254 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A system is provided and includes a wafer and a mask. The wafer includes a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer and has a first region with a first SOI thickness and a second region with a second SOI thickness, the first and second SOI thicknesses being different from one another and sufficiently large such that respective pairs of SOI pads connected via respective nanowires with different thicknesses are formable therein. The mask covers one of the first and second regions and prevents a thickness change of the other of the first and second regions from having effect at the one of the first and second regions. | 08-28-2014 |
| 20140239255 | INTEGRATED CIRCUIT DEVICES AND FABRICATING METHOD THEREOF - An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors. | 08-28-2014 |
| 20140252315 | SINGLE ELECTRON TRANSISTOR HAVING NANOPARTICLES OF UNIFORM PATTERN ARRANGEMENT AND METHOD FOR FABRICATING THE SAME - A transistor and a fabrication method thereof. A transistor includes a channel region including linkers, formed on a substrate, and metallic nanoparticles grown from metal ions bonded to the linkers, a source region disposed at one end of the channel region, a drain region disposed at the other end of the channel region opposite of the source region, and a gate coupled to the channel region and serving to control migration of charges in the channel region. The metallic nanoparticles have a substantially uniform pattern arrangement in the channel region. | 09-11-2014 |
| 20140252316 | QUANTUM DOTS, RODS, WIRES, SHEETS, AND RIBBONS, AND USES THEREOF - Described are Zn | 09-11-2014 |
| 20140264276 | NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS - A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region. | 09-18-2014 |
| 20140264277 | Intra-Band Tunnel FET - The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled. | 09-18-2014 |
| 20140264278 | Strained InGaAs Quantum Wells for Complementary Transistors - An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials. | 09-18-2014 |
| 20140319466 | ELECTROCHEMICALLY-GATED FIELD-EFFECT TRANSISTOR, METHODS FOR ITS MANUFACTURE, ITS USE, AND ELECTRONICS COMPRISING SAID FIELD-EFFECT TRANSISTOR - An electrochemically-gated field-effect transistor includes a source electrode, a drain electrode, a gate electrode, a transistor channel and an electrolyte. The transistor channel is located between the source electrode and the drain electrode. The electrolyte completely covers the transistor channel and has a one-dimensional nanostructure and a solid polymer-based electrolyte that is employed as the electrolyte. | 10-30-2014 |
| 20140326952 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 11-06-2014 |
| 20140326953 | TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS - Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material. | 11-06-2014 |
| 20140353588 | QUANTUM INTERFERENCE DEVICE - A device to produce an output based on interference of electron waves is disclosed. Said device comprised out of two areas having different medium properties for propagation of an electron wave, where the first of said areas is connected to a source to inject electrons and the second of said areas is connected to a drain to collect electrons while said electrons have a propagation path through the device starting at the source and ending at the drain. Said areas are designed in a manner to result in advancing and reflected waves having interleaved sections along said path which yield interference, either constructive or destructive, thus determining the transport probability of the electron through the device. Said device is operated either as a switch, in a first embodiment, by adding a control gate, or as a detector, in a second embodiment, used for measurement of external particle ensemble properties. | 12-04-2014 |
| 20150014630 | TUNNELING DEVICES AND METHODS OF MANUFACTURING THE SAME - A tunneling device may include a tunnel barrier layer, a first material layer including a first conductivity type two-dimensional material on a first surface of the tunnel barrier layer and a second material layer including a second conductivity type two-dimensional material on a second surface of the tunnel barrier layer. The tunneling device may use a tunneling current through the tunnel barrier layer between the first material layer and the second material layer. | 01-15-2015 |
| 20150014631 | GALLIUM NITRIDE NANOWIRE BASED ELECTRONICS - GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics. | 01-15-2015 |
| 20150014632 | Advanced Heterojunction Devices and Methods of Manufacturing Advanced Heterojunction Devices - Methods of manufacture of advanced electronic and photonic structures including heterojunction transistors, transistor lasers and solar cells and their related structures, are described herein. Other embodiments are also disclosed herein. | 01-15-2015 |
| 20150034905 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor device is provided. The method includes forming a substrate structure, wherein the substrate structure includes a substrate and a fin-shaped barrier layer formed on a surface of the substrate; forming a quantum well (QW) material layer on a surface of the fin-shaped barrier layer; and forming a barrier material layer on the QW material layer. | 02-05-2015 |
| 20150034906 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method for fabricating the same are disclosed. In the method, a substrate structure is provided, including a substrate and a fin-shaped buffer layer formed on the surface of the substrate. A QW material layer is formed on the surface of the fin-shaped buffer layer. A barrier material layer is formed on the QW material layer. The QW material layer is suitable for forming an electron gas therein. Thereby the short-channel effect is improved, while high mobility of the semiconductor device is guaranteed. In addition, according to the present disclosure, thermal dissipation of the semiconductor device may be improved, and thus performance and stability of the device may be improved. | 02-05-2015 |
| 20150041763 | CARBON NANOTUBE DEVICE - Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided. | 02-12-2015 |
| 20150041764 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening. | 02-12-2015 |
| 20150053925 | Top-Down Fabrication Method for Forming a Nanowire Transistor Device - The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions. | 02-26-2015 |
| 20150060766 | TUNNELING FIELD EFFECT TRANSISTORS - In another embodiment, the tunneling field effect TFET includes a source electrode, a drain electrode, and a channel layer between the source electrode and the drain electrode. A first junction surface is between the source electrode and the channel layer, and a second junction surface is between the drain electrode and the channel layer. A gate is on the channel layer. The gate has first and second side surfaces. The first side surface is at the source electrode side and the second side surface is at the drain electrode side. The first side surface extends from the channel layer. | 03-05-2015 |
| 20150060767 | NANOWIRES AND NANOWIRE FIELDE-EFFECT TRANSISTORS - A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section. | 03-05-2015 |
| 20150069328 | STACKED NANOWIRE DEVICE WITH VARIABLE NUMBER OF NANOWIRE CHANNELS - A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack. | 03-12-2015 |
| 20150083999 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 03-26-2015 |
| 20150084000 | Forming A Non-Planar Transistor Having A Quantum Well Channel - In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed. | 03-26-2015 |
| 20150097158 | VERTICAL TUNNELING NEGATIVE DIFFERENTIAL RESISTANCE DEVICES - The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry. | 04-09-2015 |
| 20150137073 | NANOWIRE DEVICES - A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device. | 05-21-2015 |
| 20150144880 | NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF - A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire. | 05-28-2015 |
| 20150303289 | NANOWIRE ELECTRIC FIELD EFFECT SENSOR HAVING THREE-DIMENSIONAL STACKING STRUCTURE NANOWIRE AND MANUFACTURING METHOD THEREFOR - The present invention provides a nanowire sensor comprising nanowires, in which the nanowires are stacked to form a three-dimensional structure so that they have a large exposed surface area compared to that of a conventional straight nanowire sensor in the same limited area, thereby increasing the probability of attachment of a target material to the nanowires to thereby increase the measurement sensitivity of the sensor. Thus, a change in the electrical conductivity (conductance or resistance) of the nanowires can be sensed with higher sensitivity, suggesting that the sensor has increased sensitivity. | 10-22-2015 |
| 20150333123 | FERROMAGNET-FREE SPIN TRANSISTOR AND METHOD FOR OPERATING THE SAME - A spin transistor includes: an input part that is made of a material exhibiting a spin Hall effect and configured to transfer electrons with a predetermined direction of spin to a connecting part; and the connecting part that receives the electrons with the predetermined direction of spin from the input part, rotates the spin of the electrons in accordance with a gate voltage applied to the gate electrode, and transfers the electrons to the output part. | 11-19-2015 |
| 20150333162 | METHODS OF FORMING NANOWIRE DEVICES WITH METAL-INSULATOR-SEMICONDUCTOR SOURCE/DRAIN CONTACTS AND THE RESULTING DEVICES - A device includes a gate structure and a nanowire channel structure positioned under the gate structure. The nanowire channel structure includes first and second end surfaces. The device further includes a first insulating liner positioned on the first end surface and a second insulating liner positioned on the second end surface. The device further includes a metal-containing source contact positioned on the first insulating liner and a metal-containing drain contact positioned on the second insulating liner. | 11-19-2015 |
| 20150333163 | HIGH PERFORMANCE TOPOLOGICAL INSULATOR TRANSISTORS - Topological insulators, such as single-crystal Bi | 11-19-2015 |
| 20150348968 | Methods and Apparatus for Artificial Exciton in CMOS Processes - Methods and apparatus for artificial exciton devices. An artificial exciton device includes a semiconductor substrate; at least one well region doped to a first conductivity type in a portion of the semiconductor substrate; a channel region in a central portion of the well region; a cathode region in the well region doped to a second conductivity type; an anode region in the well region doped to the first conductivity type; a first lightly doped drain region disposed between the cathode region and the channel region doped to the first conductivity type; a second lightly doped drain region disposed between the anode region and the channel region doped to the second conductivity type; and a gate structure overlying the channel region, the gate structure comprising a gate dielectric layer lying over the channel region and a gate conductor material overlying the gate dielectric. Methods are disclosed. | 12-03-2015 |
| 20150357432 | SYSTEMS AND METHODS FOR FABRICATING VERTICAL-GATE-ALL-AROUND DEVICES - Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region. | 12-10-2015 |
| 20150364545 | ELECTRONIC DEVICE INCLUDING GRAPHENE AND QUANTUM DOTS - According to example embodiments, an electronic device includes channel layer including a graphene layer electrically contacting a quantum dot layer including a plurality of quantum dots, a first electrode and a second electrode electrically connected to the channel layer, respectively, and a gate electrode configured to control an electric current between the first electrode and the second electrode via the channel layer. A gate insulating layer may be between the gate electrode and the channel layer. | 12-17-2015 |
| 20160005849 | METHOD AND APPARATUS FOR 3D CONCURRENT MULTIPLE PARALLEL 2D QUANTUM WELLS - An inner fin of a high bandgap material is on a substrate, having two vertical faces, and is surrounded by a carrier redistribution fin of a low bandgap material. The inner fin and the carrier redistribution fin have two vertical interfaces. The carrier redistribution fin has a thickness and a bandgap relative to the bandgap of the inner fin that establishes, along the two vertical interfaces, an equilibrium of a corresponding two two-dimensional electron gasses. | 01-07-2016 |
| 20160005881 | STACKED FILMS AND METHOD FOR PRODUCING STACKED FILMS - Stacked films includes mica, a self-assembled film and a graphene film. The self-assembled film is formed on the mica. The graphene film is formed over the self-assembled film. The molecules that make up the self-assembled film have hydrophobic main chains. | 01-07-2016 |
| 20160020312 | FIELD EFFECT TRANSISTOR WITH CHANNEL CORE MODIFIED TO REDUCE LEAKAGE CURRENT AND METHOD OF FABRICATION - A method of fabricating a semiconductor device with a reduced leakage method includes forming a channel structure on a substrate, the channel structure having a non-uniform composition, in a cross-sectional view, that comprises a core region and a peripheral region. An etch rate of the core region differs from an etch rate of the peripheral region. A source structure connected to one end of the channel structure is formed, and a drain structure connected to the other end of the channel structure is formed. At least a portion of the core region is electively etched and a gate structure to cover at least a portion of a surface of the channel structure, is formed, the gate structure comprising a film of insulation material and a gate electrode. | 01-21-2016 |
| 20160020317 | Non-Planar Quantum Well Device Having Interfacial Layer and Method of Forming Same - Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 01-21-2016 |
| 20160020352 | OPTOELECTRONIC APPARATUS AND FABRICATION METHOD OF THE SAME - An optoelectronic apparatus, such as a photodetector apparatus comprising a substrate ( | 01-21-2016 |
| 20160027908 | LOGICAL OPERATION ELEMENT - Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element | 01-28-2016 |
| 20160043207 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device comprising: an insulation substrate; an intrinsic semiconductor nanowire formed on the insulation substrate and having both ends doped in a p-type and an n-type, respectively and a region, which is not doped, between the doped region; doped region electrodes formed on each of the p-type doped region and the n-type doped region of the semiconductor nanowire; a lower insulation layer formed on an intrinsic region of the semiconductor nanowire; an intrinsic region electrode formed on a part of the lower insulation layer; and a metal or semiconductor nanoparticle region formed on the lower insulation layer and between the intrinsic region electrode and the doped region electrode and spaced apart from the electrodes. | 02-11-2016 |
| 20160093613 | EPITAXIALLY GROWN QUANTUM WELL FINFETS FOR ENHANCED PFET PERFORMANCE - A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100} crystallographic oriented substrate; forming a conformal well on the fins using epitaxial growth; and forming a conformal barrier on the conformal well using epitaxial growth. | 03-31-2016 |
| 20160111423 | EXTREME HIGH MOBILITY CMOS LOGIC - A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. | 04-21-2016 |
| 20160118608 | SINGLE ELECTRON TRANSISTOR HAVING NANOPARTICLES OF UNIFORM PATTERN ARRANGEMENT AND METHOD FOR FABRICATING THE SAME - A transistor and a fabrication method thereof. A transistor includes a channel region including linkers, formed on a substrate, and metallic nanoparticles grown from metal ions bonded to the linkers, a source region disposed at one end of the channel region, a drain region disposed at the other end of the channel region opposite of the source region, and a gate coupled to the channel region and serving to control migration of charges in the channel region. The metallic nanoparticles have a substantially uniform pattern arrangement in the channel region. | 04-28-2016 |
| 20160126341 | Field Effect Transistor with Conduction Band Electron Channel and Uni-Terminal Response - A uni-terminal transistor device is described. In one embodiment, an n-channel transistor having p-terminal characteristics comprises a first semiconductor layer having a discrete hole level; a second semiconductor layer having a conduction band whose minimum level is lower than that of the first semiconductor layer; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level below the minimum level of the conduction band of the second semiconductor layer for zero bias applied to the gate metal layer and to obtain p-terminal characteristics. | 05-05-2016 |
| 20160149001 | GRADED HETEROJUNCTION NANOWIRE DEVICE - A device includes a source region, a drain region, and a semiconductor channel connecting the source region to the drain region. The semiconductor channel includes a source-side channel portion adjoining the source region, wherein the source-side channel portion has a first bandgap, and a drain-side channel portion adjoining the drain region. The drain-side channel portion has a second bandgap different from the first bandgap. | 05-26-2016 |
| 20160149022 | HETEROJUNCTION FIELD EFFECT TRANSISTOR (HFET) VARIABLE GAIN AMPLIFIER HAVING VARIABLE TRANSCONDUCTANCE - A heterojunction semiconductor field effect transistor HFET having a pair of layers of different semiconductor materials forming a quantum well within the structure to support the 2DEG. Source, drain and gate electrodes are disposed above the channel. The HFET has a predetermined transconductance. A transconductance control electrode varies an electric field within the structure under the channel to vary the shape of the quantum well and thereby the transconductance of the FET in accordance with a variable control signal fed to the transconductance control electrode. | 05-26-2016 |
| 20160163843 | Quantum Well Fin-Like Field Effect Transistor (QWFINFET) Having a Two-Section Combo QW Structure - The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure. | 06-09-2016 |
| 20160163844 | Method and Structure for III-V FinFET - A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the Ill-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension. | 06-09-2016 |
| 20160181407 | METHOD TO FABRICATE QUANTUM DOT FIELD-EFFECT TRANSISTORS WITHOUT BIAS-STRESS EFFECT | 06-23-2016 |
| 20160254384 | FETs and Methods for Forming the Same | 09-01-2016 |
| 20190148555 | FETs and Methods for Forming the Same | 05-16-2019 |
